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4ec5c19
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fix outline layer to not trigger DRC errors
author
Bdale Garbee
<bdale@gag.com>
Sun, 14 Jul 2013 06:55:29 +0000
(
02:55
-0400)
committer
Bdale Garbee
<bdale@gag.com>
Sun, 14 Jul 2013 06:55:29 +0000
(
02:55
-0400)
lipocharger.pcb
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diff --git
a/lipocharger.pcb
b/lipocharger.pcb
index d51255b479e247d374d0c3eebd93c233b0d90cf3..77d5f99239ee3691574c50d59aaceeb1389e94a7 100644
(file)
--- a/
lipocharger.pcb
+++ b/
lipocharger.pcb
@@
-995,6
+995,7
@@
Layer(2 "bottom")
)
Layer(3 "outline")
(
+ Attribute("PCB::skip-drc" "1")
Line[0.0000 0.0000 0.0000 400.00mil 10.00mil 0.0000 ""]
Line[0.0000 400.00mil 1000.00mil 400.00mil 10.00mil 0.0000 ""]
Line[1000.00mil 400.00mil 1000.00mil 0.0000 10.00mil 0.0000 ""]