SFR(DPH, 0x83); // Data Pointer High.\r
\r
SFR(DPTC, 0x85); // Data Pointer Control Register.\r
+SFR(DPS, 0x85); // Data Pointer Control Register alias for SDCC\r
#define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1\r
#define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR\r
\r
#define TCLK1 0x04 //Transmit Clock Flag (UART1)\r
#define PD 0x02 //Power-Down Mode Enable.\r
#define IDL 0x01 //Idle Mode Enable.\r
- \r
+\r
SFR(TCON, 0x88); // Timer/Counter Control.\r
SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.\r
SBIT(TR1, 0x88, 6); // Timer 1 run control flag.\r
SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.\r
SBIT(IE0, 0x88, 1); // Interrupt 0 flag.\r
SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.\r
- \r
+\r
SFR(TMOD, 0x89); // Timer/Counter Mode Control.\r
#define GATE1 0x80 // External enable for timer 1.\r
#define C_T1 0x40 // Timer or counter select for timer 1.\r
SBIT(SPIRXD, 0x90, 5);\r
SBIT(SPITXD, 0x90, 6);\r
SBIT(SPISEL, 0x90, 7);\r
- \r
+\r
SFR(P3SFS, 0x91); // Port 3 Special Function Select Register\r
#define P3SF7 0x80\r
#define P3SF6 0x40\r
#define P4SF12 0x04\r
#define P4SF11 0x02\r
#define P4SF10 0x01\r
- \r
+\r
SFR(ADCPS, 0x94); // ADC pre-scaller?\r
#define ADCCE 0x08 // ADC Conversion Reference Clock Enable.\r
//ADC Reference Clock PreScaler. Only three Prescaler values are allowed:\r
#define ADCPS2 0x02 // Resulting ADC clock is fOSC.\r
#define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.\r
#define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.\r
- \r
+\r
SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).\r
SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).\r
SFR(ACON, 0x97); // A/D control register.\r
#define ADS0 0x04 // Analog channel Select bit 1.\r
#define ADST 0x02 // ADC Start Bit.\r
#define ADSF 0x01 // ADC Status Bit.\r
- \r
+\r
SFR(SCON, 0x98); // For compatibity with legacy code\r
SFR(SCON0, 0x98); // Serial Port UART0 Control Register\r
SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.\r
#define RDW0 0x04 // RD Wait bit 1.\r
#define CW1 0x02 // PSEN Wait bit 2.\r
#define CW0 0x01 // PSEN Wait bit 1.\r
- \r
+\r
SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter.\r
SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter.\r
SFR(PCACON0, 0xA4); // PCA 0 Control Register.\r
#define EI2C 0x02 // Enable I2C Interrupt.\r
\r
SFR(IE, 0xA8); // Interrupt Enable Register.\r
- SBIT(EA, 0xA8, 7); // Global disable bit. \r
+ SBIT(EA, 0xA8, 7); // Global disable bit.\r
SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.\r
SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.\r
SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.\r
SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.\r
SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.\r
SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.\r
- \r
+\r
SFR(TCMMODE0, 0xA9); // TCM 0 Mode.\r
SFR(TCMMODE1, 0xAA); // TCM 1 Mode.\r
SFR(TCMMODE2, 0xAB); // TCM 2 Mode.\r
#define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin.\r
#define PWM1 0x02 // PWM mode bit 2.\r
#define PWM0 0x01 // PWM mode bit 1.\r
- \r
+\r
SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.\r
SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.\r
SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.\r
#define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.\r
#define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.\r
#define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.\r
- \r
+\r
SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.\r
#define PCA0CE 0x10 // PCA0 Clock Enable.\r
#define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.\r
#define DIV16 0x10\r
#define DIV8 0x08\r
#define DIV4 0x04\r
- \r
+\r
SFR(SPISTAT, 0xD3); // SPI Interface Status Register.\r
#define BUSY 0x10 // SPI Busy.\r
#define TEISF 0x08 // Transmission End Interrupt Source flag.\r
#define RORISF 0x04 // Receive Overrun Interrupt Source flag.\r
#define TISF 0x02 // Transfer Interrupt Source flag.\r
#define RISF 0x01 // Receive Interrupt Source flag.\r
- \r
+\r
SFR(SPITDR, 0xD4); // SPI transmit data register.\r
SFR(SPIRDR, 0xD5); // SPI receive data register.\r
\r
#define SSEL 0x08 // Slave Selection.\r
#define FLSB 0x04 // First LSB.\r
#define SPO 0x02 // Sampling Polarity.\r
- \r
+\r
SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.\r
#define TEIE 0x08 // Transmission End Interrupt Enable.\r
#define RORIE 0x04 // Receive Overrun Interrupt Enable.\r
; /*-------------------------------------------------------------------------
-;
+;
; crtxinit.asm :- C run-time: copy XINIT to XISEG
-;
+;
; This library is free software; you can redistribute it and/or modify it
; under the terms of the GNU Library General Public License as published by the
; Free Software Foundation; either version 2, or (at your option) any
; later version.
-;
+;
; This library is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU Library General Public License for more details.
-;
+;
; You should have received a copy of the GNU Library General Public License
; along with this program; if not, write to the Free Software
; Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-;
+;
; In other words, you are welcome to use, share and improve this program.
; You are forbidden to forbid anyone else to use, share and improve
-; what you give them. Help stamp out software-hoarding!
+; what you give them. Help stamp out software-hoarding!
; -------------------------------------------------------------------------*/
+; Set DUAL_DPTR to 1 and reassemble if your derivative has dual data pointers
+; Especially useful if movx @Ri cannot go beyond the first 256 bytes of xdata
+; due to lack of P2 or _XPAGE
+; If the derivative has auto-toggle or auto-increment it can be further optimized
+ DUAL_DPTR = 0
+
.area CSEG (CODE)
.area GSINIT0 (CODE)
.area GSINIT1 (CODE)
.area GSINIT (CODE)
.area GSFINAL (CODE)
- .globl __XPAGE
-
.area GSINIT3 (CODE)
-
+
+ .if DUAL_DPTR
+
+ .globl _DPS ; assume DPSEL is in DPS bit0
+
+__mcs51_genXINIT::
+ mov r1,#l_XINIT
+ mov a,r1
+ orl a,#(l_XINIT >> 8)
+ jz 00003$
+ mov r2,#((l_XINIT+255) >> 8)
+ orl _DPS,#0x01 ; set DPSEL, select DPTR1
+ mov dptr,#s_XINIT ; DPTR1 for code
+ dec _DPS ; clear DPSEL, select DPTR0
+ mov dptr,#s_XISEG ; DPTR0 for xdata
+00001$: clr a
+ inc _DPS ; set DPSEL, select DPTR1
+ movc a,@a+dptr
+ inc dptr
+ dec _DPS ; clear DPSEL, select DPTR0
+ movx @dptr,a
+ inc dptr
+ djnz r1,00001$
+ djnz r2,00001$
+00003$:
+
+ .else
+
+ .globl __XPAGE
+
__mcs51_genXINIT::
mov r1,#l_XINIT
mov a,r1
djnz r2,00001$
mov __XPAGE,#0xFF
00003$:
-
\ No newline at end of file
+
+ .endif
projects / fw / sdcc / commitdiff