--- /dev/null
+/*-------------------------------------------------------------------------\r
+ Register Declarations for ST's uPSD33xx "Fast 8032 MCU with Programmable Logic"\r
+ (Based on preliminary datasheet from Jan/2005 )\r
+\r
+ Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (May 2007)\r
+\r
+ This library is free software; you can redistribute it and/or\r
+ modify it under the terms of the GNU Lesser General Public\r
+ License as published by the Free Software Foundation; either\r
+ version 2.1 of the License, or (at your option); any later version\r
+\r
+ This library is distributed in the hope that it will be useful,\r
+ but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\r
+ Lesser General Public License for more details\r
+\r
+ You should have received a copy of the GNU Lesser General Public\r
+ License along with this library; if not, write to the Free Software\r
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA\r
+\r
+ In other words, you are welcome to use, share and improve this program\r
+ You are forbidden to forbid anyone else to use, share and improve\r
+ what you give them. Help stamp out software-hoarding!\r
+-------------------------------------------------------------------------*/\r
+#ifndef REG_UPSD33XX_H\r
+#define REG_UPSD33XX_H\r
+\r
+#include <compiler.h>\r
+\r
+//Interrupt vector numbers (see table 16 on datasheet)\r
+#define EXT0_INTERRUPT ((0x03-3)/8)\r
+#define TIMER0_INTERRUPT ((0x0B-3)/8)\r
+#define EXT1_INTERRUPT ((0x13-3)/8)\r
+#define TIMER1_INTERRUPT ((0x1B-3)/8)\r
+#define UART0_INTERRUPT ((0x23-3)/8)\r
+#define TIMER2_INTERRUPT ((0x2B-3)/8)\r
+#define TX2_INTERRUPT ((0x2B-3)/8)\r
+#define SPI_INTERRUPT ((0x53-3)/8)\r
+#define I2C_INTERRUPT ((0x43-3)/8)\r
+#define ADC_INTERRUPT ((0x3B-3)/8)\r
+#define PCA_INTERRUPT ((0x5B-3)/8)\r
+#define UART1_INTERRUPT ((0x4B-3)/8)\r
+\r
+SFR(SP, 0x81); // Stack Pointer.\r
+SFR(DPL, 0x82); // Data Pointer Low.\r
+SFR(DPH, 0x83); // Data Pointer High.\r
+\r
+SFR(DPTC, 0x85); // Data Pointer Control Register.\r
+ #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1\r
+ #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR\r
+\r
+SFR(DPTM, 0x86); // Data Pointer Mode Register.\r
+ #define DP1_1 0x08 // DPTR1 Mode Bit 1.\r
+ #define DP1_0 0x04 // DPTR1 Mode Bit 0.\r
+ #define DP0_1 0x02 // DPTR0 Mode Bit 1.\r
+ #define DP0_0 0x01 // DPTR0 Mode Bit 0.\r
+ // DPx_1 DPx_0\r
+ // 0 0 : DPTRx No Change\r
+ // 0 1 : Reserved\r
+ // 1 0 : DPTRx Auto Increment\r
+ // 1 1 : DPTRx Auto Decrement\r
+\r
+SFR(PCON, 0x87); // Power Control.\r
+ #define SMOD0 0x80 //Baud Rate Double Bit (UART0)\r
+ #define SMOD1 0x40 //Baud Rate Double Bit (UART1)\r
+ #define POR 0x10 //Only a power-on reset sets this bit (cold reset).\r
+ #define RCLK1 0x08 //Receive Clock Flag (UART1)\r
+ #define TCLK1 0x04 //Transmit Clock Flag (UART1)\r
+ #define PD 0x02 //Power-Down Mode Enable.\r
+ #define IDL 0x01 //Idle Mode Enable.\r
+ \r
+SFR(TCON, 0x88); // Timer/Counter Control.\r
+ SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.\r
+ SBIT(TR1, 0x88, 6); // Timer 1 run control flag.\r
+ SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.\r
+ SBIT(TR0, 0x88, 4); // Timer 0 run control flag.\r
+ SBIT(IE1, 0x88, 3); // Interrupt 1 flag.\r
+ SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.\r
+ SBIT(IE0, 0x88, 1); // Interrupt 0 flag.\r
+ SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.\r
+ \r
+SFR(TMOD, 0x89); // Timer/Counter Mode Control.\r
+ #define GATE1 0x80 // External enable for timer 1.\r
+ #define C_T1 0x40 // Timer or counter select for timer 1.\r
+ #define M1_1 0x20 // Operation mode bit 1 for timer 1.\r
+ #define M0_1 0x10 // Operation mode bit 0 for timer 1.\r
+ #define GATE0 0x08 // External enable for timer 0.\r
+ #define C_T0 0x04 // Timer or counter select for timer 0.\r
+ #define M1_0 0x02 // Operation mode bit 1 for timer 0.\r
+ #define M0_0 0x01 // Operation mode bit 0 for timer 0.\r
+\r
+SFR(TL0, 0x8A); // Timer 0 LSB.\r
+SFR(TL1, 0x8B); // Timer 1 LSB.\r
+SFR(TH0, 0x8C); // Timer 0 MSB.\r
+SFR(TH1, 0x8D); // Timer 1 MSB.\r
+\r
+//For P1SFS0 and P1SFS1 SFRs details check datasheet Table 31.\r
+SFR(P1SFS0, 0x8E); //Port 1 Special Function Select 0 Register.\r
+ #define P1SF07 0x80\r
+ #define P1SF06 0x40\r
+ #define P1SF05 0x20\r
+ #define P1SF04 0x10\r
+ #define P1SF03 0x08\r
+ #define P1SF02 0x04\r
+ #define P1SF01 0x02\r
+ #define P1SF00 0x01\r
+SFR(P1SFS1, 0x8F); //Port 1 Special Function Select 1 Register.\r
+ #define P1SF17 0x80\r
+ #define P1SF16 0x40\r
+ #define P1SF15 0x20\r
+ #define P1SF14 0x10\r
+ #define P1SF13 0x08\r
+ #define P1SF12 0x04\r
+ #define P1SF11 0x02\r
+ #define P1SF10 0x01\r
+\r
+SFR(P1, 0x90); // Port 1\r
+ SBIT(P1_0, 0x90, 0); // Port 1 bit 0.\r
+ SBIT(P1_1, 0x90, 1); // Port 1 bit 1.\r
+ SBIT(P1_2, 0x90, 2); // Port 1 bit 2.\r
+ SBIT(P1_3, 0x90, 3); // Port 1 bit 3.\r
+ SBIT(P1_4, 0x90, 4); // Port 1 bit 4.\r
+ SBIT(P1_5, 0x90, 5); // Port 1 bit 5.\r
+ SBIT(P1_6, 0x90, 6); // Port 1 bit 6.\r
+ SBIT(P1_7, 0x90, 7); // Port 1 bit 7.\r
+ //Alternate names (from figure 3)\r
+ SBIT(T2, 0x90, 0); //Input to Timer/Counter 2.\r
+ SBIT(T2X, 0x90, 1); //Capture/reload trigger for Counter 2.\r
+ SBIT(RXD1, 0x90, 2);\r
+ SBIT(TXD1, 0x90, 3);\r
+ SBIT(SPICLK, 0x90, 4);\r
+ SBIT(SPIRXD, 0x90, 5);\r
+ SBIT(SPITXD, 0x90, 6);\r
+ SBIT(SPISEL, 0x90, 7);\r
+ \r
+SFR(P3SFS, 0x91); // Port 3 Special Function Select Register\r
+ #define P3SF7 0x80\r
+ #define P3SF6 0x40\r
+ #define P3SF5 0x20\r
+ #define P3SF4 0x10\r
+ #define P3SF3 0x08\r
+ #define P3SF2 0x04\r
+ #define P3SF1 0x02\r
+ #define P3SF0 0x01\r
+\r
+//For P4SFS0 and P4SFS1 SFRs details check datasheet Table 34.\r
+SFR(P4SFS0, 0x92); //Port 4 Special Function Select 0 Register.\r
+ #define P4SF07 0x80\r
+ #define P4SF06 0x40\r
+ #define P4SF05 0x20\r
+ #define P4SF04 0x10\r
+ #define P4SF03 0x08\r
+ #define P4SF02 0x04\r
+ #define P4SF01 0x02\r
+ #define P4SF00 0x01\r
+SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register.\r
+ #define P4SF17 0x80\r
+ #define P4SF16 0x40\r
+ #define P4SF15 0x20\r
+ #define P4SF14 0x10\r
+ #define P4SF13 0x08\r
+ #define P4SF12 0x04\r
+ #define P4SF11 0x02\r
+ #define P4SF10 0x01\r
+ \r
+SFR(ADCPS, 0x94); // ADC pre-scaller?\r
+ #define ADCCE 0x08 // ADC Conversion Reference Clock Enable.\r
+ //ADC Reference Clock PreScaler. Only three Prescaler values are allowed:\r
+ #define ADCPS2 0x02 // Resulting ADC clock is fOSC.\r
+ #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.\r
+ #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.\r
+ \r
+SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).\r
+SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).\r
+SFR(ACON, 0x97); // A/D control register.\r
+ #define AINTF 0x80 // ADC Interrupt flag. This bit must be cleared with software.\r
+ #define AINTEN 0x40 // ADC Interrupt Enable.\r
+ #define ADEN 0x20 // ADC Enable Bit.\r
+ #define ADS2 0x10 // Analog channel Select bit 3.\r
+ #define ADS1 0x08 // Analog channel Select bit 2.\r
+ #define ADS0 0x04 // Analog channel Select bit 1.\r
+ #define ADST 0x02 // ADC Start Bit.\r
+ #define ADSF 0x01 // ADC Status Bit.\r
+ \r
+SFR(SCON, 0x98); // For compatibity with legacy code\r
+SFR(SCON0, 0x98); // Serial Port UART0 Control Register\r
+ SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.\r
+ SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.\r
+ SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.\r
+ SBIT(REN, 0x98, 4); // Enables serial reception.\r
+ SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.\r
+ SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.\r
+ SBIT(TI, 0x98, 1); // Transmit interrupt flag.\r
+ SBIT(RI, 0x98, 0); // Receive interrupt flag.\r
+\r
+SFR(SBUF, 0x99); // For compatibity with legacy code.\r
+SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.\r
+\r
+SFR(BUSCON, 0x9D); // Bus Control Register.\r
+ #define EPFQ 0x80 // Enable Pre-Fetch Queue.\r
+ #define EBC 0x40 // Enable Branch Cache.\r
+ #define WRW1 0x20 // WR Wait bit 2.\r
+ #define WRW0 0x10 // WR Wait bit 1.\r
+ #define RDW1 0x08 // RD Wait bit 2.\r
+ #define RDW0 0x04 // RD Wait bit 1.\r
+ #define CW1 0x02 // PSEN Wait bit 2.\r
+ #define CW0 0x01 // PSEN Wait bit 1.\r
+ \r
+SFR(PCACL0, 0xA2); // The low 8 bits of PCA 0 16-bit counter.\r
+SFR(PCACH0, 0xA3); // The high 8 bits of PCA 0 16-bit counter.\r
+SFR(PCACON0, 0xA4); // PCA 0 Control Register.\r
+SFR(PCASTA, 0xA5); // PCA 0 and PCA 1 Status Register.\r
+SFR(PCACL1, 0xBA); // The low 8 bits of PCA 1 16-bit counter.\r
+SFR(PCACH1, 0xBB); // The high 8 bits of PCA 1 16-bit counter.\r
+SFR(PCACON1, 0xBC); // PCA 1 Control Register.\r
+\r
+SFR(IEA, 0xA7); // Interrupt Enable Addition Register.\r
+ #define EADC 0x80 // Enable ADC Interrupt.\r
+ #define ESPI 0x40 // Enable SPI Interrupt.\r
+ #define EPCA 0x20 // Enable Programmable Counter Array Interrupt.\r
+ #define ES1 0x10 // Enable UART1 Interrupt.\r
+ #define EI2C 0x02 // Enable I2C Interrupt.\r
+\r
+SFR(IE, 0xA8); // Interrupt Enable Register.\r
+ SBIT(EA, 0xA8, 7); // Global disable bit. \r
+ SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.\r
+ SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.\r
+ SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.\r
+ SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.\r
+ SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.\r
+ SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.\r
+ \r
+SFR(TCMMODE0, 0xA9); // TCM 0 Mode.\r
+SFR(TCMMODE1, 0xAA); // TCM 1 Mode.\r
+SFR(TCMMODE2, 0xAB); // TCM 2 Mode.\r
+SFR(TCMMODE3, 0xBD); // TCM 3 Mode.\r
+SFR(TCMMODE4, 0xBE); // TCM 4 Mode.\r
+SFR(TCMMODE5, 0xBF); // TCM 5 Mode.\r
+//These are the bits for the six SFRs above:\r
+ #define EINTF 0x80 // Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.\r
+ #define E_COMP 0x40 // Enable the comparator when set.\r
+ #define CAP_PE 0x20 // Enable Capture Mode, a positive edge on the CEXn pin.\r
+ #define CAP_NE 0x20 // Enable Capture Mode, a negative edge on the CEXn pin.\r
+ #define MATCH 0x08 // A match from the comparator sets the INTF bits in the Status Register.\r
+ #define TOGGLE 0x04 // A match on the comparator results in a toggling output on CEXn pin.\r
+ #define PWM1 0x02 // PWM mode bit 2.\r
+ #define PWM0 0x01 // PWM mode bit 1.\r
+ \r
+SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.\r
+SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.\r
+SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.\r
+SFR(CAPCOMH1, 0xB1); // Capture/Compare register High of TCM 1.\r
+SFR(CAPCOML2, 0xB2); // Capture/Compare register low of TCM 2.\r
+SFR(CAPCOMH2, 0xB3); // Capture/Compare register High of TCM 2.\r
+SFR(CAPCOML3, 0xC1); // Capture/Compare register low of TCM 3.\r
+SFR(CAPCOMH3, 0xC2); // Capture/Compare register High of TCM 3.\r
+SFR(CAPCOML4, 0xC3); // Capture/Compare register low of TCM 4.\r
+SFR(CAPCOMH4, 0xC4); // Capture/Compare register High of TCM 4.\r
+SFR(CAPCOML5, 0xC5); // Capture/Compare register low of TCM 5.\r
+SFR(CAPCOMH5, 0xC6); // Capture/Compare register High of TCM 5.\r
+\r
+SFR(IPA, 0xB7); // Interrupt Priority Addition register.\r
+ #define PADC 0x80 // ADC Interrupt priority level.\r
+ #define PSPI 0x40 // SPI Interrupt priority level.\r
+ #define PPCA 0x20 // PCA Interrupt level.\r
+ #define PS1 0x10 // UART1 Interrupt priority.\r
+ #define PI2C 0x02 // I2C Interrupt priority level.\r
+\r
+SFR(IP, 0xB8); // Interrupt Priority Register.\r
+ SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.\r
+ SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.\r
+ SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.\r
+ SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.\r
+ SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.\r
+ SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.\r
+\r
+SFR(WDTRST, 0xA6); // Watchdog Timer Reset Counter Register.\r
+SFR(WDTKEY, 0xAE); //Watchdog Timer Key Register.\r
+\r
+SFR(P3, 0xB0); // I/O Port 3 Register\r
+ SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.\r
+ SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.\r
+ SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.\r
+ SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.\r
+ SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.\r
+ SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.\r
+ SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.\r
+ SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.\r
+\r
+SFR(P4, 0xC0); // I/O Port 4 Register\r
+ SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.\r
+ SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.\r
+ SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.\r
+ SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.\r
+ SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.\r
+ SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.\r
+ SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.\r
+ SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.\r
+\r
+SFR(PWMF0, 0xB4); // PWM frequency register 0.\r
+SFR(PWMF1, 0xC7); // PWM frequency register 1.\r
+\r
+SFR(T2CON, 0xC8); // Timer / Counter 2 Control.\r
+ SBIT(TF2, 0xC8, 7); // Timer 2 overflow flag.\r
+ SBIT(EXF2, 0xC8, 6); // Timer 2 external flag.\r
+ SBIT(RCLK, 0xC8, 5); // Receive clock flag.\r
+ SBIT(TCLK, 0xC8, 4); // Transmit clock flag.\r
+ SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.\r
+ SBIT(TR2, 0xC8, 2); // Start/stop control for timer 2.\r
+ SBIT(CNT2, 0xC8, 1); // Timer or coutner select.\r
+ SBIT(CAP2, 0xC8, 0); // Capture/reload flag.\r
+\r
+SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.\r
+SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.\r
+SFR(TL2, 0xCC); // Timer 2 LSB.\r
+SFR(TH2, 0xCD); // Timer 2 MSB.\r
+\r
+SFR(IRDACON, 0xCE); //IrDA control register\r
+ #define IRDAEN 0x40 // IrDA Enable bit\r
+ #define PULSE 0x20 // IrDA Pulse Modulation Select. 0: 1.627us, 1: 3/16 bit time pulses.\r
+ #define CDIV4 0x10 //Specify Clock Divider bit 5.\r
+ #define CDIV3 0x08 //Specify Clock Divider bit 4.\r
+ #define CDIV2 0x04 //Specify Clock Divider bit 3.\r
+ #define CDIV1 0x02 //Specify Clock Divider bit 2.\r
+ #define CDIV0 0x01 //Specify Clock Divider bit 1.\r
+\r
+SFR(CCON0, 0xF9); // Clock Control Register.\r
+ #define DBGCE 0x10 // Debug Unit Breakpoint Comparator Enable.\r
+ #define CPUAR 0x08 // Automatic MCU Clock Recovery.\r
+ #define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.\r
+ #define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.\r
+ #define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.\r
+ \r
+SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.\r
+ #define PCA0CE 0x10 // PCA0 Clock Enable.\r
+ #define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.\r
+ #define PCA0PS2 0x04 // PCA0 Pre-Scaler bit 3.\r
+ #define PCA0PS1 0x02 // PCA0 Pre-Scaler bit 2.\r
+ #define PCA0PS0 0x01 // PCA0 Pre-Scaler bit 1.\r
+\r
+SFR(CCON3, 0xFC); // Pre-scaler value for PCA1.\r
+ #define PCA1CE 0x10 // PCA1 Clock Enable.\r
+ #define PCA1PS3 0x08 // PCA1 Pre-Scaler bit 4.\r
+ #define PCA1PS2 0x04 // PCA1 Pre-Scaler bit 3.\r
+ #define PCA1PS1 0x02 // PCA1 Pre-Scaler bit 2.\r
+ #define PCA1PS0 0x01 // PCA1 Pre-Scaler bit 1.\r
+\r
+SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register.\r
+ #define DIV128 0x80\r
+ #define DIV64 0x40\r
+ #define DIV32 0x20\r
+ #define DIV16 0x10\r
+ #define DIV8 0x08\r
+ #define DIV4 0x04\r
+ \r
+SFR(SPISTAT, 0xD3); // SPI Interface Status Register.\r
+ #define BUSY 0x10 // SPI Busy.\r
+ #define TEISF 0x08 // Transmission End Interrupt Source flag.\r
+ #define RORISF 0x04 // Receive Overrun Interrupt Source flag.\r
+ #define TISF 0x02 // Transfer Interrupt Source flag.\r
+ #define RISF 0x01 // Receive Interrupt Source flag.\r
+ \r
+SFR(SPITDR, 0xD4); // SPI transmit data register.\r
+SFR(SPIRDR, 0xD5); // SPI receive data register.\r
+\r
+SFR(SPICON0, 0xD6); // SPI Control Register 0.\r
+ #define TE 0x40 // Transmitter Enable.\r
+ #define RE 0x20 // Receiver Enable.\r
+ #define SPIEN 0x10 // SPI Enable.\r
+ #define SSEL 0x08 // Slave Selection.\r
+ #define FLSB 0x04 // First LSB.\r
+ #define SPO 0x02 // Sampling Polarity.\r
+ \r
+SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.\r
+ #define TEIE 0x08 // Transmission End Interrupt Enable.\r
+ #define RORIE 0x04 // Receive Overrun Interrupt Enable.\r
+ #define TIE 0x02 // Transmission Interrupt Enable.\r
+ #define RIE 0x01 // Reception Interrupt Enable.\r
+\r
+SFR(SCON1, 0x98); // Serial Port Control.\r
+ SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.\r
+ SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.\r
+ SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.\r
+ SBIT(REN, 0x98, 4); // Enables serial reception.\r
+ SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.\r
+ SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.\r
+ SBIT(TI, 0x98, 1); // Transmit interrupt flag.\r
+ SBIT(RI, 0x98, 0); // Receive interrupt flag.\r
+\r
+SFR(SBUF1, 0xD9); // Data buffer for UART1.\r
+SFR(S1SETUP, 0xDB); // I2C START Condition Sample Setup register.\r
+ #define EN_SS 0x80 // Enable Sample Setup.\r
+ #define SMPL_SET6 0x40 // Sample Setting bit 7.\r
+ #define SMPL_SET5 0x20 // Sample Setting bit 6.\r
+ #define SMPL_SET4 0x10 // Sample Setting bit 5.\r
+ #define SMPL_SET3 0x08 // Sample Setting bit 4.\r
+ #define SMPL_SET2 0x04 // Sample Setting bit 3.\r
+ #define SMPL_SET1 0x02 // Sample Setting bit 2.\r
+ #define SMPL_SET0 0x01 // Sample Setting bit 1.\r
+\r
+SFR(S1CON, 0xDC); // I2C Interface Control Register.\r
+ #define CR2 0x80 // SCL clock frequency select bit 3.\r
+ #define ENI1 0x40 // I2C Interface Enable.\r
+ #define STA 0x20 // START flag.\r
+ #define STO 0x10 // STOP flag.\r
+ #define ADDR 0x08 // Slave mode address.\r
+ #define AA 0x04 // Assert Acknowledge enable.\r
+ #define CR1 0x02 // SCL clock frequency select bit 2.\r
+ #define CR0 0x01 // SCL clock frequency select bit 1.\r
+\r
+SFR(S1STA, 0xDD); // I2C Interface Status Register.\r
+ #define GC 0x80 // General Call flag.\r
+ #define STOP 0x40 // STOP flag.\r
+ #define INTR 0x20 // Interrupt flag.\r
+ #define TX_MODE 0x10 // Transmission Mode flag.\r
+ #define BBUSY 0x08 // Bus Busy flag.\r
+ #define BLOST 0x04 // Bus Lost flag.\r
+ #define ACK_RESP 0x02 // Not Acknowledge Response flag.\r
+ #define SLV 0x01 // Slave Mode flag.\r
+\r
+SFR(S1DAT, 0xDE); // I2C Data Shift Register.\r
+SFR(S1ADR, 0xDF); // I2C Address Register (bit 0 not used).\r
+\r
+SFR(PSW, 0xD0); // Program Status Word.\r
+ SBIT(CY, 0xD0, 7); // Carry Flag.\r
+ SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag.\r
+ SBIT(F0, 0xD0, 5); // User-Defined Flag.\r
+ SBIT(RS1, 0xD0, 4); // Register Bank Select 1.\r
+ SBIT(RS0, 0xD0, 3); // Register Bank Select 0.\r
+ SBIT(OV, 0xD0, 2); // Overflow Flag.\r
+ SBIT(P, 0xD0, 0); // Parity Flag.\r
+\r
+SFR(A, 0xE0);\r
+SFR(ACC, 0xE0); // Accumulator\r
+ SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.\r
+ SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.\r
+ SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.\r
+ SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.\r
+ SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.\r
+ SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.\r
+ SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.\r
+ SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.\r
+\r
+SFR(B, 0xF0); // B Register\r
+ SBIT(B_0, 0xF0, 0); // Register B bit 0.\r
+ SBIT(B_1, 0xF0, 1); // Register B bit 1.\r
+ SBIT(B_2, 0xF0, 2); // Register B bit 2.\r
+ SBIT(B_3, 0xF0, 3); // Register B bit 3.\r
+ SBIT(B_4, 0xF0, 4); // Register B bit 4.\r
+ SBIT(B_5, 0xF0, 5); // Register B bit 5.\r
+ SBIT(B_6, 0xF0, 6); // Register B bit 6.\r
+ SBIT(B_7, 0xF0, 7); // Register B bit 7.\r
+\r
+#endif //REG_UPSD33XX_H\r
projects / fw / sdcc / commitdiff