__sfr __at (0xAF) CKCON1; //Clock control Register 1
#define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
__sfr __at (0xAF) CKCON1; //Clock control Register 1
#define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
-__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
-__sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
-__sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
-__sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
-__sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
-__sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
-__sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
-__sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
-__sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
-__sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
-
-__sfr __at (0xDA) CCAPM0; //Module 0 Mode.
-__sfr __at (0xDB) CCAPM1; //Module 1 Mode.
-__sfr __at (0xDC) CCAPM2; //Module 2 Mode.
-__sfr __at (0xDD) CCAPM3; //Module 3 Mode.
+__sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
+__sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
+__sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
+__sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
+__sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
+__sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
+__sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
+__sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
+__sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
+__sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
+
+__sfr __at (0xDA) CCAPM0; //Module 0 Mode.
+__sfr __at (0xDB) CCAPM1; //Module 1 Mode.
+__sfr __at (0xDC) CCAPM2; //Module 2 Mode.
+__sfr __at (0xDD) CCAPM3; //Module 3 Mode.
#define ECOM 0x40 //Enable Comparator.
#define CAPP 0x20 //1=enables positive edge capture.
#define CAPN 0x10 //1=enables negative edge capture.
#define ECOM 0x40 //Enable Comparator.
#define CAPP 0x20 //1=enables positive edge capture.
#define CAPN 0x10 //1=enables negative edge capture.
__sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
__sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
__sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
__sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
#define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
#define WDTE 0x40 //Watchdog Timer Enable.
#define CPS1 0x04 //PCA Count Pulse Select bit 1.
#define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
#define WDTE 0x40 //Watchdog Timer Enable.
#define CPS1 0x04 //PCA Count Pulse Select bit 1.
__sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit.
__sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit.
__sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit.
__sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit.
#define PPCH 0x40 //PCA Interrupt Priority High Bit.
#define PT2H 0x20 //Timer 2 Interrupt Priority High Bit.
#define PHS 0x10 //Serial Port Interrupt Priority High Bit.
#define PPCH 0x40 //PCA Interrupt Priority High Bit.
#define PT2H 0x20 //Timer 2 Interrupt Priority High Bit.
#define PHS 0x10 //Serial Port Interrupt Priority High Bit.
//1 1 0 (2^20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz
//1 1 1 (2^21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
//1 1 0 (2^20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz
//1 1 1 (2^21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
-__sfr __at (0xA9) SADDR; //Serial Port Address Register.
-__sfr __at (0xB9) SADEN; //Serial Port Address Enable.
+__sfr __at (0xA9) SADDR; //Serial Port Address Register.
+__sfr __at (0xB9) SADEN; //Serial Port Address Enable.
__sfr __at (0xC4) SPSTA; //Serial Peripheral Status register
#define SPIF 0x80 //Serial Peripheral Data Transfer Flag
#define WCOL 0x40 //Write collision Flag.
__sfr __at (0xC4) SPSTA; //Serial Peripheral Status register
#define SPIF 0x80 //Serial Peripheral Data Transfer Flag
#define WCOL 0x40 //Write collision Flag.
__sfr __at (0x9B) BDRCON; //Baud Rate Control
#define BRR 0x10 //Baud Rate Run Control bit. '1'=enable
#define TBCK 0x08 //Transmission Baud rate Generator Selection bit for UART
__sfr __at (0x9B) BDRCON; //Baud Rate Control
#define BRR 0x10 //Baud Rate Run Control bit. '1'=enable
#define TBCK 0x08 //Transmission Baud rate Generator Selection bit for UART
#define SPD 0x02 //Baud Rate Speed Control bit for UART
#define SRC 0x01 //Baud Rate Source select bit in Mode 0 for UART
#define SPD 0x02 //Baud Rate Speed Control bit for UART
#define SRC 0x01 //Baud Rate Source select bit in Mode 0 for UART