1 /*-------------------------------------------------------------------------
2 Register Declarations for the Atmel AT89C51RD2/ED2 Processor
4 Written By - Jesus Calvino-Fraga / jesusc at ece.ubc.ca (July 2005)
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Lesser General Public License for more details.
16 You should have received a copy of the GNU Lesser General Public
17 License along with this library; if not, write to the Free Software
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 In other words, you are welcome to use, share and improve this program.
21 You are forbidden to forbid anyone else to use, share and improve
22 what you give them. Help stamp out software-hoarding!
23 -------------------------------------------------------------------------*/
25 #ifndef REG_AT89C51ED2_H
26 #define REG_AT89C51ED2_H
28 #include <8052.h> // Load definitions for the 8052
34 // Define AT89C51RD2/ED2 specific registers only
36 __sfr __at (0x8E) AUXR; //Auxiliary function register
37 #define DPU 0x80 //'1'=Disables weak pull-up
38 #define M0 0x20 //'1'=Strechs MOVX control signals
39 #define XRS2 0x10 // XRAM select bit 2
40 #define XRS1 0x08 // XRAM select bit 1
41 #define XRS0 0x04 // XRAM select bit 0
42 // XRS2 XRS1 XRS2 XRAM Size
45 // 0 1 0 768 bytes (default)
48 #define EXTRAM 0x02 //'0'=uses internal XRAM.
49 #define AO 0x01 //'1'=Disables ALE generation.
51 __sfr __at (0xA2) AUXR1; //Auxiliary function register 1
52 #define ENBOOT 0x20 //'0'=Disables boot ROM
53 #define GF3 0x08 //General purpose user-defined flag.
54 #define DPS 0x01 //Data pointer select.
56 __sfr __at (0x97) CKRL; //Clock Reload Register
57 __sfr __at (0x8F) CKCON0; //Clock control Register 0
58 #define WDTX2 0x40 //Watch Dog Clock speed '1'=12 ck/cy, '0'=6 ck/cy
59 #define PCAX2 0x20 //Programmable Counter Array Clock speed '1'=12 ck/cy, '0'=6 ck/cy
60 #define SIX2 0x10 //Enhanced UART Clock (Mode 0 and 2) speed '1'=12 ck/cy, '0'=6 ck/cy
61 #define T2X2 0x08 //Timer2 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
62 #define T1X2 0x04 //Timer1 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
63 #define T0X2 0x02 //Timer0 Clock speed '1'=12 ck/cy, '0'=6 ck/cy
64 #define X2 0x01 //CPU Clock '0'=12 ck/cy, '1'=6 ck/cy
65 __sfr __at (0xAF) CKCON1; //Clock control Register 1
66 #define XPIX2 0x01 //SPI Clock speed '1'=12 ck/cy, '0'=6 ck/cy
68 __sfr __at (0xFA) CCAP0H; //Module 0 Capture HIGH.
69 __sfr __at (0xFB) CCAP1H; //Module 1 Capture HIGH.
70 __sfr __at (0xFC) CCAP2H; //Module 2 Capture HIGH.
71 __sfr __at (0xFD) CCAP3H; //Module 3 Capture HIGH.
72 __sfr __at (0xFE) CCAP4H; //Module 4 Capture HIGH.
73 __sfr __at (0xEA) CCAP0L; //Module 0 Capture LOW.
74 __sfr __at (0xEB) CCAP1L; //Module 1 Capture LOW.
75 __sfr __at (0xEC) CCAP2L; //Module 2 Capture LOW.
76 __sfr __at (0xED) CCAP3L; //Module 3 Capture LOW.
77 __sfr __at (0xEE) CCAP4L; //Module 4 Capture LOW.
79 __sfr __at (0xDA) CCAPM0; //Module 0 Mode.
80 __sfr __at (0xDB) CCAPM1; //Module 1 Mode.
81 __sfr __at (0xDC) CCAPM2; //Module 2 Mode.
82 __sfr __at (0xDD) CCAPM3; //Module 3 Mode.
83 __sfr __at (0xDE) CCAPM4; //Module 4 Mode.
84 //The preceding five registers have the following bits:
85 #define ECOM 0x40 //Enable Comparator.
86 #define CAPP 0x20 //1=enables positive edge capture.
87 #define CAPN 0x10 //1=enables negative edge capture.
88 #define MAT 0x08 //When counter matches sets CCF_n bit causing and interrupt.
89 #define TOG 0x04 //Toggle output on match.
90 #define PWM 0x02 //Pulse width modulation mode.
91 #define ECCF 0x01 //Enable CCF interrupt.
93 __sfr __at (0xD8) CCON; //PCA Counter Control
94 __sbit __at (0xDF) CF; //PCA Counter overflow flag.
95 __sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on. 0=counter off.
96 __sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag.
97 __sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag.
98 __sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag.
99 __sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
100 __sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
102 __sfr __at (0xF9) CH; //PCA Counter HIGH.
103 __sfr __at (0xE9) CL; //PCA Counter LOW.
105 __sfr __at (0xD9) CMOD; //PCA Counter Mode.
106 #define CIDL 0x80 //CIDL=0 program the PCA counter to work during idle mode.
107 #define WDTE 0x40 //Watchdog Timer Enable.
108 #define CPS1 0x04 //PCA Count Pulse Select bit 1.
109 #define CPS0 0x02 //PCA Count Pulse Select bit 0.
110 //00=Internal clock, Fosc/6
111 //01=Internal clock, Fosc/6
112 //10=Timer 0 overflow
113 //11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
114 #define ECF 0x01 //PCA Enable Counter Overflow Interrupt.
116 //Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here.
117 __sfr __at (0xA8) IEN0; //Interrupt Enable 1.
118 __sbit __at (0xAE) EC; //PCA Interrupt Enable bit.
120 __sfr __at (0xB1) IEN1; //Interrupt Enable 1
121 #define ESPI 0x04 //SPA Interrupt Enable bit.
122 #define KBD 0x01 //Keyboard Interrupt Enable bit.
124 //Attention IPL0 is the same as register IP found in <8051.h>
125 __sfr __at (0xB8) IPL0; //Interrupt Priority 0 LOW
126 __sbit __at (0xBE) PPCL;//PCA Interrupt Priority low bit.
127 __sbit __at (0xBD) PT2L;//Timer 2 Interrupt Priority Low Bit.
128 __sbit __at (0xBC) PLS; //Serial Port Interrupt Priority Low Bit.
129 __sbit __at (0xBB) PT1L;//Timer 1 Interrupt Priority Low Bit.
130 __sbit __at (0xBA) PX1L;//External Interrupt 1 Priority Low Bit.
131 __sbit __at (0xB9) PT0L;//Timer 0 Interrupt Priority Low Bit.
132 __sbit __at (0xB8) PX0L;//External Interrupt 0 Priority Low Bit.
134 __sfr __at (0xB7) IPH0; //Interrupt Priority 0 HIGH
135 #define PPCH 0x40 //PCA Interrupt Priority High Bit.
136 #define PT2H 0x20 //Timer 2 Interrupt Priority High Bit.
137 #define PHS 0x10 //Serial Port Interrupt Priority High Bit.
138 #define PT1H 0x08 //Timer 1 Interrupt Priority High Bit.
139 #define PX1H 0x04 //External Interrupt 1 Priority High Bit.
140 #define PT0H 0x02 //Timer 0 Interrupt Priority High Bit.
141 #define PX0H 0x01 //External Interrupt 0 Priority High Bit.
143 __sfr __at (0xB2) IPL1; //Interrupt Priority 1 LOW.
144 #define SPIL 0x04 //SPI Priority Low Bit
145 #define KBDL 0x01 //Keyboard Priority Low Bit
147 __sfr __at (0xB3) IPH1; //Interrupt Priority 1 HIGH.
148 #define SPIH 0x04 //SPI Priority High Bit
149 #define KBDH 0x01 //Keyboard Priority High Bit
151 __sfr __at (0xC0) P4; //8-bit port 4
152 __sbit __at (0xC0) P4_0 ;
153 __sbit __at (0xC1) P4_1 ;
154 __sbit __at (0xC2) P4_2 ;
155 __sbit __at (0xC3) P4_3 ;
156 __sbit __at (0xC4) P4_4 ;
157 __sbit __at (0xC5) P4_5 ;
158 __sbit __at (0xC6) P4_6 ;
159 __sbit __at (0xC7) P4_7 ;
161 __sfr __at (0xD8) P5; //8-bit port 5
162 __sbit __at (0xD8) P5_0 ;
163 __sbit __at (0xD9) P5_1 ;
164 __sbit __at (0xDA) P5_2 ;
165 __sbit __at (0xDB) P5_3 ;
166 __sbit __at (0xDC) P5_4 ;
167 __sbit __at (0xDD) P5_5 ;
168 __sbit __at (0xDE) P5_6 ;
169 __sbit __at (0xDF) P5_7 ;
171 __sfr __at (0xA6) WDTRST; //WatchDog Timer Reset
172 __sfr __at (0xA7) WDTPRG; //WatchDog Timer Program
173 #define WTO2 0x04 //WDT Time-out select bit 2
174 #define WTO1 0x02 //WDT Time-out select bit 1
175 #define WTO0 0x01 //WDT Time-out select bit 0
176 //This names appear also in the datasheet:
177 #define S2 0x04 //WDT Time-out select bit 2
178 #define S1 0x02 //WDT Time-out select bit 1
179 #define S0 0x01 //WDT Time-out select bit 0
180 //S2 S1 S0 Selected Time-out
181 //0 0 0 (2^14 - 1) machine cycles, 16.3 ms @ FOSCA=12 MHz
182 //0 0 1 (2^15 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
183 //0 1 0 (2^16 - 1) machine cycles, 65.5 ms @ FOSCA=12 MHz
184 //0 1 1 (2^17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
185 //1 0 0 (2^18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
186 //1 0 1 (2^19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
187 //1 1 0 (2^20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz
188 //1 1 1 (2^21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
190 __sfr __at (0xA9) SADDR; //Serial Port Address Register.
191 __sfr __at (0xB9) SADEN; //Serial Port Address Enable.
193 __sfr __at (0xC3) SPCON; //SPI Control Register
194 #define SPR2 0x80 //SPI Clork Rate select bit 2.
195 #define SPEN 0x40 //SPI enable bit. When set enables SPI.
196 #define SSDIS 0x20 //Cleared to enable SS in both Master and Slave modes.
197 #define MSTR 0x10 //1=master mode. 0=slave mode.
198 #define CPOL 0x08 //1=SCK is high when idle (active low), 0=SCK is low when idle (active high).
199 #define CPHA 0x04 //1=shift triggered on the trailing edge of SCK. 0=shift trig. on leading edge.
200 #define SPR1 0x02 //SPI Clork Rate select bit 1.
201 #define SPR0 0x01 //SPI Clork Rate select bit 0.
202 //SPR2 SPR1 SPR0 Baud Rate Divisor
210 // 1 1 1 Invalid: Don't Use
212 __sfr __at (0xC4) SPSTA; //Serial Peripheral Status register
213 #define SPIF 0x80 //Serial Peripheral Data Transfer Flag
214 #define WCOL 0x40 //Write collision Flag.
215 #define SSERR 0x20 //Synchronous Serial Slave Error Flag
216 #define MODF 0x10 //Mode Fault Flag
218 __sfr __at (0xC5) SPDAT; //SPI Data
220 __sfr __at (0xC9) T2MOD; //Timer 2 mode control
221 #define T2OE 0x02 //Timer 2 Output Enable bit.
222 #define DCEN 0x01 //Down count enable
224 __sfr __at (0x9B) BDRCON; //Baud Rate Control
225 #define BRR 0x10 //Baud Rate Run Control bit. '1'=enable
226 #define TBCK 0x08 //Transmission Baud rate Generator Selection bit for UART
227 #define RBCK 0x03 //Reception Baud Rate Generator Selection bit for UART
228 #define SPD 0x02 //Baud Rate Speed Control bit for UART
229 #define SRC 0x01 //Baud Rate Source select bit in Mode 0 for UART
231 __sfr __at (0x9A) BRL; //Baud Rate Reload
233 __sfr __at (0x9C) KBLS; //Keyboard level Selector
234 __sfr __at (0x9D) KBE; //Keyboard Input Enable
235 __sfr __at (0x9E) KBF; //Keyboard Flag Register
237 __sfr __at (0xD2) EECON; //EEPROM Data Control
238 #define EEE 0x02 //EEPROM Enable. '1'=use EEPROM, '0'=use XRAM
239 #define EEBUSY 0x01 //EEPROM Busy. '1'=EEPROM is busy programming
241 #endif /*REG_AT89C51ED2_H*/
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