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   1 /***************************************************************************
   2  *   Copyright (C) 2011 by Mathias Kuester                                 *
   3  *   Mathias Kuester <kesmtp@freenet.de>                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2011 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include "jtag/jtag.h"
  29 #include "jtag/stlink/stlink_transport.h"
  30 #include "jtag/stlink/stlink_interface.h"
  31 #include "jtag/stlink/stlink_layout.h"
  32 #include "register.h"
  33 #include "algorithm.h"
  34 #include "target.h"
  35 #include "breakpoints.h"
  36 #include "target_type.h"
  37 #include "armv7m.h"
  38 #include "cortex_m.h"
  39 #include "arm_semihosting.h"
  40
  41 #define ARMV7M_SCS_DCRSR        0xe000edf4
  42 #define ARMV7M_SCS_DCRDR        0xe000edf8
  43
  44 static inline struct stlink_interface_s *target_to_stlink(struct target *target)
  45 {
  46         return target->tap->priv;
  47 }
  48
  49 static int stm32_stlink_load_core_reg_u32(struct target *target,
  50                 enum armv7m_regtype type,
  51                 uint32_t num, uint32_t *value)
  52 {
  53         int retval;
  54         struct stlink_interface_s *stlink_if = target_to_stlink(target);
  55
  56         LOG_DEBUG("%s", __func__);
  57
  58         /* NOTE:  we "know" here that the register identifiers used
  59          * in the v7m header match the Cortex-M3 Debug Core Register
  60          * Selector values for R0..R15, xPSR, MSP, and PSP.
  61          */
  62         switch (num) {
  63         case 0 ... 18:
  64                 /* read a normal core register */
  65                 retval = stlink_if->layout->api->read_reg(stlink_if->fd, num, value);
  66
  67                 if (retval != ERROR_OK) {
  68                         LOG_ERROR("JTAG failure %i", retval);
  69                         return ERROR_JTAG_DEVICE_ERROR;
  70                 }
  71                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  72                 break;
  73
  74         case ARMV7M_FPSID:
  75         case ARMV7M_FPEXC:
  76                 *value = 0;
  77                 break;
  78
  79         case ARMV7M_FPSCR:
  80                 /* Floating-point Status and Registers */
  81                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
  82                 if (retval != ERROR_OK)
  83                         return retval;
  84                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  85                 if (retval != ERROR_OK)
  86                         return retval;
  87                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  88                 break;
  89
  90         case ARMV7M_S0 ... ARMV7M_S31:
  91                 /* Floating-point Status and Registers */
  92                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
  93                 if (retval != ERROR_OK)
  94                         return retval;
  95                 retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
  96                 if (retval != ERROR_OK)
  97                         return retval;
  98                 LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
  99                 break;
 100
 101         case ARMV7M_D0 ... ARMV7M_D15:
 102                 value = 0;
 103                 break;
 104
 105         case ARMV7M_PRIMASK:
 106         case ARMV7M_BASEPRI:
 107         case ARMV7M_FAULTMASK:
 108         case ARMV7M_CONTROL:
 109                 /* Cortex-M3 packages these four registers as bitfields
 110                  * in one Debug Core register.  So say r0 and r2 docs;
 111                  * it was removed from r1 docs, but still works.
 112                  */
 113                 retval = stlink_if->layout->api->read_reg(stlink_if->fd, 20, value);
 114
 115                 switch (num) {
 116                 case ARMV7M_PRIMASK:
 117                         *value = buf_get_u32((uint8_t *) value, 0, 1);
 118                         break;
 119
 120                 case ARMV7M_BASEPRI:
 121                         *value = buf_get_u32((uint8_t *) value, 8, 8);
 122                         break;
 123
 124                 case ARMV7M_FAULTMASK:
 125                         *value = buf_get_u32((uint8_t *) value, 16, 1);
 126                         break;
 127
 128                 case ARMV7M_CONTROL:
 129                         *value = buf_get_u32((uint8_t *) value, 24, 2);
 130                         break;
 131                 }
 132
 133                 LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "",
 134                           (int)num, *value);
 135                 break;
 136
 137         default:
 138                 return ERROR_COMMAND_SYNTAX_ERROR;
 139         }
 140
 141         return ERROR_OK;
 142 }
 143
 144 static int stm32_stlink_store_core_reg_u32(struct target *target,
 145                 enum armv7m_regtype type,
 146                 uint32_t num, uint32_t value)
 147 {
 148         int retval;
 149         uint32_t reg;
 150         struct armv7m_common *armv7m = target_to_armv7m(target);
 151         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 152
 153         LOG_DEBUG("%s", __func__);
 154
 155 #ifdef ARMV7_GDB_HACKS
 156         /* If the LR register is being modified, make sure it will put us
 157          * in "thumb" mode, or an INVSTATE exception will occur. This is a
 158          * hack to deal with the fact that gdb will sometimes "forge"
 159          * return addresses, and doesn't set the LSB correctly (i.e., when
 160          * printing expressions containing function calls, it sets LR = 0.)
 161          * Valid exception return codes have bit 0 set too.
 162          */
 163         if (num == ARMV7M_R14)
 164                 value |= 0x01;
 165 #endif
 166
 167         /* NOTE:  we "know" here that the register identifiers used
 168          * in the v7m header match the Cortex-M3 Debug Core Register
 169          * Selector values for R0..R15, xPSR, MSP, and PSP.
 170          */
 171         switch (num) {
 172         case 0 ... 18:
 173                 retval = stlink_if->layout->api->write_reg(stlink_if->fd, num, value);
 174
 175                 if (retval != ERROR_OK) {
 176                         struct reg *r;
 177
 178                         LOG_ERROR("JTAG failure");
 179                         r = armv7m->core_cache->reg_list + num;
 180                         r->dirty = r->valid;
 181                         return ERROR_JTAG_DEVICE_ERROR;
 182                 }
 183                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 184                 break;
 185
 186         case ARMV7M_FPSID:
 187         case ARMV7M_FPEXC:
 188                 break;
 189
 190         case ARMV7M_FPSCR:
 191                 /* Floating-point Status and Registers */
 192                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 193                 if (retval != ERROR_OK)
 194                         return retval;
 195                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
 196                 if (retval != ERROR_OK)
 197                         return retval;
 198                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 199                 break;
 200
 201         case ARMV7M_S0 ... ARMV7M_S31:
 202                 /* Floating-point Status and Registers */
 203                 retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
 204                 if (retval != ERROR_OK)
 205                         return retval;
 206                 retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
 207                 if (retval != ERROR_OK)
 208                         return retval;
 209                 LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 210                 break;
 211
 212         case ARMV7M_D0 ... ARMV7M_D15:
 213                 break;
 214
 215         case ARMV7M_PRIMASK:
 216         case ARMV7M_BASEPRI:
 217         case ARMV7M_FAULTMASK:
 218         case ARMV7M_CONTROL:
 219                 /* Cortex-M3 packages these four registers as bitfields
 220                  * in one Debug Core register.  So say r0 and r2 docs;
 221                  * it was removed from r1 docs, but still works.
 222                  */
 223
 224                 stlink_if->layout->api->read_reg(stlink_if->fd, 20, &reg);
 225
 226                 switch (num) {
 227                 case ARMV7M_PRIMASK:
 228                         buf_set_u32((uint8_t *) &reg, 0, 1, value);
 229                         break;
 230
 231                 case ARMV7M_BASEPRI:
 232                         buf_set_u32((uint8_t *) &reg, 8, 8, value);
 233                         break;
 234
 235                 case ARMV7M_FAULTMASK:
 236                         buf_set_u32((uint8_t *) &reg, 16, 1, value);
 237                         break;
 238
 239                 case ARMV7M_CONTROL:
 240                         buf_set_u32((uint8_t *) &reg, 24, 2, value);
 241                         break;
 242                 }
 243
 244                 stlink_if->layout->api->write_reg(stlink_if->fd, 20, reg);
 245
 246                 LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
 247                 break;
 248
 249         default:
 250                 return ERROR_COMMAND_SYNTAX_ERROR;
 251         }
 252
 253         return ERROR_OK;
 254 }
 255
 256 static int stm32_stlink_examine_debug_reason(struct target *target)
 257 {
 258         if ((target->debug_reason != DBG_REASON_DBGRQ)
 259                         && (target->debug_reason != DBG_REASON_SINGLESTEP)) {
 260                 target->debug_reason = DBG_REASON_BREAKPOINT;
 261         }
 262
 263         return ERROR_OK;
 264 }
 265
 266 static int stm32_stlink_init_arch_info(struct target *target,
 267                                        struct cortex_m3_common *cortex_m3,
 268                                        struct jtag_tap *tap)
 269 {
 270         struct armv7m_common *armv7m;
 271
 272         LOG_DEBUG("%s", __func__);
 273
 274         armv7m = &cortex_m3->armv7m;
 275         armv7m_init_arch_info(target, armv7m);
 276
 277         armv7m->load_core_reg_u32 = stm32_stlink_load_core_reg_u32;
 278         armv7m->store_core_reg_u32 = stm32_stlink_store_core_reg_u32;
 279
 280         armv7m->examine_debug_reason = stm32_stlink_examine_debug_reason;
 281
 282         return ERROR_OK;
 283 }
 284
 285 static int stm32_stlink_init_target(struct command_context *cmd_ctx,
 286                                     struct target *target)
 287 {
 288         LOG_DEBUG("%s", __func__);
 289
 290         armv7m_build_reg_cache(target);
 291
 292         return ERROR_OK;
 293 }
 294
 295 static int stm32_stlink_target_create(struct target *target,
 296                 Jim_Interp *interp)
 297 {
 298         LOG_DEBUG("%s", __func__);
 299
 300         struct cortex_m3_common *cortex_m3 = calloc(1, sizeof(struct cortex_m3_common));
 301
 302         if (!cortex_m3)
 303                 return ERROR_COMMAND_SYNTAX_ERROR;
 304
 305         stm32_stlink_init_arch_info(target, cortex_m3, target->tap);
 306
 307         return ERROR_OK;
 308 }
 309
 310 static int stm32_stlink_load_context(struct target *target)
 311 {
 312         struct armv7m_common *armv7m = target_to_armv7m(target);
 313         int num_regs = armv7m->core_cache->num_regs;
 314
 315         for (int i = 0; i < num_regs; i++) {
 316                 if (!armv7m->core_cache->reg_list[i].valid)
 317                         armv7m->read_core_reg(target, i);
 318         }
 319
 320         return ERROR_OK;
 321 }
 322
 323 static int stlink_debug_entry(struct target *target)
 324 {
 325         struct armv7m_common *armv7m = target_to_armv7m(target);
 326         struct arm *arm = &armv7m->arm;
 327         struct reg *r;
 328         uint32_t xPSR;
 329         int retval;
 330
 331         retval = armv7m->examine_debug_reason(target);
 332         if (retval != ERROR_OK)
 333                 return retval;
 334
 335         stm32_stlink_load_context(target);
 336
 337         r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
 338         xPSR = buf_get_u32(r->value, 0, 32);
 339
 340         /* Are we in an exception handler */
 341         if (xPSR & 0x1FF) {
 342                 armv7m->core_mode = ARMV7M_MODE_HANDLER;
 343                 armv7m->exception_number = (xPSR & 0x1FF);
 344
 345                 arm->core_mode = ARM_MODE_HANDLER;
 346                 arm->map = armv7m_msp_reg_map;
 347         } else {
 348                 unsigned control = buf_get_u32(armv7m->core_cache
 349                                 ->reg_list[ARMV7M_CONTROL].value, 0, 2);
 350
 351                 /* is this thread privileged? */
 352                 armv7m->core_mode = control & 1;
 353                 arm->core_mode = armv7m->core_mode
 354                                 ? ARM_MODE_USER_THREAD
 355                                 : ARM_MODE_THREAD;
 356
 357                 /* which stack is it using? */
 358                 if (control & 2)
 359                         arm->map = armv7m_psp_reg_map;
 360                 else
 361                         arm->map = armv7m_msp_reg_map;
 362
 363                 armv7m->exception_number = 0;
 364         }
 365
 366         LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 367                 armv7m_mode_strings[armv7m->core_mode],
 368                 *(uint32_t *)(arm->pc->value),
 369                 target_state_name(target));
 370
 371         return retval;
 372 }
 373
 374 static int stm32_stlink_poll(struct target *target)
 375 {
 376         enum target_state state;
 377         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 378         struct armv7m_common *armv7m = target_to_armv7m(target);
 379
 380         state = stlink_if->layout->api->state(stlink_if->fd);
 381
 382         if (state == TARGET_UNKNOWN) {
 383                 LOG_ERROR("jtag status contains invalid mode value - communication failure");
 384                 return ERROR_TARGET_FAILURE;
 385         }
 386
 387         if (target->state == state)
 388                 return ERROR_OK;
 389
 390         if (state == TARGET_HALTED) {
 391                 target->state = state;
 392
 393                 int retval = stlink_debug_entry(target);
 394                 if (retval != ERROR_OK)
 395                         return retval;
 396
 397                 if (arm_semihosting(target, &retval) != 0)
 398                         return retval;
 399
 400                 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 401                 LOG_DEBUG("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 402         }
 403
 404         return ERROR_OK;
 405 }
 406
 407 static int stm32_stlink_assert_reset(struct target *target)
 408 {
 409         int res;
 410         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 411         struct armv7m_common *armv7m = target_to_armv7m(target);
 412
 413         LOG_DEBUG("%s", __func__);
 414
 415         res = stlink_if->layout->api->reset(stlink_if->fd);
 416
 417         if (res != ERROR_OK)
 418                 return res;
 419
 420         /* virtual assert reset, we need it for the internal
 421          * jtag state machine
 422          */
 423         jtag_add_reset(1, 1);
 424
 425         /* registers are now invalid */
 426         register_cache_invalidate(armv7m->core_cache);
 427
 428         if (target->reset_halt) {
 429                 target->state = TARGET_RESET;
 430                 target->debug_reason = DBG_REASON_DBGRQ;
 431         } else {
 432                 target->state = TARGET_HALTED;
 433         }
 434
 435         return ERROR_OK;
 436 }
 437
 438 static int stm32_stlink_deassert_reset(struct target *target)
 439 {
 440         int res;
 441
 442         LOG_DEBUG("%s", __func__);
 443
 444         /* virtual deassert reset, we need it for the internal
 445          * jtag state machine
 446          */
 447         jtag_add_reset(0, 0);
 448
 449         if (!target->reset_halt) {
 450                 res = target_resume(target, 1, 0, 0, 0);
 451
 452                 if (res != ERROR_OK)
 453                         return res;
 454         }
 455
 456         return ERROR_OK;
 457 }
 458
 459 static int stm32_stlink_soft_reset_halt(struct target *target)
 460 {
 461         LOG_DEBUG("%s", __func__);
 462         return ERROR_OK;
 463 }
 464
 465 static int stm32_stlink_halt(struct target *target)
 466 {
 467         int res;
 468         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 469
 470         LOG_DEBUG("%s", __func__);
 471
 472         if (target->state == TARGET_HALTED) {
 473                 LOG_DEBUG("target was already halted");
 474                 return ERROR_OK;
 475         }
 476
 477         if (target->state == TARGET_UNKNOWN)
 478                 LOG_WARNING("target was in unknown state when halt was requested");
 479
 480         res = stlink_if->layout->api->halt(stlink_if->fd);
 481
 482         if (res != ERROR_OK)
 483                 return res;
 484
 485         target->debug_reason = DBG_REASON_DBGRQ;
 486
 487         return ERROR_OK;
 488 }
 489
 490 static int stm32_stlink_resume(struct target *target, int current,
 491                 uint32_t address, int handle_breakpoints,
 492                 int debug_execution)
 493 {
 494         int res;
 495         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 496         struct armv7m_common *armv7m = target_to_armv7m(target);
 497         uint32_t resume_pc;
 498         struct breakpoint *breakpoint = NULL;
 499         struct reg *pc;
 500
 501         LOG_DEBUG("%s %d %x %d %d", __func__, current, address,
 502                         handle_breakpoints, debug_execution);
 503
 504         if (target->state != TARGET_HALTED) {
 505                 LOG_WARNING("target not halted");
 506                 return ERROR_TARGET_NOT_HALTED;
 507         }
 508
 509         pc = armv7m->arm.pc;
 510         if (!current) {
 511                 buf_set_u32(pc->value, 0, 32, address);
 512                 pc->dirty = true;
 513                 pc->valid = true;
 514         }
 515
 516         if (!breakpoint_find(target, buf_get_u32(pc->value, 0, 32))
 517                         && !debug_execution) {
 518                 armv7m_maybe_skip_bkpt_inst(target, NULL);
 519         }
 520
 521         resume_pc = buf_get_u32(pc->value, 0, 32);
 522
 523         armv7m_restore_context(target);
 524
 525         /* registers are now invalid */
 526         register_cache_invalidate(armv7m->core_cache);
 527
 528         /* the front-end may request us not to handle breakpoints */
 529         if (handle_breakpoints) {
 530                 /* Single step past breakpoint at current address */
 531                 breakpoint = breakpoint_find(target, resume_pc);
 532                 if (breakpoint) {
 533                         LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 534                                         breakpoint->address,
 535                                         breakpoint->unique_id);
 536                         cortex_m3_unset_breakpoint(target, breakpoint);
 537
 538                         res = stlink_if->layout->api->step(stlink_if->fd);
 539
 540                         if (res != ERROR_OK)
 541                                 return res;
 542
 543                         cortex_m3_set_breakpoint(target, breakpoint);
 544                 }
 545         }
 546
 547         res = stlink_if->layout->api->run(stlink_if->fd);
 548
 549         if (res != ERROR_OK)
 550                 return res;
 551
 552         target->state = TARGET_RUNNING;
 553
 554         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 555
 556         return ERROR_OK;
 557 }
 558
 559 static int stm32_stlink_step(struct target *target, int current,
 560                 uint32_t address, int handle_breakpoints)
 561 {
 562         int res;
 563         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 564         struct armv7m_common *armv7m = target_to_armv7m(target);
 565         struct breakpoint *breakpoint = NULL;
 566         struct reg *pc = armv7m->arm.pc;
 567         bool bkpt_inst_found = false;
 568
 569         LOG_DEBUG("%s", __func__);
 570
 571         if (target->state != TARGET_HALTED) {
 572                 LOG_WARNING("target not halted");
 573                 return ERROR_TARGET_NOT_HALTED;
 574         }
 575
 576         if (!current) {
 577                 buf_set_u32(pc->value, 0, 32, address);
 578                 pc->dirty = true;
 579                 pc->valid = true;
 580         }
 581
 582         uint32_t pc_value = buf_get_u32(pc->value, 0, 32);
 583
 584         /* the front-end may request us not to handle breakpoints */
 585         if (handle_breakpoints) {
 586                 breakpoint = breakpoint_find(target, pc_value);
 587                 if (breakpoint)
 588                         cortex_m3_unset_breakpoint(target, breakpoint);
 589         }
 590
 591         armv7m_maybe_skip_bkpt_inst(target, &bkpt_inst_found);
 592
 593         target->debug_reason = DBG_REASON_SINGLESTEP;
 594
 595         armv7m_restore_context(target);
 596
 597         target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
 598
 599         res = stlink_if->layout->api->step(stlink_if->fd);
 600
 601         if (res != ERROR_OK)
 602                 return res;
 603
 604         /* registers are now invalid */
 605         register_cache_invalidate(armv7m->core_cache);
 606
 607         if (breakpoint)
 608                 cortex_m3_set_breakpoint(target, breakpoint);
 609
 610         stlink_debug_entry(target);
 611         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 612
 613         LOG_INFO("halted: PC: 0x%x", buf_get_u32(armv7m->arm.pc->value, 0, 32));
 614
 615         return ERROR_OK;
 616 }
 617
 618 static int stm32_stlink_read_memory(struct target *target, uint32_t address,
 619                 uint32_t size, uint32_t count,
 620                 uint8_t *buffer)
 621 {
 622         int res;
 623         uint32_t buffer_threshold = 128;
 624         uint32_t addr_increment = 4;
 625         uint32_t c;
 626         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 627
 628         if (!count || !buffer)
 629                 return ERROR_COMMAND_SYNTAX_ERROR;
 630
 631         LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
 632
 633         /* prepare byte count, buffer threshold
 634          * and address increment for none 32bit access
 635          */
 636         if (size != 4) {
 637                 count *= size;
 638                 buffer_threshold = 64;
 639                 addr_increment = 1;
 640         }
 641
 642         while (count) {
 643                 if (count > buffer_threshold)
 644                         c = buffer_threshold;
 645                 else
 646                         c = count;
 647
 648                 if (size != 4)
 649                         res = stlink_if->layout->api->read_mem8(stlink_if->fd,
 650                                         address, c, buffer);
 651                 else
 652                         res = stlink_if->layout->api->read_mem32(stlink_if->fd,
 653                                         address, c, buffer);
 654
 655                 if (res != ERROR_OK)
 656                         return res;
 657
 658                 address += (c * addr_increment);
 659                 buffer += (c * addr_increment);
 660                 count -= c;
 661         }
 662
 663         return ERROR_OK;
 664 }
 665
 666 static int stm32_stlink_write_memory(struct target *target, uint32_t address,
 667                 uint32_t size, uint32_t count,
 668                 const uint8_t *buffer)
 669 {
 670         int res;
 671         uint32_t buffer_threshold = 128;
 672         uint32_t addr_increment = 4;
 673         uint32_t c;
 674         struct stlink_interface_s *stlink_if = target_to_stlink(target);
 675
 676         if (!count || !buffer)
 677                 return ERROR_COMMAND_SYNTAX_ERROR;
 678
 679         LOG_DEBUG("%s %x %d %d", __func__, address, size, count);
 680
 681         /* prepare byte count, buffer threshold
 682          * and address increment for none 32bit access
 683          */
 684         if (size != 4) {
 685                 count *= size;
 686                 buffer_threshold = 64;
 687                 addr_increment = 1;
 688         }
 689
 690         while (count) {
 691                 if (count > buffer_threshold)
 692                         c = buffer_threshold;
 693                 else
 694                         c = count;
 695
 696                 if (size != 4)
 697                         res = stlink_if->layout->api->write_mem8(stlink_if->fd,
 698                                         address, c, buffer);
 699                 else
 700                         res = stlink_if->layout->api->write_mem32(stlink_if->fd,
 701                                         address, c, buffer);
 702
 703                 if (res != ERROR_OK)
 704                         return res;
 705
 706                 address += (c * addr_increment);
 707                 buffer += (c * addr_increment);
 708                 count -= c;
 709         }
 710
 711         return ERROR_OK;
 712 }
 713
 714 static int stm32_stlink_bulk_write_memory(struct target *target,
 715                 uint32_t address, uint32_t count,
 716                 const uint8_t *buffer)
 717 {
 718         return stm32_stlink_write_memory(target, address, 4, count, buffer);
 719 }
 720
 721 struct target_type stm32_stlink_target = {
 722         .name = "stm32_stlink",
 723
 724         .init_target = stm32_stlink_init_target,
 725         .target_create = stm32_stlink_target_create,
 726         .examine = cortex_m3_examine,
 727
 728         .poll = stm32_stlink_poll,
 729         .arch_state = armv7m_arch_state,
 730
 731         .assert_reset = stm32_stlink_assert_reset,
 732         .deassert_reset = stm32_stlink_deassert_reset,
 733         .soft_reset_halt = stm32_stlink_soft_reset_halt,
 734
 735         .halt = stm32_stlink_halt,
 736         .resume = stm32_stlink_resume,
 737         .step = stm32_stlink_step,
 738
 739         .get_gdb_reg_list = armv7m_get_gdb_reg_list,
 740
 741         .read_memory = stm32_stlink_read_memory,
 742         .write_memory = stm32_stlink_write_memory,
 743         .bulk_write_memory = stm32_stlink_bulk_write_memory,
 744         .checksum_memory = armv7m_checksum_memory,
 745         .blank_check_memory = armv7m_blank_check_memory,
 746
 747         .run_algorithm = armv7m_run_algorithm,
 748         .start_algorithm = armv7m_start_algorithm,
 749         .wait_algorithm = armv7m_wait_algorithm,
 750
 751         .add_breakpoint = cortex_m3_add_breakpoint,
 752         .remove_breakpoint = cortex_m3_remove_breakpoint,
 753         .add_watchpoint = cortex_m3_add_watchpoint,
 754         .remove_watchpoint = cortex_m3_remove_watchpoint,
 755 };