stm32: Update register read/write to the register definition.

This patch fix the register index on read/write register.

Change-Id: I7b52a927a48259d6f497ac0f474aff7ff1529e9a
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/525
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c
index 7bec73f5827a3ceafcf4d6de109c9a6bd35666a1..7336b14780aa87fbcbcfcf77dabf7dba75b7c704 100644 (file)
--- a/src/target/stm32_stlink.c
+++ b/src/target/stm32_stlink.c
@@ -71,10 +71,14 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
                LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
                break;
 
-       case 33:
-       case 64 ... 96:
+       case ARMV7M_FPSID:
+       case ARMV7M_FPEXC:
+               *value = 0;
+               break;
+
+       case ARMV7M_FPSCR:
                /* Floating-point Status and Registers */
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num);
+               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
                if (retval != ERROR_OK)
                        return retval;
                retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
@@ -83,6 +87,21 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
                LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
                break;
 
+       case ARMV7M_S0 ... ARMV7M_S31:
+               /* Floating-point Status and Registers */
+               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num-ARMV7M_S0+64);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+               if (retval != ERROR_OK)
+                       return retval;
+               LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+               break;
+
+       case ARMV7M_D0 ... ARMV7M_D15:
+               value = 0;
+               break;
+
        case ARMV7M_PRIMASK:
        case ARMV7M_BASEPRI:
        case ARMV7M_FAULTMASK:
@@ -164,18 +183,35 @@ static int stm32_stlink_store_core_reg_u32(struct target *target,
                LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
                break;
 
-       case 33:
-       case 64 ... 96:
+       case ARMV7M_FPSID:
+       case ARMV7M_FPEXC:
+               break;
+
+       case ARMV7M_FPSCR:
                /* Floating-point Status and Registers */
                retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
                if (retval != ERROR_OK)
                        return retval;
-               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num | (1<<16));
+               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
                if (retval != ERROR_OK)
                        return retval;
                LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
                break;
 
+       case ARMV7M_S0 ... ARMV7M_S31:
+               /* Floating-point Status and Registers */
+               retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+               if (retval != ERROR_OK)
+                       return retval;
+               retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
+               if (retval != ERROR_OK)
+                       return retval;
+               LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+               break;
+
+       case ARMV7M_D0 ... ARMV7M_D15:
+               break;
+
        case ARMV7M_PRIMASK:
        case ARMV7M_BASEPRI:
        case ARMV7M_FAULTMASK: