1 /***************************************************************************
2 * ESP32-S3 target for OpenOCD *
3 * Copyright (C) 2020 Espressif Systems Ltd. *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
19 #ifndef OPENOCD_TARGET_ESP32S3_H
20 #define OPENOCD_TARGET_ESP32S3_H
22 #include <target/xtensa/xtensa_regs.h>
24 #define ESP32_S3_DROM_LOW 0x3C000000
25 #define ESP32_S3_DROM_HIGH 0x3D000000
26 #define ESP32_S3_IROM_LOW 0x42000000
27 #define ESP32_S3_IROM_HIGH 0x44000000
29 /*Number of registers returned directly by the G command
30 *Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
31 #define ESP32_S3_NUM_REGS_G_COMMAND 128
34 /* chip specific registers that extend ISA go after ISA-defined ones */
35 ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
36 ESP32_S3_REG_IDX_ACCX_0,
37 ESP32_S3_REG_IDX_ACCX_1,
38 ESP32_S3_REG_IDX_QACC_H_0,
39 ESP32_S3_REG_IDX_QACC_H_1,
40 ESP32_S3_REG_IDX_QACC_H_2,
41 ESP32_S3_REG_IDX_QACC_H_3,
42 ESP32_S3_REG_IDX_QACC_H_4,
43 ESP32_S3_REG_IDX_QACC_L_0,
44 ESP32_S3_REG_IDX_QACC_L_1,
45 ESP32_S3_REG_IDX_QACC_L_2,
46 ESP32_S3_REG_IDX_QACC_L_3,
47 ESP32_S3_REG_IDX_QACC_L_4,
48 ESP32_S3_REG_IDX_SAR_BYTE,
49 ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
50 ESP32_S3_REG_IDX_UA_STATE_0,
51 ESP32_S3_REG_IDX_UA_STATE_1,
52 ESP32_S3_REG_IDX_UA_STATE_2,
53 ESP32_S3_REG_IDX_UA_STATE_3,
65 #endif /* OPENOCD_TARGET_ESP32S3_H */