2 // Using typedef'ed structures instead of #define's would be much cleaner. However,
3 // it's a damn lot of work to define them all, and there were a bunch of #defines
4 // to start with, so I just expanded them.
12 /*##############################################################################
14 ##############################################################################*/
16 /* Constants for data to put in IRQ/FIQ Exception Vectors */
17 #define VECTDATA_IRQ 0xe51ffff0 /* LDR PC,[PC,#-0xFF0] */
18 #define VECTDATA_FIQ /* __TODO */
21 /*##############################################################################
22 ## VECTORED INTERRUPT CONTROLLER
23 ##############################################################################*/
25 #define VIC_IRQStatus (*(pREG32 (0xfffff000)))
26 #define VIC_FIQStatus (*(pREG32 (0xfffff004)))
27 #define VIC_RawIntr (*(pREG32 (0xfffff008)))
28 #define VIC_IntSelect (*(pREG32 (0xfffff00c)))
29 #define VIC_IntEnable (*(pREG32 (0xfffff010)))
30 #define VIC_IntEnClr (*(pREG32 (0xfffff014)))
31 #define VIC_SoftInt (*(pREG32 (0xfffff018)))
32 #define VIC_SoftIntClear (*(pREG32 (0xfffff01c)))
33 #define VIC_Protection (*(pREG32 (0xfffff020)))
34 #define VIC_VectAddr (*(pREG32 (0xfffff030)))
35 #define VIC_DefVectAddr (*(pREG32 (0xfffff034)))
37 #define VIC_VectAddr0 (*(pREG32 (0xfffff100)))
38 #define VIC_VectAddr1 (*(pREG32 (0xfffff104)))
39 #define VIC_VectAddr2 (*(pREG32 (0xfffff108)))
40 #define VIC_VectAddr3 (*(pREG32 (0xfffff10c)))
41 #define VIC_VectAddr4 (*(pREG32 (0xfffff110)))
42 #define VIC_VectAddr5 (*(pREG32 (0xfffff114)))
43 #define VIC_VectAddr6 (*(pREG32 (0xfffff118)))
44 #define VIC_VectAddr7 (*(pREG32 (0xfffff11c)))
45 #define VIC_VectAddr8 (*(pREG32 (0xfffff120)))
46 #define VIC_VectAddr9 (*(pREG32 (0xfffff124)))
47 #define VIC_VectAddr10 (*(pREG32 (0xfffff128)))
48 #define VIC_VectAddr11 (*(pREG32 (0xfffff12c)))
49 #define VIC_VectAddr12 (*(pREG32 (0xfffff130)))
50 #define VIC_VectAddr13 (*(pREG32 (0xfffff134)))
51 #define VIC_VectAddr14 (*(pREG32 (0xfffff138)))
52 #define VIC_VectAddr15 (*(pREG32 (0xfffff13c)))
54 #define VIC_VectCntl0 (*(pREG32 (0xfffff200)))
55 #define VIC_VectCntl1 (*(pREG32 (0xfffff204)))
56 #define VIC_VectCntl2 (*(pREG32 (0xfffff208)))
57 #define VIC_VectCntl3 (*(pREG32 (0xfffff20c)))
58 #define VIC_VectCntl4 (*(pREG32 (0xfffff210)))
59 #define VIC_VectCntl5 (*(pREG32 (0xfffff214)))
60 #define VIC_VectCntl6 (*(pREG32 (0xfffff218)))
61 #define VIC_VectCntl7 (*(pREG32 (0xfffff21c)))
62 #define VIC_VectCntl8 (*(pREG32 (0xfffff220)))
63 #define VIC_VectCntl9 (*(pREG32 (0xfffff224)))
64 #define VIC_VectCntl10 (*(pREG32 (0xfffff228)))
65 #define VIC_VectCntl11 (*(pREG32 (0xfffff22c)))
66 #define VIC_VectCntl12 (*(pREG32 (0xfffff230)))
67 #define VIC_VectCntl13 (*(pREG32 (0xfffff234)))
68 #define VIC_VectCntl14 (*(pREG32 (0xfffff238)))
69 #define VIC_VectCntl15 (*(pREG32 (0xfffff23c)))
71 #define VIC_ITCR (*(pREG32 (0xfffff300)))
72 #define VIC_ITIP1 (*(pREG32 (0xfffff304)))
73 #define VIC_ITIP2 (*(pREG32 (0xfffff308)))
74 #define VIC_ITOP1 (*(pREG32 (0xfffff30c)))
75 #define VIC_ITOP2 (*(pREG32 (0xfffff310)))
76 #define VIC_PeriphID0 (*(pREG32 (0xffffffe0)))
77 #define VIC_PeriphID1 (*(pREG32 (0xffffffe4)))
78 #define VIC_PeriphID2 (*(pREG32 (0xffffffe8)))
79 #define VIC_PeriphID3 (*(pREG32 (0xffffffec)))
81 #define VIC_SoftInt_WDT (0x00000001)
82 #define VIC_SoftInt_ARMCore0 (0x00000004)
83 #define VIC_SoftInt_ARMCore1 (0x00000008)
84 #define VIC_SoftInt_Timer0 (0x00000010)
85 #define VIC_SoftInt_Timer1 (0x00000020)
86 #define VIC_SoftInt_UART0 (0x00000040)
87 #define VIC_SoftInt_UART1 (0x00000080)
88 #define VIC_SoftInt_PWM0 (0x00000100)
89 #define VIC_SoftInt_I2C0 (0x00000200)
90 #define VIC_SoftInt_SPI0 (0x00000400)
91 #define VIC_SoftInt_SPI1 (0x00000800)
92 #define VIC_SoftInt_SSP (0x00000800)
93 #define VIC_SoftInt_PLL (0x00001000)
94 #define VIC_SoftInt_RTC (0x00002000)
95 #define VIC_SoftInt_EINT0 (0x00004000)
96 #define VIC_SoftInt_EINT1 (0x00008000)
97 #define VIC_SoftInt_EINT2 (0x00010000)
98 #define VIC_SoftInt_EINT3 (0x00020000)
99 #define VIC_SoftInt_AD0 (0x00040000)
100 #define VIC_SoftInt_I2C1 (0x00080000)
101 #define VIC_SoftInt_BOD (0x00100000)
102 #define VIC_SoftInt_AD1 (0x00200000)
103 #define VIC_SoftInt_USB (0x00400000)
104 #define VIC_SoftInt_MASK (0x007ffffd)
106 #define VIC_SoftIntClr_WDT (0x00000001)
107 #define VIC_SoftIntClr_ARMCore0 (0x00000004)
108 #define VIC_SoftIntClr_ARMCore1 (0x00000008)
109 #define VIC_SoftIntClr_Timer0 (0x00000010)
110 #define VIC_SoftIntClr_Timer1 (0x00000020)
111 #define VIC_SoftIntClr_UART0 (0x00000040)
112 #define VIC_SoftIntClr_UART1 (0x00000080)
113 #define VIC_SoftIntClr_PWM0 (0x00000100)
114 #define VIC_SoftIntClr_I2C0 (0x00000200)
115 #define VIC_SoftIntClr_SPI0 (0x00000400)
116 #define VIC_SoftIntClr_SPI1 (0x00000800)
117 #define VIC_SoftIntClr_SSP (0x00000800)
118 #define VIC_SoftIntClr_PLL (0x00001000)
119 #define VIC_SoftIntClr_RTC (0x00002000)
120 #define VIC_SoftIntClr_EINT0 (0x00004000)
121 #define VIC_SoftIntClr_EINT1 (0x00008000)
122 #define VIC_SoftIntClr_EINT2 (0x00010000)
123 #define VIC_SoftIntClr_EINT3 (0x00020000)
124 #define VIC_SoftIntClr_AD0 (0x00040000)
125 #define VIC_SoftIntClr_I2C1 (0x00080000)
126 #define VIC_SoftIntClr_BOD (0x00100000)
127 #define VIC_SoftIntClr_AD1 (0x00200000)
128 #define VIC_SoftIntClr_USB (0x00400000)
129 #define VIC_SoftIntClr_MASK (0x007ffffd)
131 #define VIC_RawIntr_WDT (0x00000001)
132 #define VIC_RawIntr_ARMCore0 (0x00000004)
133 #define VIC_RawIntr_ARMCore1 (0x00000008)
134 #define VIC_RawIntr_Timer0 (0x00000010)
135 #define VIC_RawIntr_Timer1 (0x00000020)
136 #define VIC_RawIntr_UART0 (0x00000040)
137 #define VIC_RawIntr_UART1 (0x00000080)
138 #define VIC_RawIntr_PWM0 (0x00000100)
139 #define VIC_RawIntr_I2C0 (0x00000200)
140 #define VIC_RawIntr_SPI0 (0x00000400)
141 #define VIC_RawIntr_SPI1 (0x00000800)
142 #define VIC_RawIntr_SSP (0x00000800)
143 #define VIC_RawIntr_PLL (0x00001000)
144 #define VIC_RawIntr_RTC (0x00002000)
145 #define VIC_RawIntr_EINT0 (0x00004000)
146 #define VIC_RawIntr_EINT1 (0x00008000)
147 #define VIC_RawIntr_EINT2 (0x00010000)
148 #define VIC_RawIntr_EINT3 (0x00020000)
149 #define VIC_RawIntr_AD0 (0x00040000)
150 #define VIC_RawIntr_I2C1 (0x00080000)
151 #define VIC_RawIntr_BOD (0x00100000)
152 #define VIC_RawIntr_AD1 (0x00200000)
153 #define VIC_RawIntr_USB (0x00400000)
154 #define VIC_RawIntr_MASK (0x007ffffd)
156 #define VIC_IntEnable_WDT (0x00000001)
157 #define VIC_IntEnable_ARMCore0 (0x00000004)
158 #define VIC_IntEnable_ARMCore1 (0x00000008)
159 #define VIC_IntEnable_Timer0 (0x00000010)
160 #define VIC_IntEnable_Timer1 (0x00000020)
161 #define VIC_IntEnable_UART0 (0x00000040)
162 #define VIC_IntEnable_UART1 (0x00000080)
163 #define VIC_IntEnable_PWM0 (0x00000100)
164 #define VIC_IntEnable_I2C0 (0x00000200)
165 #define VIC_IntEnable_SPI0 (0x00000400)
166 #define VIC_IntEnable_SPI1 (0x00000800)
167 #define VIC_IntEnable_SSP (0x00000800)
168 #define VIC_IntEnable_PLL (0x00001000)
169 #define VIC_IntEnable_RTC (0x00002000)
170 #define VIC_IntEnable_EINT0 (0x00004000)
171 #define VIC_IntEnable_EINT1 (0x00008000)
172 #define VIC_IntEnable_EINT2 (0x00010000)
173 #define VIC_IntEnable_EINT3 (0x00020000)
174 #define VIC_IntEnable_AD0 (0x00040000)
175 #define VIC_IntEnable_I2C1 (0x00080000)
176 #define VIC_IntEnable_BOD (0x00100000)
177 #define VIC_IntEnable_AD1 (0x00200000)
178 #define VIC_IntEnable_USB (0x00400000)
179 #define VIC_IntEnable_MASK (0x007ffffd)
181 #define VIC_IntEnClr_WDT (0x00000001)
182 #define VIC_IntEnClr_ARMCore0 (0x00000004)
183 #define VIC_IntEnClr_ARMCore1 (0x00000008)
184 #define VIC_IntEnClr_Timer0 (0x00000010)
185 #define VIC_IntEnClr_Timer1 (0x00000020)
186 #define VIC_IntEnClr_UART0 (0x00000040)
187 #define VIC_IntEnClr_UART1 (0x00000080)
188 #define VIC_IntEnClr_PWM0 (0x00000100)
189 #define VIC_IntEnClr_I2C0 (0x00000200)
190 #define VIC_IntEnClr_SPI0 (0x00000400)
191 #define VIC_IntEnClr_SPI1 (0x00000800)
192 #define VIC_IntEnClr_SSP (0x00000800)
193 #define VIC_IntEnClr_PLL (0x00001000)
194 #define VIC_IntEnClr_RTC (0x00002000)
195 #define VIC_IntEnClr_EINT0 (0x00004000)
196 #define VIC_IntEnClr_EINT1 (0x00008000)
197 #define VIC_IntEnClr_EINT2 (0x00010000)
198 #define VIC_IntEnClr_EINT3 (0x00020000)
199 #define VIC_IntEnClr_AD0 (0x00040000)
200 #define VIC_IntEnClr_I2C1 (0x00080000)
201 #define VIC_IntEnClr_BOD (0x00100000)
202 #define VIC_IntEnClr_AD1 (0x00200000)
203 #define VIC_IntEnClr_USB (0x00400000)
204 #define VIC_IntEnClr_MASK (0x007ffffd)
206 #define VIC_IntSelect_WDT (0x00000001)
207 #define VIC_IntSelect_ARMCore0 (0x00000004)
208 #define VIC_IntSelect_ARMCore1 (0x00000008)
209 #define VIC_IntSelect_Timer0 (0x00000010)
210 #define VIC_IntSelect_Timer1 (0x00000020)
211 #define VIC_IntSelect_UART0 (0x00000040)
212 #define VIC_IntSelect_UART1 (0x00000080)
213 #define VIC_IntSelect_PWM0 (0x00000100)
214 #define VIC_IntSelect_I2C0 (0x00000200)
215 #define VIC_IntSelect_SPI0 (0x00000400)
216 #define VIC_IntSelect_SPI1 (0x00000800)
217 #define VIC_IntSelect_SSP (0x00000800)
218 #define VIC_IntSelect_PLL (0x00001000)
219 #define VIC_IntSelect_RTC (0x00002000)
220 #define VIC_IntSelect_EINT0 (0x00004000)
221 #define VIC_IntSelect_EINT1 (0x00008000)
222 #define VIC_IntSelect_EINT2 (0x00010000)
223 #define VIC_IntSelect_EINT3 (0x00020000)
224 #define VIC_IntSelect_AD0 (0x00040000)
225 #define VIC_IntSelect_I2C1 (0x00080000)
226 #define VIC_IntSelect_BOD (0x00100000)
227 #define VIC_IntSelect_AD1 (0x00200000)
228 #define VIC_IntSelect_USB (0x00400000)
229 #define VIC_IntSelect_MASK (0x007ffffd)
231 #define VIC_IRQStatus_WDT (0x00000001)
232 #define VIC_IRQStatus_ARMCore0 (0x00000004)
233 #define VIC_IRQStatus_ARMCore1 (0x00000008)
234 #define VIC_IRQStatus_Timer0 (0x00000010)
235 #define VIC_IRQStatus_Timer1 (0x00000020)
236 #define VIC_IRQStatus_UART0 (0x00000040)
237 #define VIC_IRQStatus_UART1 (0x00000080)
238 #define VIC_IRQStatus_PWM0 (0x00000100)
239 #define VIC_IRQStatus_I2C0 (0x00000200)
240 #define VIC_IRQStatus_SPI0 (0x00000400)
241 #define VIC_IRQStatus_SPI1 (0x00000800)
242 #define VIC_IRQStatus_SSP (0x00000800)
243 #define VIC_IRQStatus_PLL (0x00001000)
244 #define VIC_IRQStatus_RTC (0x00002000)
245 #define VIC_IRQStatus_EINT0 (0x00004000)
246 #define VIC_IRQStatus_EINT1 (0x00008000)
247 #define VIC_IRQStatus_EINT2 (0x00010000)
248 #define VIC_IRQStatus_EINT3 (0x00020000)
249 #define VIC_IRQStatus_AD0 (0x00040000)
250 #define VIC_IRQStatus_I2C1 (0x00080000)
251 #define VIC_IRQStatus_BOD (0x00100000)
252 #define VIC_IRQStatus_AD1 (0x00200000)
253 #define VIC_IRQStatus_USB (0x00400000)
254 #define VIC_IRQStatus_MASK (0x007ffffd)
256 #define VIC_FIQStatus_WDT (0x00000001)
257 #define VIC_FIQStatus_ARMCore0 (0x00000004)
258 #define VIC_FIQStatus_ARMCore1 (0x00000008)
259 #define VIC_FIQStatus_Timer0 (0x00000010)
260 #define VIC_FIQStatus_Timer1 (0x00000020)
261 #define VIC_FIQStatus_UART0 (0x00000040)
262 #define VIC_FIQStatus_UART1 (0x00000080)
263 #define VIC_FIQStatus_PWM0 (0x00000100)
264 #define VIC_FIQStatus_I2C0 (0x00000200)
265 #define VIC_FIQStatus_SPI0 (0x00000400)
266 #define VIC_FIQStatus_SPI1 (0x00000800)
267 #define VIC_FIQStatus_SSP (0x00000800)
268 #define VIC_FIQStatus_PLL (0x00001000)
269 #define VIC_FIQStatus_RTC (0x00002000)
270 #define VIC_FIQStatus_EINT0 (0x00004000)
271 #define VIC_FIQStatus_EINT1 (0x00008000)
272 #define VIC_FIQStatus_EINT2 (0x00010000)
273 #define VIC_FIQStatus_EINT3 (0x00020000)
274 #define VIC_FIQStatus_AD0 (0x00040000)
275 #define VIC_FIQStatus_I2C1 (0x00080000)
276 #define VIC_FIQStatus_BOD (0x00100000)
277 #define VIC_FIQStatus_AD1 (0x00200000)
278 #define VIC_FIQStatus_USB (0x00400000)
279 #define VIC_FIQStatus_MASK (0x007ffffd)
281 #define VIC_VectCntl_SLOTMASK (0x0000001f)
282 #define VIC_VectCntl_ENABLE (0x00000020)
284 #define VIC_Protection_ACCESS (0x00000001)
285 #define VIC_Protection_MASK (0x00000001)
287 #define VIC_Mask_WDT (0x00000001)
288 #define VIC_Mask_RSVD (0x00000002)
289 #define VIC_Mask_ARMCore0 (0x00000004)
290 #define VIC_Mask_ARMCore1 (0x00000008)
291 #define VIC_Mask_Timer0 (0x00000010)
292 #define VIC_Mask_Timer1 (0x00000020)
293 #define VIC_Mask_UART0 (0x00000040)
294 #define VIC_Mask_UART1 (0x00000080)
295 #define VIC_Mask_PWM0 (0x00000100)
296 #define VIC_Mask_I2C0 (0x00000200)
297 #define VIC_Mask_SPI0 (0x00000400)
298 #define VIC_Mask_SPI1 (0x00000800)
299 #define VIC_Mask_SSP (0x00000800)
300 #define VIC_Mask_PLL (0x00001000)
301 #define VIC_Mask_RTC (0x00002000)
302 #define VIC_Mask_EINT0 (0x00004000)
303 #define VIC_Mask_EINT1 (0x00008000)
304 #define VIC_Mask_EINT2 (0x00010000)
305 #define VIC_Mask_EINT3 (0x00020000)
306 #define VIC_Mask_AD0 (0x00040000)
307 #define VIC_Mask_I2C1 (0x00080000)
308 #define VIC_Mask_BOD (0x00100000)
309 #define VIC_Mask_AD1 (0x00200000)
310 #define VIC_Mask_USB (0x00400000)
311 #define VIC_Mask_MASK (0x007ffffd)
313 #define VIC_Channel_WDT (0)
314 #define VIC_Channel_RSVD (1)
315 #define VIC_Channel_ARMCore0 (2)
316 #define VIC_Channel_ARMCore1 (3)
317 #define VIC_Channel_Timer0 (4)
318 #define VIC_Channel_Timer1 (5)
319 #define VIC_Channel_UART0 (6)
320 #define VIC_Channel_UART1 (7)
321 #define VIC_Channel_PWM0 (8)
322 #define VIC_Channel_I2C0 (9)
323 #define VIC_Channel_SPI0 (10)
324 #define VIC_Channel_SPI1 (11)
325 #define VIC_Channel_SSP (11)
326 #define VIC_Channel_PLL (12)
327 #define VIC_Channel_RTC (13)
328 #define VIC_Channel_EINT0 (14)
329 #define VIC_Channel_EINT1 (15)
330 #define VIC_Channel_EINT2 (16)
331 #define VIC_Channel_EINT3 (17)
332 #define VIC_Channel_AD0 (18)
333 #define VIC_Channel_I2C1 (19)
334 #define VIC_Channel_BOD (20)
335 #define VIC_Channel_AD1 (21)
336 #define VIC_Channel_USB (22)
339 /*##############################################################################
340 ## PCB - Pin Connect Block
341 ##############################################################################*/
343 #define PCB_PINSEL0 (*(pREG32 (0xe002c000)))
344 #define PCB_PINSEL1 (*(pREG32 (0xe002c004)))
346 #define PCB_PINSEL0_P00_GPIO ((unsigned int) 0x00000000)
347 #define PCB_PINSEL0_P00_TXD0 ((unsigned int) 0x00000001)
348 #define PCB_PINSEL0_P00_PWM1 ((unsigned int) 0x00000002)
349 #define PCB_PINSEL0_P00_RSVD3 ((unsigned int) 0x00000003)
350 #define PCB_PINSEL0_P00_MASK ((unsigned int) 0x00000003)
352 #define PCB_PINSEL0_P01_GPIO ((unsigned int) 0x00000000)
353 #define PCB_PINSEL0_P01_RXD0 ((unsigned int) 0x00000004)
354 #define PCB_PINSEL0_P01_PWM3 ((unsigned int) 0x00000008)
355 #define PCB_PINSEL0_P01_EINT0 ((unsigned int) 0x0000000c)
356 #define PCB_PINSEL0_P01_MASK ((unsigned int) 0x0000000c)
358 #define PCB_PINSEL0_P02_GPIO ((unsigned int) 0x00000000)
359 #define PCB_PINSEL0_P02_SCL0 ((unsigned int) 0x00000010)
360 #define PCB_PINSEL0_P02_CAP00 ((unsigned int) 0x00000020)
361 #define PCB_PINSEL0_P02_RSVD3 ((unsigned int) 0x00000030)
362 #define PCB_PINSEL0_P02_MASK ((unsigned int) 0x00000030)
364 #define PCB_PINSEL0_P03_GPIO ((unsigned int) 0x00000000)
365 #define PCB_PINSEL0_P03_SDA0 ((unsigned int) 0x00000040)
366 #define PCB_PINSEL0_P03_MAT00 ((unsigned int) 0x00000080)
367 #define PCB_PINSEL0_P03_EINT1 ((unsigned int) 0x000000c0)
368 #define PCB_PINSEL0_P03_MASK ((unsigned int) 0x000000c0)
370 #define PCB_PINSEL0_P04_GPIO ((unsigned int) 0x00000000)
371 #define PCB_PINSEL0_P04_SCK0 ((unsigned int) 0x00000100)
372 #define PCB_PINSEL0_P04_CAP01 ((unsigned int) 0x00000200)
373 #define PCB_PINSEL0_P04_RSVD3 ((unsigned int) 0x00000300)
374 #define PCB_PINSEL0_P04_MASK ((unsigned int) 0x00000300)
376 #define PCB_PINSEL0_P05_GPIO ((unsigned int) 0x00000000)
377 #define PCB_PINSEL0_P05_MISO0 ((unsigned int) 0x00000400)
378 #define PCB_PINSEL0_P05_MAT01 ((unsigned int) 0x00000800)
379 #define PCB_PINSEL0_P05_AD06 ((unsigned int) 0x00000c00)
380 #define PCB_PINSEL0_P05_MASK ((unsigned int) 0x00000c00)
382 #define PCB_PINSEL0_P06_GPIO ((unsigned int) 0x00000000)
383 #define PCB_PINSEL0_P06_MOSI0 ((unsigned int) 0x00001000)
384 #define PCB_PINSEL0_P06_CAP02 ((unsigned int) 0x00002000)
385 #define PCB_PINSEL0_P06_AD10 ((unsigned int) 0x00003000)
386 #define PCB_PINSEL0_P06_MASK ((unsigned int) 0x00003000)
388 #define PCB_PINSEL0_P07_GPIO ((unsigned int) 0x00000000)
389 #define PCB_PINSEL0_P07_SSEL0 ((unsigned int) 0x00004000)
390 #define PCB_PINSEL0_P07_PWM2 ((unsigned int) 0x00008000)
391 #define PCB_PINSEL0_P07_EINT2 ((unsigned int) 0x0000c000)
392 #define PCB_PINSEL0_P07_MASK ((unsigned int) 0x0000c000)
394 #define PCB_PINSEL0_P08_GPIO ((unsigned int) 0x00000000)
395 #define PCB_PINSEL0_P08_TXD1 ((unsigned int) 0x00010000)
396 #define PCB_PINSEL0_P08_PWM4 ((unsigned int) 0x00020000)
397 #define PCB_PINSEL0_P08_AD11 ((unsigned int) 0x00030000)
398 #define PCB_PINSEL0_P08_MASK ((unsigned int) 0x00030000)
400 #define PCB_PINSEL0_P09_GPIO ((unsigned int) 0x00000000)
401 #define PCB_PINSEL0_P09_RXD1 ((unsigned int) 0x00040000)
402 #define PCB_PINSEL0_P09_PWM6 ((unsigned int) 0x00080000)
403 #define PCB_PINSEL0_P09_EINT3 ((unsigned int) 0x000c0000)
404 #define PCB_PINSEL0_P09_MASK ((unsigned int) 0x000c0000)
406 #define PCB_PINSEL0_P010_GPIO ((unsigned int) 0x00000000)
407 #define PCB_PINSEL0_P010_RTS1 ((unsigned int) 0x00100000)
408 #define PCB_PINSEL0_P010_CAP10 ((unsigned int) 0x00200000)
409 #define PCB_PINSEL0_P010_AD12 ((unsigned int) 0x00300000)
410 #define PCB_PINSEL0_P010_MASK ((unsigned int) 0x00300000)
412 #define PCB_PINSEL0_P011_GPIO ((unsigned int) 0x00000000)
413 #define PCB_PINSEL0_P011_CTS1 ((unsigned int) 0x00400000)
414 #define PCB_PINSEL0_P011_CAP11 ((unsigned int) 0x00800000)
415 #define PCB_PINSEL0_P011_SCL1 ((unsigned int) 0x00c00000)
416 #define PCB_PINSEL0_P011_MASK ((unsigned int) 0x00c00000)
418 #define PCB_PINSEL0_P012_GPIO ((unsigned int) 0x00000000)
419 #define PCB_PINSEL0_P012_DSR1 ((unsigned int) 0x01000000)
420 #define PCB_PINSEL0_P012_MAT10 ((unsigned int) 0x02000000)
421 #define PCB_PINSEL0_P012_AD13 ((unsigned int) 0x03000000)
422 #define PCB_PINSEL0_P012_MASK ((unsigned int) 0x03000000)
424 #define PCB_PINSEL0_P013_GPIO ((unsigned int) 0x00000000)
425 #define PCB_PINSEL0_P013_DTR1 ((unsigned int) 0x04000000)
426 #define PCB_PINSEL0_P013_MAT11 ((unsigned int) 0x08000000)
427 #define PCB_PINSEL0_P013_AD14 ((unsigned int) 0x0c000000)
428 #define PCB_PINSEL0_P013_MASK ((unsigned int) 0x0c000000)
430 #define PCB_PINSEL0_P014_GPIO ((unsigned int) 0x00000000)
431 #define PCB_PINSEL0_P014_DCD1 ((unsigned int) 0x10000000)
432 #define PCB_PINSEL0_P014_EINT1 ((unsigned int) 0x20000000)
433 #define PCB_PINSEL0_P014_SDA1 ((unsigned int) 0x30000000)
434 #define PCB_PINSEL0_P014_MASK ((unsigned int) 0x30000000)
436 #define PCB_PINSEL0_P015_GPIO ((unsigned int) 0x00000000)
437 #define PCB_PINSEL0_P015_RI1 ((unsigned int) 0x40000000)
438 #define PCB_PINSEL0_P015_EINT2 ((unsigned int) 0x80000000)
439 #define PCB_PINSEL0_P015_AD15 ((unsigned int) 0xc0000000)
440 #define PCB_PINSEL0_P015_MASK ((unsigned int) 0xc0000000)
442 #define PCB_PINSEL1_P016_GPIO ((unsigned int) 0x00000000)
443 #define PCB_PINSEL1_P016_EINT0 ((unsigned int) 0x00000001)
444 #define PCB_PINSEL1_P016_MAT02 ((unsigned int) 0x00000002)
445 #define PCB_PINSEL1_P016_CAP02 ((unsigned int) 0x00000003)
446 #define PCB_PINSEL1_P016_MASK ((unsigned int) 0x00000003)
448 #define PCB_PINSEL1_P017_GPIO ((unsigned int) 0x00000000)
449 #define PCB_PINSEL1_P017_CAP12 ((unsigned int) 0x00000004)
450 #define PCB_PINSEL1_P017_SCK1 ((unsigned int) 0x00000008)
451 #define PCB_PINSEL1_P017_MAT12 ((unsigned int) 0x0000000c)
452 #define PCB_PINSEL1_P017_MASK ((unsigned int) 0x0000000c)
454 #define PCB_PINSEL1_P018_GPIO ((unsigned int) 0x00000000)
455 #define PCB_PINSEL1_P018_CAP13 ((unsigned int) 0x00000010)
456 #define PCB_PINSEL1_P018_MISO1 ((unsigned int) 0x00000020)
457 #define PCB_PINSEL1_P018_MAT13 ((unsigned int) 0x00000030)
458 #define PCB_PINSEL1_P018_MASK ((unsigned int) 0x00000030)
460 #define PCB_PINSEL1_P019_GPIO ((unsigned int) 0x00000000)
461 #define PCB_PINSEL1_P019_MAT12 ((unsigned int) 0x00000040)
462 #define PCB_PINSEL1_P019_MOSI1 ((unsigned int) 0x00000080)
463 #define PCB_PINSEL1_P019_CAP12 ((unsigned int) 0x000000c0)
465 #define PCB_PINSEL1_P020_GPIO ((unsigned int) 0x00000000)
466 #define PCB_PINSEL1_P020_MAT13 ((unsigned int) 0x00000100)
467 #define PCB_PINSEL1_P020_SSEL1 ((unsigned int) 0x00000200)
468 #define PCB_PINSEL1_P020_EINT3 ((unsigned int) 0x00000300)
469 #define PCB_PINSEL1_P020_MASK ((unsigned int) 0x00000300)
471 #define PCB_PINSEL1_P021_GPIO ((unsigned int) 0x00000000)
472 #define PCB_PINSEL1_P021_PWM5 ((unsigned int) 0x00000400)
473 #define PCB_PINSEL1_P021_AD16 ((unsigned int) 0x00000800)
474 #define PCB_PINSEL1_P021_CAP13 ((unsigned int) 0x00000c00)
475 #define PCB_PINSEL1_P021_MASK ((unsigned int) 0x00000c00)
477 #define PCB_PINSEL1_P022_GPIO ((unsigned int) 0x00000000)
478 #define PCB_PINSEL1_P022_AD17 ((unsigned int) 0x00001000)
479 #define PCB_PINSEL1_P022_CAP00 ((unsigned int) 0x00002000)
480 #define PCB_PINSEL1_P022_MAT00 ((unsigned int) 0x00003000)
481 #define PCB_PINSEL1_P022_MASK ((unsigned int) 0x00003000)
483 #define PCB_PINSEL1_P023_GPIO ((unsigned int) 0x00000000)
484 #define PCB_PINSEL1_P023_VBUS ((unsigned int) 0x00004000)
485 #define PCB_PINSEL1_P023_RSVD2 ((unsigned int) 0x00008000)
486 #define PCB_PINSEL1_P023_RSVD3 ((unsigned int) 0x0000c000)
487 #define PCB_PINSEL1_P023_MASK ((unsigned int) 0x0000c000)
489 #define PCB_PINSEL1_P024_RSVD0 ((unsigned int) 0x00000000)
490 #define PCB_PINSEL1_P024_RSVD1 ((unsigned int) 0x00010000)
491 #define PCB_PINSEL1_P024_RSVD2 ((unsigned int) 0x00020000)
492 #define PCB_PINSEL1_P024_RSVD3 ((unsigned int) 0x00030000)
493 #define PCB_PINSEL1_P024_MASK ((unsigned int) 0x00030000)
495 #define PCB_PINSEL1_P025_GPIO ((unsigned int) 0x00000000)
496 #define PCB_PINSEL1_P025_AD04 ((unsigned int) 0x00040000)
497 #define PCB_PINSEL1_P025_AOUT ((unsigned int) 0x00080000)
498 #define PCB_PINSEL1_P025_RSVD3 ((unsigned int) 0x000c0000)
499 #define PCB_PINSEL1_P025_MASK ((unsigned int) 0x000c0000)
501 #define PCB_PINSEL1_P026_RSVD0 ((unsigned int) 0x00000000)
502 #define PCB_PINSEL1_P026_RSVD1 ((unsigned int) 0x00100000)
503 #define PCB_PINSEL1_P026_RSVD2 ((unsigned int) 0x00200000)
504 #define PCB_PINSEL1_P026_RSVD3 ((unsigned int) 0x00300000)
505 #define PCB_PINSEL1_P026_MASK ((unsigned int) 0x00300000)
507 #define PCB_PINSEL1_P027_RSVD0 ((unsigned int) 0x00000000)
508 #define PCB_PINSEL1_P027_RSVD1 ((unsigned int) 0x00400000)
509 #define PCB_PINSEL1_P027_RSVD2 ((unsigned int) 0x00800000)
510 #define PCB_PINSEL1_P027_RSVD3 ((unsigned int) 0x00c00000)
511 #define PCB_PINSEL1_P027_MASK ((unsigned int) 0x00c00000)
513 #define PCB_PINSEL1_P028_GPIO ((unsigned int) 0x00000000)
514 #define PCB_PINSEL1_P028_AD01 ((unsigned int) 0x01000000)
515 #define PCB_PINSEL1_P028_CAP02 ((unsigned int) 0x02000000)
516 #define PCB_PINSEL1_P028_MAT02 ((unsigned int) 0x03000000)
517 #define PCB_PINSEL1_P028_MASK ((unsigned int) 0x03000000)
519 #define PCB_PINSEL1_P029_GPIO ((unsigned int) 0x00000000)
520 #define PCB_PINSEL1_P029_AD02 ((unsigned int) 0x04000000)
521 #define PCB_PINSEL1_P029_CAP03 ((unsigned int) 0x08000000)
522 #define PCB_PINSEL1_P029_MAT03 ((unsigned int) 0x0c000000)
523 #define PCB_PINSEL1_P029_MASK ((unsigned int) 0x0c000000)
525 #define PCB_PINSEL1_P030_GPIO ((unsigned int) 0x00000000)
526 #define PCB_PINSEL1_P030_AD03 ((unsigned int) 0x10000000)
527 #define PCB_PINSEL1_P030_EINT3 ((unsigned int) 0x20000000)
528 #define PCB_PINSEL1_P030_CAP00 ((unsigned int) 0x30000000)
529 #define PCB_PINSEL1_P030_MASK ((unsigned int) 0x30000000)
531 #define PCB_PINSEL1_P031_GPIO ((unsigned int) 0x00000000)
532 #define PCB_PINSEL1_P031_UPLED ((unsigned int) 0x40000000)
533 #define PCB_PINSEL1_P031_CONNECT ((unsigned int) 0x80000000)
534 #define PCB_PINSEL1_P031_RSVD3 ((unsigned int) 0xc0000000)
535 #define PCB_PINSEL1_P031_MASK ((unsigned int) 0xc0000000)
538 /*##############################################################################
539 ## GPIO - General Purpose I/O
540 ##############################################################################*/
542 #define GPIO0_IOPIN (*(pREG32 (0xe0028000)))
543 #define GPIO0_IOSET (*(pREG32 (0xe0028004)))
544 #define GPIO0_IODIR (*(pREG32 (0xe0028008)))
545 #define GPIO0_IOCLR (*(pREG32 (0xe002800c)))
546 #define GPIO1_IOPIN (*(pREG32 (0xe0028010)))
547 #define GPIO1_IOSET (*(pREG32 (0xe0028014)))
548 #define GPIO1_IODIR (*(pREG32 (0xe0028018)))
549 #define GPIO1_IOCLR (*(pREG32 (0xe002801c)))
551 #define GPIO_IO_P0 ((unsigned int) 0x00000001)
552 #define GPIO_IO_P1 ((unsigned int) 0x00000002)
553 #define GPIO_IO_P2 ((unsigned int) 0x00000004)
554 #define GPIO_IO_P3 ((unsigned int) 0x00000008)
555 #define GPIO_IO_P4 ((unsigned int) 0x00000010)
556 #define GPIO_IO_P5 ((unsigned int) 0x00000020)
557 #define GPIO_IO_P6 ((unsigned int) 0x00000040)
558 #define GPIO_IO_P7 ((unsigned int) 0x00000080)
559 #define GPIO_IO_P8 ((unsigned int) 0x00000100)
560 #define GPIO_IO_P9 ((unsigned int) 0x00000200)
561 #define GPIO_IO_P10 ((unsigned int) 0x00000400)
562 #define GPIO_IO_P11 ((unsigned int) 0x00000800)
563 #define GPIO_IO_P12 ((unsigned int) 0x00001000)
564 #define GPIO_IO_P13 ((unsigned int) 0x00002000)
565 #define GPIO_IO_P14 ((unsigned int) 0x00004000)
566 #define GPIO_IO_P15 ((unsigned int) 0x00008000)
567 #define GPIO_IO_P16 ((unsigned int) 0x00010000)
568 #define GPIO_IO_P17 ((unsigned int) 0x00020000)
569 #define GPIO_IO_P18 ((unsigned int) 0x00040000)
570 #define GPIO_IO_P19 ((unsigned int) 0x00080000)
571 #define GPIO_IO_P20 ((unsigned int) 0x00100000)
572 #define GPIO_IO_P21 ((unsigned int) 0x00200000)
573 #define GPIO_IO_P22 ((unsigned int) 0x00400000)
574 #define GPIO_IO_P23 ((unsigned int) 0x00800000)
575 #define GPIO_IO_P24 ((unsigned int) 0x01000000)
576 #define GPIO_IO_P25 ((unsigned int) 0x02000000)
577 #define GPIO_IO_P26 ((unsigned int) 0x04000000)
578 #define GPIO_IO_P27 ((unsigned int) 0x08000000)
579 #define GPIO_IO_P28 ((unsigned int) 0x10000000)
580 #define GPIO_IO_P29 ((unsigned int) 0x20000000)
581 #define GPIO_IO_P30 ((unsigned int) 0x40000000)
582 #define GPIO_IO_P31 ((unsigned int) 0x80000000)
583 #define GPIO_IO_JTAG ((unsigned int) 0x003e0000)
586 /*##############################################################################
588 ##############################################################################*/
590 #define UART0_RBR (*(pREG32 (0xe000c000)))
591 #define UART0_THR (*(pREG32 (0xe000c000)))
592 #define UART0_IER (*(pREG32 (0xe000c004)))
593 #define UART0_IIR (*(pREG32 (0xe000c008)))
594 #define UART0_FCR (*(pREG32 (0xe000c008)))
595 #define UART0_LCR (*(pREG32 (0xe000c00c)))
596 #define UART0_LSR (*(pREG32 (0xe000c014)))
597 #define UART0_SCR (*(pREG32 (0xe000c01c)))
598 #define UART0_ACR (*(pREG32 (0xe0000020)))
599 #define UART0_FDR (*(pREG32 (0xe0000028)))
600 #define UART0_TER (*(pREG32 (0xe0000030)))
601 #define UART0_DLL (*(pREG32 (0xe000c000)))
602 #define UART0_DLM (*(pREG32 (0xe000c004)))
604 #define UART1_RBR (*(pREG32 (0xe0010000)))
605 #define UART1_THR (*(pREG32 (0xe0010000)))
606 #define UART1_IER (*(pREG32 (0xe0010004)))
607 #define UART1_IIR (*(pREG32 (0xe0010008)))
608 #define UART1_FCR (*(pREG32 (0xe0010008)))
609 #define UART1_LCR (*(pREG32 (0xe001000c)))
610 #define UART1_LSR (*(pREG32 (0xe0010014)))
611 #define UART1_SCR (*(pREG32 (0xe001001c)))
612 #define UART1_ACR (*(pREG32 (0xe0010020)))
613 #define UART1_FDR (*(pREG32 (0xe0010028)))
614 #define UART1_TER (*(pREG32 (0xe0010030)))
615 #define UART1_DLL (*(pREG32 (0xe0010000)))
616 #define UART1_DLM (*(pREG32 (0xe0010004)))
617 #define UART1_MCR (*(pREG32 (0xe0010010)))
618 #define UART1_MSR (*(pREG32 (0xe0010018)))
620 #define UART_LCR_DLAB (0x00000080)
621 #define UART_LCR_NOPAR (0x00000000)
622 #define UART_LCR_1STOP (0x00000000)
623 #define UART_LCR_8BITS (0x00000003)
624 #define UART_IER_EI (0x00000003)
625 #define UART_FCR_EN (0x00000001)
626 #define UART_FCR_CLR (0x00000006)
629 /*##############################################################################
631 ##############################################################################*/
633 #define I2C0_CONSET (*(pREG32 (0xe001c000)))
634 #define I2C0_STAT (*(pREG32 (0xe001c004)))
635 #define I2C0_DAT (*(pREG32 (0xe001c008)))
636 #define I2C0_ADR (*(pREG32 (0xe001c00c)))
637 #define I2C0_SCLH (*(pREG32 (0xe001c010)))
638 #define I2C0_SCLL (*(pREG32 (0xe001c014)))
639 #define I2C0_CONCLR (*(pREG32 (0xe001c018)))
641 #define I2C1_CONSET (*(pREG32 (0xe005c000)))
642 #define I2C1_STAT (*(pREG32 (0xe005c004)))
643 #define I2C1_DAT (*(pREG32 (0xe005c008)))
644 #define I2C1_ADR (*(pREG32 (0xe005c00c)))
645 #define I2C1_SCLH (*(pREG32 (0xe005c010)))
646 #define I2C1_SCLL (*(pREG32 (0xe005c014)))
647 #define I2C1_CONCLR (*(pREG32 (0xe005c018)))
649 #define I2C_CONSET_AA (0x00000004)
650 #define I2C_CONSET_SI (0x00000008)
651 #define I2C_CONSET_STO (0x00000010)
652 #define I2C_CONSET_STA (0x00000020)
653 #define I2C_CONSET_I2EN (0x00000040)
654 #define I2C_CONSET_MASK (0x0000007c)
656 #define I2C_STAT_STATMASK (0x000000f8)
657 #define I2C_STAT_STATSHIFT (3)
659 #define I2C_ADDR_GC (0x00000001)
660 #define I2C_ADDR_ADDRMASK (0x000000fe)
661 #define I2C_ADDR_ADDRSHIFT (1)
663 #define I2C_CONCLR_AAC (0x00000004)
664 #define I2C_CONCLR_SIC (0x00000008)
665 #define I2C_CONCLR_STAC (0x00000020)
666 #define I2C_CONCLR_I2ENC (0x00000040)
667 #define I2C_CONCLR_MASK (0x0000006c)
670 /*##############################################################################
671 ## SPI - Serial Peripheral Interface
672 ##############################################################################*/
674 #define SPI_SPCR (*(pREG32 (0xe0020000)))
675 #define SPI_SPSR (*(pREG32 (0xe0020004)))
676 #define SPI_SPDR (*(pREG32 (0xe0020008)))
677 #define SPI_SPCCR (*(pREG32 (0xe002000c)))
678 #define SPI_SPTCR (*(pREG32 (0xe0020010)))
679 #define SPI_SPTSR (*(pREG32 (0xe0020014)))
680 #define SPI_SPTOR (*(pREG32 (0xe0020018)))
681 #define SPI_SPINT (*(pREG32 (0xe002001c)))
684 /*##############################################################################
685 ## SSP - Synchronous Serial Port
686 ##############################################################################*/
688 #define SSP_CR0 (*(pREG32 (0xe0068000)))
689 #define SSP_CR1 (*(pREG32 (0xe0068004)))
690 #define SSP_DR (*(pREG32 (0xe0068008)))
691 #define SSP_SR (*(pREG32 (0xe006800C)))
692 #define SSP_CPSR (*(pREG32 (0xe0068010)))
693 #define SSP_IMSC (*(pREG32 (0xe0068014)))
694 #define SSP_RIS (*(pREG32 (0xe0068018)))
695 #define SSP_MIS (*(pREG32 (0xe006801C)))
696 #define SSP_ICR (*(pREG32 (0xe0068020)))
698 #define SSP_FIFO_DEPTH (8)
700 #define SSP_CR0_DSS_4 ((unsigned int) 0x00000003)
701 #define SSP_CR0_DSS_5 ((unsigned int) 0x00000004)
702 #define SSP_CR0_DSS_6 ((unsigned int) 0x00000005)
703 #define SSP_CR0_DSS_7 ((unsigned int) 0x00000006)
704 #define SSP_CR0_DSS_8 ((unsigned int) 0x00000007)
705 #define SSP_CR0_DSS_9 ((unsigned int) 0x00000008)
706 #define SSP_CR0_DSS 10 ((unsigned int) 0x00000009)
707 #define SSP_CR0_DSS_11 ((unsigned int) 0x0000000a)
708 #define SSP_CR0_DSS_12 ((unsigned int) 0x0000000b)
709 #define SSP_CR0_DSS_13 ((unsigned int) 0x0000000c)
710 #define SSP_CR0_DSS_14 ((unsigned int) 0x0000000d)
711 #define SSP_CR0_DSS_15 ((unsigned int) 0x0000000e)
712 #define SSP_CR0_DSS_16 ((unsigned int) 0x0000000f)
713 #define SSP_CR0_FRF_SPI ((unsigned int) 0x00000000)
714 #define SSP_CR0_FRF_SSI ((unsigned int) 0x00000010)
715 #define SSP_CR0_FRF_MW ((unsigned int) 0x00000020)
716 #define SSP_CR0_CPOL ((unsigned int) 0x00000040)
717 #define SSP_CR0_CPHA ((unsigned int) 0x00000080)
718 #define SSP_CR0_SCR ((unsigned int) 0x0000ff00)
720 #define SSP_CR1_LBM ((unsigned int) 0x00000001)
721 #define SSP_CR1_SSE ((unsigned int) 0x00000002)
722 #define SSP_CR1_MS ((unsigned int) 0x00000004)
723 #define SSP_CR1_SOD ((unsigned int) 0x00000008)
725 #define SSP_SR_TFE ((unsigned int) 0x00000001)
726 #define SSP_SR_TNF ((unsigned int) 0x00000002)
727 #define SSP_SR_RNE ((unsigned int) 0x00000004)
728 #define SSP_SR_RFF ((unsigned int) 0x00000008)
729 #define SSP_SR_BSY ((unsigned int) 0x00000010)
731 #define SSP_IMSC_RORIM ((unsigned int) 0x00000001)
732 #define SSP_IMSC_RTIM ((unsigned int) 0x00000002)
733 #define SSP_IMSC_RXIM ((unsigned int) 0x00000004)
734 #define SSP_IMSC_TXIM ((unsigned int) 0x00000008)
736 #define SSP_RIS_RORRIS ((unsigned int) 0x00000001)
737 #define SSP_RIS_RTRIS ((unsigned int) 0x00000002)
738 #define SSP_RIS_RXRIS ((unsigned int) 0x00000004)
739 #define SSP_RIS_TXRIS ((unsigned int) 0x00000008)
741 #define SSP_MIS_RORMIS ((unsigned int) 0x00000001)
742 #define SSP_MIS_RTMIS ((unsigned int) 0x00000002)
743 #define SSP_MIS_RXMIS ((unsigned int) 0x00000004)
744 #define SSP_MIS_TXMIS ((unsigned int) 0x00000008)
746 #define SSP_ICR_RORIC ((unsigned int) 0x00000001)
747 #define SSP_ICR_RTIC ((unsigned int) 0x00000002)
750 /*##############################################################################
751 ## Timer 0 and Timer 1
752 ##############################################################################*/
754 #define T0_BASE_ADDR (pREG32 (0xe0004000))
755 #define T0_IR (*(pREG32 (0xe0004000)))
756 #define T0_TCR (*(pREG32 (0xe0004004)))
757 #define T0_TC (*(pREG32 (0xe0004008)))
758 #define T0_PR (*(pREG32 (0xe000400c)))
759 #define T0_PC (*(pREG32 (0xe0004010)))
760 #define T0_MCR (*(pREG32 (0xe0004014)))
761 #define T0_MR0 (*(pREG32 (0xe0004018)))
762 #define T0_MR1 (*(pREG32 (0xe000401c)))
763 #define T0_MR2 (*(pREG32 (0xe0004020)))
764 #define T0_MR3 (*(pREG32 (0xe0004024)))
765 #define T0_CCR (*(pREG32 (0xe0004028)))
766 #define T0_CR0 (*(pREG32 (0xe000402c)))
767 #define T0_CR1 (*(pREG32 (0xe0004030)))
768 #define T0_CR2 (*(pREG32 (0xe0004034)))
769 #define T0_CR3 (*(pREG32 (0xe0004038)))
770 #define T0_EMR (*(pREG32 (0xe000403c)))
771 #define T0_CTCR (*(pREG32 (0xe0004070)))
773 #define T1_BASE_ADDR (pREG32 (0xe0008000))
774 #define T1_IR (*(pREG32 (0xe0008000)))
775 #define T1_TCR (*(pREG32 (0xe0008004)))
776 #define T1_TC (*(pREG32 (0xe0008008)))
777 #define T1_PR (*(pREG32 (0xe000800c)))
778 #define T1_PC (*(pREG32 (0xe0008010)))
779 #define T1_MCR (*(pREG32 (0xe0008014)))
780 #define T1_MR0 (*(pREG32 (0xe0008018)))
781 #define T1_MR1 (*(pREG32 (0xe000801c)))
782 #define T1_MR2 (*(pREG32 (0xe0008020)))
783 #define T1_MR3 (*(pREG32 (0xe0008024)))
784 #define T1_CCR (*(pREG32 (0xe0008028)))
785 #define T1_CR0 (*(pREG32 (0xe000802c)))
786 #define T1_CR1 (*(pREG32 (0xe0008030)))
787 #define T1_CR2 (*(pREG32 (0xe0008034)))
788 #define T1_CR3 (*(pREG32 (0xe0008038)))
789 #define T1_EMR (*(pREG32 (0xe000803c)))
790 #define T1_CTCR (*(pREG32 (0xe0008070)))
792 #define T_IR_MR0 (0x00000001)
793 #define T_IR_MR1 (0x00000002)
794 #define T_IR_MR2 (0x00000004)
795 #define T_IR_MR3 (0x00000008)
796 #define T_IR_CR0 (0x00000010)
797 #define T_IR_CR1 (0x00000020)
798 #define T_IR_CR2 (0x00000040)
799 #define T_IR_CR3 (0x00000080)
800 #define T_IR_MASK (0x000000ff)
802 #define T_TCR_CE (0x00000001)
803 #define T_TCR_CR (0x00000002)
805 #define T_CTCR_MODE_PCLK (0x00000000)
806 #define T_CTCR_MODE_CAPRISE (0x00000001)
807 #define T_CTCR_MODE_CAPFALL (0x00000002)
808 #define T_CTCR_MODE_CAPBOTH (0x00000003)
809 #define T_CTCR_MODE_MASK (0x00000003)
810 #define T_CTCR_CIS_CAPN0 (0x00000000)
811 #define T_CTCR_CIS_CAPN1 (0x00000004)
812 #define T_CTCR_CIS_CAPN2 (0x00000008)
813 #define T_CTCR_CIS_CAPN3 (0x0000000c)
814 #define T_CTCR_CIS_MASK (0x0000000c)
816 #define T_MCR_MR0I (0x00000001)
817 #define T_MCR_MR0R (0x00000002)
818 #define T_MCR_MR0S (0x00000004)
819 #define T_MCR_MR1I (0x00000008)
820 #define T_MCR_MR1R (0x00000010)
821 #define T_MCR_MR1S (0x00000020)
822 #define T_MCR_MR2I (0x00000040)
823 #define T_MCR_MR2R (0x00000080)
824 #define T_MCR_MR2S (0x00000100)
825 #define T_MCR_MR3I (0x00000200)
826 #define T_MCR_MR3R (0x00000400)
827 #define T_MCR_MR3S (0x00000800)
829 #define T_CCR_CAP0RE (0x00000001)
830 #define T_CCR_CAP0FE (0x00000002)
831 #define T_CCR_CAP0I (0x00000004)
832 #define T_CCR_CAP1RE (0x00000008)
833 #define T_CCR_CAP1FE (0x00000010)
834 #define T_CCR_CAP1I (0x00000020)
835 #define T_CCR_CAP2RE (0x00000040)
836 #define T_CCR_CAP2FE (0x00000080)
837 #define T_CCR_CAP2I (0x00000100)
838 #define T_CCR_CAP3RE (0x00000200)
839 #define T_CCR_CAP3FE (0x00000400)
840 #define T_CCR_CAP3I (0x00000800)
842 #define T_EMR_EM0 (0x00000001)
843 #define T_EMR_EM1 (0x00000002)
844 #define T_EMR_EM2 (0x00000004)
845 #define T_EMR_EM3 (0x00000008)
846 #define T_EMR_EMC0_NONE (0x00000000)
847 #define T_EMR_EMC0_CLEAR (0x00000010)
848 #define T_EMR_EMC0_SET (0x00000020)
849 #define T_EMR_EMC0_TOGGLE (0x00000030)
850 #define T_EMR_EMC0_MASK (0x00000030)
851 #define T_EMR_EMC1_NONE (0x00000000)
852 #define T_EMR_EMC1_CLEAR (0x00000040)
853 #define T_EMR_EMC1_SET (0x00000080)
854 #define T_EMR_EMC1_TOGGLE (0x000000c0)
855 #define T_EMR_EMC1_MASK (0x000000c0)
856 #define T_EMR_EMC2_NONE (0x00000000)
857 #define T_EMR_EMC2_CLEAR (0x00000100)
858 #define T_EMR_EMC2_SET (0x00000200)
859 #define T_EMR_EMC2_TOGGLE (0x00000300)
860 #define T_EMR_EMC2_MASK (0x00000300)
861 #define T_EMR_EMC3_NONE (0x00000000)
862 #define T_EMR_EMC3_CLEAR (0x00000400)
863 #define T_EMR_EMC3_SET (0x00000800)
864 #define T_EMR_EMC3_TOGGLE (0x00000c00)
865 #define T_EMR_EMC3_MASK (0x00000c00)
868 /*##############################################################################
870 ##############################################################################*/
872 #define AD0_CR (*(pREG32 (0xe0034000)))
873 #define AD0_GDR (*(pREG32 (0xe0034004)))
874 #define AD0_STAT (*(pREG32 (0xe0034030)))
875 #define AD0_GSR (*(pREG32 (0xe0034008)))
876 #define AD0_INTEN (*(pREG32 (0xe003400c)))
877 #define AD0_DR0 (*(pREG32 (0xe0034010)))
878 #define AD0_DR1 (*(pREG32 (0xe0034014)))
879 #define AD0_DR2 (*(pREG32 (0xe0034018)))
880 #define AD0_DR3 (*(pREG32 (0xe003401c)))
881 #define AD0_DR4 (*(pREG32 (0xe0034020)))
882 #define AD0_DR5 (*(pREG32 (0xe0034024)))
883 #define AD0_DR6 (*(pREG32 (0xe0034028)))
884 #define AD0_DR7 (*(pREG32 (0xe003402c)))
886 #define AD1_CR (*(pREG32 (0xe0060000)))
887 #define AD1_GDR (*(pREG32 (0xe0060004)))
888 #define AD1_STAT (*(pREG32 (0xe0060030)))
889 #define AD1_GSR (*(pREG32 (0xe0030008)))
890 #define AD1_INTEN (*(pREG32 (0xe006000c)))
891 #define AD1_DR0 (*(pREG32 (0xe0060010)))
892 #define AD1_DR1 (*(pREG32 (0xe0060014)))
893 #define AD1_DR2 (*(pREG32 (0xe0060018)))
894 #define AD1_DR3 (*(pREG32 (0xe006001c)))
895 #define AD1_DR4 (*(pREG32 (0xe0060020)))
896 #define AD1_DR5 (*(pREG32 (0xe0060024)))
897 #define AD1_DR6 (*(pREG32 (0xe0060028)))
898 #define AD1_DR7 (*(pREG32 (0xe006002c)))
900 #define AD_CR_SEL0 (0x00000001)
901 #define AD_CR_SEL1 (0x00000002)
902 #define AD_CR_SEL2 (0x00000004)
903 #define AD_CR_SEL3 (0x00000008)
904 #define AD_CR_SEL4 (0x00000010)
905 #define AD_CR_SEL5 (0x00000020)
906 #define AD_CR_SEL6 (0x00000040)
907 #define AD_CR_SEL7 (0x00000080)
908 #define AD_CR_CLKDIV (0x0000ff00)
909 #define AD_CR_CLKDIVMASK (0x0000ff00)
910 #define AD_CR_CLKDIVSHIFT (8)
911 #define AD_CR_BURST (0x00010000)
912 #define AD_CR_CLKS10 (0x00000000)
913 #define AD_CR_CLKS9 (0x00020000)
914 #define AD_CR_CLKS8 (0x00040000)
915 #define AD_CR_CLKS7 (0x00060000)
916 #define AD_CR_CLKS6 (0x00080000)
917 #define AD_CR_CLKS5 (0x000a0000)
918 #define AD_CR_CLKS4 (0x000c0000)
919 #define AD_CR_CLKS3 (0x000e0000)
920 #define AD_CR_PDN (0x00200000)
921 #define AD_CR_START_NONE (0x00000000)
922 #define AD_CR_START_NOW (0x01000000)
923 #define AD_CR_START_P016 (0x02000000)
924 #define AD_CR_START_P022 (0x03000000)
925 #define AD_CR_START_MAT01 (0x04000000)
926 #define AD_CR_START_MAT03 (0x05000000)
927 #define AD_CR_START_MAT10 (0x06000000)
928 #define AD_CR_START_MAT11 (0x07000000)
929 #define AD_CR_EDGE (0x08000000)
930 #define AD_CR_MASK (0x0f2fffff)
932 #define AD_GDR_RESULT (0x0000ffc0)
933 #define AD_GDR_CHN (0x07000000)
934 #define AD_GDR_CHNMASK (0x07000000)
935 #define AD_GDR_CHNSHIFT (24)
936 #define AD_GDR_OVERRUN (0x40000000)
937 #define AD_GDR_DONE (0x80000000)
938 #define AD_GDR_MASK (0xc700ffc0)
940 #define AD_GSR_BURST (0x00010000)
941 #define AD_GSR_START_NONE (0x00000000)
942 #define AD_GSR_START_NOW (0x01000000)
943 #define AD_GSR_START_P016 (0x02000000)
944 #define AD_GSR_START_P022 (0x03000000)
945 #define AD_GSR_START_MAT01 (0x04000000)
946 #define AD_GSR_START_MAT03 (0x05000000)
947 #define AD_GSR_START_MAT10 (0x06000000)
948 #define AD_GSR_START_MAT11 (0x07000000)
949 #define AD_GSR_EDGE (0x08000000)
950 #define AD_GSR_MASK (0x0f010000)
952 #define AD_STAT_RSVD (0x00000001)
953 #define AD_STAT_DONE0 (0x00000001)
954 #define AD_STAT_DONE1 (0x00000002)
955 #define AD_STAT_DONE2 (0x00000004)
956 #define AD_STAT_DONE3 (0x00000008)
957 #define AD_STAT_DONE4 (0x00000010)
958 #define AD_STAT_DONE5 (0x00000020)
959 #define AD_STAT_DONE6 (0x00000040)
960 #define AD_STAT_DONE7 (0x00000080)
961 #define AD_STAT_OVERRUN0 (0x00000100)
962 #define AD_STAT_OVERRUN1 (0x00000200)
963 #define AD_STAT_OVERRUN2 (0x00000400)
964 #define AD_STAT_OVERRUN3 (0x00000800)
965 #define AD_STAT_OVERRUN4 (0x00001000)
966 #define AD_STAT_OVERRUN5 (0x00002000)
967 #define AD_STAT_OVERRUN6 (0x00004000)
968 #define AD_STAT_OVERRUN7 (0x00008000)
969 #define AD_STAT_ADINT (0x00010000)
970 #define AD_STAT_MASK (0x0001ffff)
972 #define AD_INTEN_AD0 (0x00000001)
973 #define AD_INTEN_AD1 (0x00000002)
974 #define AD_INTEN_AD2 (0x00000004)
975 #define AD_INTEN_AD3 (0x00000008)
976 #define AD_INTEN_AD4 (0x00000010)
977 #define AD_INTEN_AD5 (0x00000020)
978 #define AD_INTEN_AD6 (0x00000040)
979 #define AD_INTEN_AD7 (0x00000080)
980 #define AD_INTEN_DONE (0x00000100)
981 #define AD_INTEN_MASK (0x000001ff)
983 #define AD_DR_RESULT (0x0000ffc0)
984 #define AD_DR_RESULTMASK (0x0000ffc0)
985 #define AD_DR_RESULTSHIFT (6)
986 #define AD_DR_OVERRUN (0x40000000)
987 #define AD_DR_DONE (0x80000000)
988 #define AD_DR_MASK (0xc000ffc0)
991 /*##############################################################################
993 ##############################################################################*/
995 #define DAC_CR (*(pREG32 (0xe006c000)))
997 #define DAC_CR_VALUE (0x0000ffc0)
998 #define DAC_CR_VALUEMASK (0x0000ffc0)
999 #define DAC_CR_VALUESHIFT (6)
1000 #define DAC_CR_BIAS (0x00010000)
1001 #define DAC_CR_MASK (0x0001ffc0)
1004 /*##############################################################################
1006 ##############################################################################*/
1008 #define PWM_IR (*(pREG32 (0xe0014000)))
1009 #define PWM_TCR (*(pREG32 (0xe0014004)))
1010 #define PWM_TC (*(pREG32 (0xe0014008)))
1011 #define PWM_PR (*(pREG32 (0xe001400c)))
1012 #define PWM_PC (*(pREG32 (0xe0014010)))
1013 #define PWM_MCR (*(pREG32 (0xe0014014)))
1014 #define PWM_MR0 (*(pREG32 (0xe0014018)))
1015 #define PWM_MR1 (*(pREG32 (0xe001401c)))
1016 #define PWM_MR2 (*(pREG32 (0xe0014020)))
1017 #define PWM_MR3 (*(pREG32 (0xe0014024)))
1018 #define PWM_MR4 (*(pREG32 (0xe0014040)))
1019 #define PWM_MR5 (*(pREG32 (0xe0014044)))
1020 #define PWM_MR6 (*(pREG32 (0xe0014048)))
1021 #define PWM_EMR (*(pREG32 (0xe001403c)))
1022 #define PWM_PCR (*(pREG32 (0xe001404c)))
1023 #define PWM_LER (*(pREG32 (0xe0014050)))
1024 #define PWM_CCR (*(pREG32 (0xe0014028)))
1025 #define PWM_CR0 (*(pREG32 (0xe001402c)))
1026 #define PWM_CR1 (*(pREG32 (0xe0014030)))
1027 #define PWM_CR2 (*(pREG32 (0xe0014034)))
1028 #define PWM_CR3 (*(pREG32 (0xe0014038)))
1031 /*##############################################################################
1033 ##############################################################################*/
1035 #define RTC_ILR (*(pREG32 (0xe0024000)))
1036 #define RTC_CTC (*(pREG32 (0xe0024004)))
1037 #define RTC_CCR (*(pREG32 (0xe0024008)))
1038 #define RTC_CIIR (*(pREG32 (0xe002400c)))
1039 #define RTC_AMR (*(pREG32 (0xe0024010)))
1040 #define RTC_CTIME0 (*(pREG32 (0xe0024014)))
1041 #define RTC_CTIME1 (*(pREG32 (0xe0024018)))
1042 #define RTC_CTIME2 (*(pREG32 (0xe002401c)))
1044 #define RTC_SEC (*(pREG32 (0xe0024020)))
1045 #define RTC_MIN (*(pREG32 (0xe0024024)))
1046 #define RTC_HOUR (*(pREG32 (0xe0024028)))
1047 #define RTC_DOM (*(pREG32 (0xe002402c)))
1048 #define RTC_DOW (*(pREG32 (0xe0024030)))
1049 #define RTC_DOY (*(pREG32 (0xe0024034)))
1050 #define RTC_MONTH (*(pREG32 (0xe0024038)))
1051 #define RTC_YEAR (*(pREG32 (0xe002403c)))
1053 #define RTC_ALSEC (*(pREG32 (0xe0024060)))
1054 #define RTC_ALMIN (*(pREG32 (0xe0024064)))
1055 #define RTC_ALHOUR (*(pREG32 (0xe0024068)))
1056 #define RTC_ALDOM (*(pREG32 (0xe002406c)))
1057 #define RTC_ALDOW (*(pREG32 (0xe0024070)))
1058 #define RTC_ALDOY (*(pREG32 (0xe0024074)))
1059 #define RTC_ALMON (*(pREG32 (0xe0024078)))
1060 #define RTC_ALYEAR (*(pREG32 (0xe002407c)))
1062 #define RTC_PREINT (*(pREG32 (0xe0024080)))
1063 #define RTC_PREFRAC (*(pREG32 (0xe0024084)))
1065 #define RTC_ILR_RTCCIF (0x00000001)
1066 #define RTC_ILR_RTCALF (0x00000002)
1067 #define RTC_ILR_MASK (0x00000003)
1069 #define RTC_CCR_CLKEN (0x00000001)
1070 #define RTC_CCR_CTCRST (0x00000002)
1071 #define RTC_CCR_TEST (0x0000000c)
1072 #define RTC_CCR_CLKSRC (0x00000010)
1074 #define RTC_CIIR_IMSEC (0x00000001)
1075 #define RTC_CIIR_IMMIN (0x00000002)
1076 #define RTC_CIIR_IMHOUR (0x00000004)
1077 #define RTC_CIIR_IMDOM (0x00000008)
1078 #define RTC_CIIR_IMDOW (0x00000010)
1079 #define RTC_CIIR_IMDOY (0x00000020)
1080 #define RTC_CIIR_IMMON (0x00000040)
1081 #define RTC_CIIR_IMYEAR (0x00000080)
1082 #define RTC_CIIR_IMMASK (0x000000ff)
1084 #define RTC_AMR_AMRSEC (0x00000001)
1085 #define RTC_AMR_AMRMIN (0x00000002)
1086 #define RTC_AMR_AMRHOUR (0x00000004)
1087 #define RTC_AMR_AMRDOM (0x00000008)
1088 #define RTC_AMR_AMRDOW (0x00000010)
1089 #define RTC_AMR_AMRDOY (0x00000020)
1090 #define RTC_AMR_AMRMON (0x00000040)
1091 #define RTC_AMR_AMRYEAR (0x00000080)
1092 #define RTC_AMR_AMRMASK (0x000000ff)
1094 typedef struct __attribute__ ((packed))
1100 unsigned int counter : 14;
1101 unsigned int rsvd15_31 : 18;
1109 typedef struct __attribute__ ((packed))
1115 unsigned int seconds : 6;
1116 unsigned int rsvd7_6 : 2;
1117 unsigned int minutes : 6;
1118 unsigned int rsvd14_15 : 2;
1119 unsigned int hours : 5;
1120 unsigned int rsvd21_23 : 3;
1121 unsigned int dow : 3;
1122 unsigned int rsvd27_31 : 5;
1130 typedef struct __attribute__ ((packed))
1136 unsigned int dom : 5;
1137 unsigned int rsvd5_7 : 3;
1138 unsigned int month : 4;
1139 unsigned int rsvd12_15 : 4;
1140 unsigned int year : 12;
1141 unsigned int rsvd28_31 : 4;
1149 typedef struct __attribute__ ((packed))
1155 unsigned int doy : 12;
1156 unsigned int rsvd12_31 : 20;
1165 /*##############################################################################
1167 ##############################################################################*/
1169 #define WD_MOD (*(pREG32 (0xe0000000)))
1170 #define WD_TC (*(pREG32 (0xe0000004)))
1171 #define WD_FEED (*(pREG32 (0xe0000008)))
1172 #define WD_TV (*(pREG32 (0xe000000c)))
1174 #define WD_MOD_WDEN (0x00000001)
1175 #define WD_MOD_RESET (0x00000002)
1176 #define WD_MOD_TOF (0x00000004)
1177 #define WD_MOD_INT (0x00000008)
1178 #define WD_MOD_MASK (0x0000000f)
1180 #define WD_FEED_FEED1 (0x000000aa)
1181 #define WD_FEED_FEED2 (0x00000055)
1184 /*##############################################################################
1185 ## System Control Block
1186 ##############################################################################*/
1188 #define SCB_MEMMAP (*(pREG32 (0xe01fc040)))
1189 #define SCB_PLLCON (*(pREG32 (0xe01fc080)))
1190 #define SCB_PLLCFG (*(pREG32 (0xe01fc084)))
1191 #define SCB_PLLSTAT (*(pREG32 (0xe01fc088)))
1192 #define SCB_PLLFEED (*(pREG32 (0xe01fc08c)))
1193 #define SCB_PCON (*(pREG32 (0xe01fc0c0)))
1194 #define SCB_PCONP (*(pREG32 (0xe01fc0c4)))
1195 #define SCB_VPBDIV (*(pREG32 (0xe01fc100)))
1196 #define SCB_EXTINT (*(pREG32 (0xe01fc140)))
1197 #define SCB_INTWAKE (*(pREG32 (0xe01fc144)))
1198 #define SCB_EXTMODE (*(pREG32 (0xe01fc148)))
1199 #define SCB_EXTPOLAR (*(pREG32 (0xe01fc14c)))
1200 #define SCB_RSIR (*(pREG32 (0xe01fc180)))
1201 #define SCB_CSPR (*(pREG32 (0xe01fc184)))
1202 #define SCB_SCS (*(pREG32 (0xe01fc1a0)))
1204 #define SCB_MEMMAP_BLM (0x00000000)
1205 #define SCB_MEMMAP_UFL (0x00000001)
1206 #define SCB_MEMMAP_URM (0x00000002)
1207 #define SCB_MEMMAP_RSVD (0x00000003)
1208 #define SCB_MEMMAP_MASK (0x00000003)
1210 #define SCB_PLLCON_PLLE (0x00000001)
1211 #define SCB_PLLCON_PLLC (0x00000002)
1212 #define SCB_PLLCON_MASK (0x00000003)
1214 #define SCB_PLLCFG_MSEL (0x0000001f)
1215 #define SCB_PLLCFG_PSEL (0x00000060)
1216 #define SCB_PLLCFG_MUL1 (0x00000000)
1217 #define SCB_PLLCFG_MUL2 (0x00000001)
1218 #define SCB_PLLCFG_MUL3 (0x00000002)
1219 #define SCB_PLLCFG_MUL4 (0x00000003)
1220 #define SCB_PLLCFG_MUL5 (0x00000004)
1221 #define SCB_PLLCFG_MUL6 (0x00000005)
1222 #define SCB_PLLCFG_MUL7 (0x00000006)
1223 #define SCB_PLLCFG_MUL8 (0x00000007)
1224 #define SCB_PLLCFG_MUL9 (0x00000008)
1225 #define SCB_PLLCFG_MUL10 (0x00000009)
1226 #define SCB_PLLCFG_MUL11 (0x0000000a)
1227 #define SCB_PLLCFG_MUL12 (0x0000000b)
1228 #define SCB_PLLCFG_MUL13 (0x0000000c)
1229 #define SCB_PLLCFG_MUL14 (0x0000000d)
1230 #define SCB_PLLCFG_MUL15 (0x0000000e)
1231 #define SCB_PLLCFG_MUL16 (0x0000000f)
1232 #define SCB_PLLCFG_MUL17 (0x00000010)
1233 #define SCB_PLLCFG_MUL18 (0x00000011)
1234 #define SCB_PLLCFG_MUL19 (0x00000012)
1235 #define SCB_PLLCFG_MUL20 (0x00000013)
1236 #define SCB_PLLCFG_MUL21 (0x00000014)
1237 #define SCB_PLLCFG_MUL22 (0x00000015)
1238 #define SCB_PLLCFG_MUL23 (0x00000016)
1239 #define SCB_PLLCFG_MUL24 (0x00000017)
1240 #define SCB_PLLCFG_MUL25 (0x00000018)
1241 #define SCB_PLLCFG_MUL26 (0x00000019)
1242 #define SCB_PLLCFG_MUL27 (0x0000001a)
1243 #define SCB_PLLCFG_MUL28 (0x0000001b)
1244 #define SCB_PLLCFG_MUL29 (0x0000001c)
1245 #define SCB_PLLCFG_MUL30 (0x0000001d)
1246 #define SCB_PLLCFG_MUL31 (0x0000001e)
1247 #define SCB_PLLCFG_MUL32 (0x0000001f)
1248 #define SCB_PLLCFG_DIV1 (0x00000000)
1249 #define SCB_PLLCFG_DIV2 (0x00000020)
1250 #define SCB_PLLCFG_DIV4 (0x00000040)
1251 #define SCB_PLLCFG_DIV8 (0x00000060)
1252 #define SCB_PLLCFG_MASK (0x0000007f)
1254 #define SCB_PLLSTAT_MSEL (0x0000001f)
1255 #define SCB_PLLSTAT_PSEL (0x00000060)
1256 #define SCB_PLLSTAT_PLLE (0x00000100)
1257 #define SCB_PLLSTAT_PLLC (0x00000200)
1258 #define SCB_PLLSTAT_PLOCK (0x00000400)
1260 #define SCB_PLLFEED_FEED1 (0x000000aa)
1261 #define SCB_PLLFEED_FEED2 (0x00000055)
1263 #define SCB_PCON_IDL (0x00000001)
1264 #define SCB_PCON_PD (0x00000002)
1265 #define SCB_PCON_PDBOD (0x00000004)
1266 #define SCB_PCON_BODPDM (0x00000008)
1267 #define SCB_PCON_BOGD (0x00000010)
1268 #define SCB_PCON_BORD (0x00000020)
1269 #define SCB_PCON_MASK (0x0000003f)
1271 #define SCB_PCONP_PCTIM0 (0x00000002)
1272 #define SCB_PCONP_PCTIM1 (0x00000004)
1273 #define SCB_PCONP_PCUART0 (0x00000008)
1274 #define SCB_PCONP_PCUART1 (0x00000010)
1275 #define SCB_PCONP_PCPWM0 (0x00000020)
1276 #define SCB_PCONP_PCI2C0 (0x00000080)
1277 #define SCB_PCONP_PCSPI0 (0x00000100)
1278 #define SCB_PCONP_PCRTC (0x00000200)
1279 #define SCB_PCONP_PCSPI1 (0x00000400)
1280 #define SCB_PCONP_PCAD0 (0x00001000)
1281 #define SCB_PCONP_PCI2C1 (0x00080000)
1282 #define SCB_PCONP_PCAD1 (0x00100000)
1283 #define SCB_PCONP_PUSB (0x80000000)
1284 #define SCB_PCONP_MASK (0x801817be)
1286 #define SCB_VPBDIV_25 (0x00000000)
1287 #define SCB_VPBDIV_100 (0x00000001)
1288 #define SCB_VPBDIV_50 (0x00000002)
1289 #define SCB_VPBDIV_RSVD (0x00000003)
1290 #define SCB_VPBDIV_MASK (0x00000003)
1292 #define SCB_EXTINT_EINT0 (0x00000001)
1293 #define SCB_EXTINT_EINT1 (0x00000002)
1294 #define SCB_EXTINT_EINT2 (0x00000004)
1295 #define SCB_EXTINT_EINT3 (0x00000008)
1296 #define SCB_EXTINT_MASK (0x0000000f)
1298 #define SCB_INTWAKE_EINT0 (0x00000001)
1299 #define SCB_INTWAKE_EINT1 (0x00000002)
1300 #define SCB_INTWAKE_EINT2 (0x00000004)
1301 #define SCB_INTWAKE_EINT3 (0x00000008)
1302 #define SCB_INTWAKE_USB (0x00000020)
1303 #define SCB_INTWAKE_BOD (0x00004000)
1304 #define SCB_INTWAKE_RTC (0x00008000)
1305 #define SCB_INTWAKE_MASK (0x0000c02f)
1307 #define SCB_EXTMODE_EINT0 (0x00000001)
1308 #define SCB_EXTMODE_EINT1 (0x00000002)
1309 #define SCB_EXTMODE_EINT2 (0x00000004)
1310 #define SCB_EXTMODE_EINT3 (0x00000008)
1311 #define SCB_EXTMODE_MASK (0x0000000f)
1313 #define SCB_EXTPOLAR_EINT0 (0x00000001)
1314 #define SCB_EXTPOLAR_EINT1 (0x00000002)
1315 #define SCB_EXTPOLAR_EINT2 (0x00000004)
1316 #define SCB_EXTPOLAR_EINT3 (0x00000008)
1317 #define SCB_EXTPOLAR_MASK (0x0000000f)
1319 #define SCB_RSIR_POR (0x00000001)
1320 #define SCB_RSIR_EXTR (0x00000002)
1321 #define SCB_RSIR_WDTR (0x00000004)
1322 #define SCB_RSIR_BODR (0x00000008)
1323 #define SCB_RSIR_MASK (0x0000000f)
1325 #define SCB_SCS_GPIO0M (0x00000001)
1326 #define SCB_SCS_GPIO1M (0x00000002)
1327 #define SCB_SCS_MASK (0x00000003)
1330 /*##############################################################################
1331 ## System Control Block (USB)
1332 ##############################################################################*/
1334 #define USB_PLLCON (*(pREG32 (0xe01fc0a0)))
1335 #define USB_PLLCFG (*(pREG32 (0xe01fc0a4)))
1336 #define USB_PLLSTAT (*(pREG32 (0xe01fc0a8)))
1337 #define USB_PLLFEED (*(pREG32 (0xe01fc0ac)))
1339 #define USB_IntSt (*(pREG32 (0xe01fc1c0)))
1341 #define USB_DevIntSt (*(pREG32 (0xe0090000)))
1342 #define USB_DevIntEn (*(pREG32 (0xe0090004)))
1343 #define USB_DevIntClr (*(pREG32 (0xe0090008)))
1344 #define USB_DevIntSet (*(pREG32 (0xe009000c)))
1345 #define USB_DevIntPri (*(pREG32 (0xe009002c)))
1347 #define USB_EpIntSt (*(pREG32 (0xe0090030)))
1348 #define USB_EpIntEn (*(pREG32 (0xe0090034)))
1349 #define USB_EpIntClr (*(pREG32 (0xe0090038)))
1350 #define USB_EpIntSet (*(pREG32 (0xe009003c)))
1351 #define USB_EpIntPri (*(pREG32 (0xe0090040)))
1353 #define USB_ReEP (*(pREG32 (0xe0090044)))
1354 #define USB_EpInd (*(pREG32 (0xe0090048)))
1355 #define USB_MaxPSize (*(pREG32 (0xe009004c)))
1357 #define USB_RxData (*(pREG32 (0xe0090018)))
1358 #define USB_RxPLen (*(pREG32 (0xe0090020)))
1359 #define USB_TxData (*(pREG32 (0xe009001c)))
1360 #define USB_TxPLen (*(pREG32 (0xe0090024)))
1361 #define USB_Ctrl (*(pREG32 (0xe0090028)))
1363 #define USB_CmdCode (*(pREG32 (0xe0090010)))
1364 #define USB_CmdData (*(pREG32 (0xe0090014)))
1366 #define USB_DMARSt (*(pREG32 (0xe0090050)))
1367 #define USB_DMARClr (*(pREG32 (0xe0090054)))
1368 #define USB_DMARSet (*(pREG32 (0xe0090058)))
1369 #define USB_UDCAH (*(pREG32 (0xe0090080)))
1370 #define USB_EpDMASt (*(pREG32 (0xe0090084)))
1371 #define USB_EpDMAEn (*(pREG32 (0xe0090088)))
1372 #define USB_EpDMADis (*(pREG32 (0xe009008c)))
1373 #define USB_DMAIntSt (*(pREG32 (0xe0090090)))
1374 #define USB_DMAIntEn (*(pREG32 (0xe0090094)))
1375 #define USB_EoTIntSt (*(pREG32 (0xe00900a0)))
1376 #define USB_EoTIntClr (*(pREG32 (0xe00900a4)))
1377 #define USB_EoTIntSet (*(pREG32 (0xe00900a8)))
1378 #define USB_NDDRIntSt (*(pREG32 (0xe00900ac)))
1379 #define USB_NDDRIntClr (*(pREG32 (0xe00900b0)))
1380 #define USB_NDDRIntSet (*(pREG32 (0xe00900b4)))
1381 #define USB_SysErrIntSt (*(pREG32 (0xe00900b8)))
1382 #define USB_SysErrIntClr (*(pREG32 (0xe00900bc)))
1383 #define USB_SysErrIntSet (*(pREG32 (0xe00900c0)))
1385 #define USB_PLLCON_PLLE (0x00000001)
1386 #define USB_PLLCON_PLLC (0x00000002)
1387 #define USB_PLLCON_MASK (0x00000003)
1389 #define USB_PLLCFG_MSEL (0x0000001f)
1390 #define USB_PLLCFG_PSEL (0x00000060)
1391 #define USB_PLLCFG_MUL1 (0x00000000)
1392 #define USB_PLLCFG_MUL2 (0x00000001)
1393 #define USB_PLLCFG_MUL3 (0x00000002)
1394 #define USB_PLLCFG_MUL4 (0x00000003)
1395 #define USB_PLLCFG_MUL5 (0x00000004)
1396 #define USB_PLLCFG_MUL6 (0x00000005)
1397 #define USB_PLLCFG_MUL7 (0x00000006)
1398 #define USB_PLLCFG_MUL8 (0x00000007)
1399 #define USB_PLLCFG_MUL9 (0x00000008)
1400 #define USB_PLLCFG_MUL10 (0x00000009)
1401 #define USB_PLLCFG_MUL11 (0x0000000a)
1402 #define USB_PLLCFG_MUL12 (0x0000000b)
1403 #define USB_PLLCFG_MUL13 (0x0000000c)
1404 #define USB_PLLCFG_MUL14 (0x0000000d)
1405 #define USB_PLLCFG_MUL15 (0x0000000e)
1406 #define USB_PLLCFG_MUL16 (0x0000000f)
1407 #define USB_PLLCFG_MUL17 (0x00000010)
1408 #define USB_PLLCFG_MUL18 (0x00000011)
1409 #define USB_PLLCFG_MUL19 (0x00000012)
1410 #define USB_PLLCFG_MUL20 (0x00000013)
1411 #define USB_PLLCFG_MUL21 (0x00000014)
1412 #define USB_PLLCFG_MUL22 (0x00000015)
1413 #define USB_PLLCFG_MUL23 (0x00000016)
1414 #define USB_PLLCFG_MUL24 (0x00000017)
1415 #define USB_PLLCFG_MUL25 (0x00000018)
1416 #define USB_PLLCFG_MUL26 (0x00000019)
1417 #define USB_PLLCFG_MUL27 (0x0000001a)
1418 #define USB_PLLCFG_MUL28 (0x0000001b)
1419 #define USB_PLLCFG_MUL29 (0x0000001c)
1420 #define USB_PLLCFG_MUL30 (0x0000001d)
1421 #define USB_PLLCFG_MUL31 (0x0000001e)
1422 #define USB_PLLCFG_MUL32 (0x0000001f)
1423 #define USB_PLLCFG_DIV1 (0x00000000)
1424 #define USB_PLLCFG_DIV2 (0x00000020)
1425 #define USB_PLLCFG_DIV4 (0x00000040)
1426 #define USB_PLLCFG_DIV8 (0x00000060)
1427 #define USB_PLLCFG_MASK (0x0000007f)
1429 #define USB_PLLSTAT_MSEL (0x0000001f)
1430 #define USB_PLLSTAT_PSEL (0x00000060)
1431 #define USB_PLLSTAT_PLLE (0x00000100)
1432 #define USB_PLLSTAT_PLLC (0x00000200)
1433 #define USB_PLLSTAT_PLOCK (0x00000400)
1435 #define USB_PLLFEED_FEED1 (0x000000aa)
1436 #define USB_PLLFEED_FEED2 (0x00000055)
1438 #define USB_IntSt_REQLP (0x00000001)
1439 #define USB_IntSt_REQHP (0x00000002)
1440 #define USB_IntSt_REQDMA (0x00000004)
1441 #define USB_IntSt_NeedClock (0x00000100)
1442 #define USB_IntSt_EnUSBInts (0x80000000)
1443 #define USB_IntSt_MASK (0x80000107)
1445 #define USB_DevIntSt_FRAME (0x00000001)
1446 #define USB_DevIntSt_EPFAST (0x00000002)
1447 #define USB_DevIntSt_EPSLOW (0x00000004)
1448 #define USB_DevIntSt_DEVSTAT (0x00000008)
1449 #define USB_DevIntSt_CCEMTY (0x00000010)
1450 #define USB_DevIntSt_CDFULL (0x00000020)
1451 #define USB_DevIntSt_RxENDPKT (0x00000040)
1452 #define USB_DevIntSt_TxENDPKT (0x00000080)
1453 #define USB_DevIntSt_EPRLZED (0x00000100)
1454 #define USB_DevIntSt_EPRINT (0x00000200)
1455 #define USB_DevIntSt_MASK (0x000003ff)
1457 #define USB_DevIntEn_NONE (0x00000000)
1458 #define USB_DevIntEn_FRAME (0x00000001)
1459 #define USB_DevIntEn_EPFAST (0x00000002)
1460 #define USB_DevIntEn_EPSLOW (0x00000004)
1461 #define USB_DevIntEn_DEVSTAT (0x00000008)
1462 #define USB_DevIntEn_CCEMTY (0x00000010)
1463 #define USB_DevIntEn_CDFULL (0x00000020)
1464 #define USB_DevIntEn_RxENDPKT (0x00000040)
1465 #define USB_DevIntEn_TxENDPKT (0x00000080)
1466 #define USB_DevIntEn_EPRLZED (0x00000100)
1467 #define USB_DevIntEn_EPRINT (0x00000200)
1468 #define USB_DevIntEn_MASK (0x000003ff)
1470 #define USB_DevIntClr_FRAME (0x00000001)
1471 #define USB_DevIntClr_EPFAST (0x00000002)
1472 #define USB_DevIntClr_EPSLOW (0x00000004)
1473 #define USB_DevIntClr_DEVSTAT (0x00000008)
1474 #define USB_DevIntClr_CCEMTY (0x00000010)
1475 #define USB_DevIntClr_CDFULL (0x00000020)
1476 #define USB_DevIntClr_RxENDPKT (0x00000040)
1477 #define USB_DevIntClr_TxENDPKT (0x00000080)
1478 #define USB_DevIntClr_EPRLZED (0x00000100)
1479 #define USB_DevIntClr_EPRINT (0x00000200)
1480 #define USB_DevIntClr_ALL (0x000003ff)
1481 #define USB_DevIntClr_MASK (0x000003ff)
1483 #define USB_DevIntSet_FRAME (0x00000001)
1484 #define USB_DevIntSet_EPFAST (0x00000002)
1485 #define USB_DevIntSet_EPSLOW (0x00000004)
1486 #define USB_DevIntSet_DEVSTAT (0x00000008)
1487 #define USB_DevIntSet_CCEMTY (0x00000010)
1488 #define USB_DevIntSet_CDFULL (0x00000020)
1489 #define USB_DevIntSet_RxENDPKT (0x00000040)
1490 #define USB_DevIntSet_TxENDPKT (0x00000080)
1491 #define USB_DevIntSet_EPRLZED (0x00000100)
1492 #define USB_DevIntSet_EPRINT (0x00000200)
1493 #define USB_DevIntSet_MASK (0x000003ff)
1495 #define USB_DevIntPri_FRAME (0x00000001)
1496 #define USB_DevIntPri_EPFAST (0x00000002)
1497 #define USB_DevIntPri_MASK (0x00000003)
1499 #define USB_EpIntSt_EP0RX (0x00000001)
1500 #define USB_EpIntSt_EP0TX (0x00000002)
1501 #define USB_EpIntSt_EP1RX (0x00000004)
1502 #define USB_EpIntSt_EP1TX (0x00000008)
1503 #define USB_EpIntSt_EP2RX (0x00000010)
1504 #define USB_EpIntSt_EP2TX (0x00000020)
1505 #define USB_EpIntSt_EP3RX (0x00000040)
1506 #define USB_EpIntSt_EP3TX (0x00000080)
1507 #define USB_EpIntSt_EP4RX (0x00000100)
1508 #define USB_EpIntSt_EP4TX (0x00000200)
1509 #define USB_EpIntSt_EP5RX (0x00000400)
1510 #define USB_EpIntSt_EP5TX (0x00000800)
1511 #define USB_EpIntSt_EP6RX (0x00001000)
1512 #define USB_EpIntSt_EP6TX (0x00002000)
1513 #define USB_EpIntSt_EP7RX (0x00004000)
1514 #define USB_EpIntSt_EP7TX (0x00008000)
1515 #define USB_EpIntSt_EP8RX (0x00010000)
1516 #define USB_EpIntSt_EP8TX (0x00020000)
1517 #define USB_EpIntSt_EP9RX (0x00040000)
1518 #define USB_EpIntSt_EP9TX (0x00080000)
1519 #define USB_EpIntSt_EP10RX (0x00100000)
1520 #define USB_EpIntSt_EP10TX (0x00200000)
1521 #define USB_EpIntSt_EP11RX (0x00400000)
1522 #define USB_EpIntSt_EP11TX (0x00800000)
1523 #define USB_EpIntSt_EP12RX (0x01000000)
1524 #define USB_EpIntSt_EP12TX (0x02000000)
1525 #define USB_EpIntSt_EP13RX (0x04000000)
1526 #define USB_EpIntSt_EP13TX (0x08000000)
1527 #define USB_EpIntSt_EP14RX (0x10000000)
1528 #define USB_EpIntSt_EP14TX (0x20000000)
1529 #define USB_EpIntSt_EP15RX (0x40000000)
1530 #define USB_EpIntSt_EP15TX (0x80000000)
1531 #define USB_EpIntSt_MASK (0xffffffff)
1533 #define USB_EpIntEn_NONE (0x00000000)
1534 #define USB_EpIntEn_EP0RX (0x00000001)
1535 #define USB_EpIntEn_EP0TX (0x00000002)
1536 #define USB_EpIntEn_EP1RX (0x00000004)
1537 #define USB_EpIntEn_EP1TX (0x00000008)
1538 #define USB_EpIntEn_EP2RX (0x00000010)
1539 #define USB_EpIntEn_EP2TX (0x00000020)
1540 #define USB_EpIntEn_EP3RX (0x00000040)
1541 #define USB_EpIntEn_EP3TX (0x00000080)
1542 #define USB_EpIntEn_EP4RX (0x00000100)
1543 #define USB_EpIntEn_EP4TX (0x00000200)
1544 #define USB_EpIntEn_EP5RX (0x00000400)
1545 #define USB_EpIntEn_EP5TX (0x00000800)
1546 #define USB_EpIntEn_EP6RX (0x00001000)
1547 #define USB_EpIntEn_EP6TX (0x00002000)
1548 #define USB_EpIntEn_EP7RX (0x00004000)
1549 #define USB_EpIntEn_EP7TX (0x00008000)
1550 #define USB_EpIntEn_EP8RX (0x00010000)
1551 #define USB_EpIntEn_EP8TX (0x00020000)
1552 #define USB_EpIntEn_EP9RX (0x00040000)
1553 #define USB_EpIntEn_EP9TX (0x00080000)
1554 #define USB_EpIntEn_EP10RX (0x00100000)
1555 #define USB_EpIntEn_EP10TX (0x00200000)
1556 #define USB_EpIntEn_EP11RX (0x00400000)
1557 #define USB_EpIntEn_EP11TX (0x00800000)
1558 #define USB_EpIntEn_EP12RX (0x01000000)
1559 #define USB_EpIntEn_EP12TX (0x02000000)
1560 #define USB_EpIntEn_EP13RX (0x04000000)
1561 #define USB_EpIntEn_EP13TX (0x08000000)
1562 #define USB_EpIntEn_EP14RX (0x10000000)
1563 #define USB_EpIntEn_EP14TX (0x20000000)
1564 #define USB_EpIntEn_EP15RX (0x40000000)
1565 #define USB_EpIntEn_EP15TX (0x80000000)
1566 #define USB_EpIntEn_MASK (0xffffffff)
1568 #define USB_EpIntClr_EP0RX (0x00000001)
1569 #define USB_EpIntClr_EP0TX (0x00000002)
1570 #define USB_EpIntClr_EP1RX (0x00000004)
1571 #define USB_EpIntClr_EP1TX (0x00000008)
1572 #define USB_EpIntClr_EP2RX (0x00000010)
1573 #define USB_EpIntClr_EP2TX (0x00000020)
1574 #define USB_EpIntClr_EP3RX (0x00000040)
1575 #define USB_EpIntClr_EP3TX (0x00000080)
1576 #define USB_EpIntClr_EP4RX (0x00000100)
1577 #define USB_EpIntClr_EP4TX (0x00000200)
1578 #define USB_EpIntClr_EP5RX (0x00000400)
1579 #define USB_EpIntClr_EP5TX (0x00000800)
1580 #define USB_EpIntClr_EP6RX (0x00001000)
1581 #define USB_EpIntClr_EP6TX (0x00002000)
1582 #define USB_EpIntClr_EP7RX (0x00004000)
1583 #define USB_EpIntClr_EP7TX (0x00008000)
1584 #define USB_EpIntClr_EP8RX (0x00010000)
1585 #define USB_EpIntClr_EP8TX (0x00020000)
1586 #define USB_EpIntClr_EP9RX (0x00040000)
1587 #define USB_EpIntClr_EP9TX (0x00080000)
1588 #define USB_EpIntClr_EP10RX (0x00100000)
1589 #define USB_EpIntClr_EP10TX (0x00200000)
1590 #define USB_EpIntClr_EP11RX (0x00400000)
1591 #define USB_EpIntClr_EP11TX (0x00800000)
1592 #define USB_EpIntClr_EP12RX (0x01000000)
1593 #define USB_EpIntClr_EP12TX (0x02000000)
1594 #define USB_EpIntClr_EP13RX (0x04000000)
1595 #define USB_EpIntClr_EP13TX (0x08000000)
1596 #define USB_EpIntClr_EP14RX (0x10000000)
1597 #define USB_EpIntClr_EP14TX (0x20000000)
1598 #define USB_EpIntClr_EP15RX (0x40000000)
1599 #define USB_EpIntClr_EP15TX (0x80000000)
1600 #define USB_EpIntClr_ALL (0xffffffff)
1601 #define USB_EpIntClr_MASK (0xffffffff)
1603 #define USB_EpIntSet_EP0RX (0x00000001)
1604 #define USB_EpIntSet_EP0TX (0x00000002)
1605 #define USB_EpIntSet_EP1RX (0x00000004)
1606 #define USB_EpIntSet_EP1TX (0x00000008)
1607 #define USB_EpIntSet_EP2RX (0x00000010)
1608 #define USB_EpIntSet_EP2TX (0x00000020)
1609 #define USB_EpIntSet_EP3RX (0x00000040)
1610 #define USB_EpIntSet_EP3TX (0x00000080)
1611 #define USB_EpIntSet_EP4RX (0x00000100)
1612 #define USB_EpIntSet_EP4TX (0x00000200)
1613 #define USB_EpIntSet_EP5RX (0x00000400)
1614 #define USB_EpIntSet_EP5TX (0x00000800)
1615 #define USB_EpIntSet_EP6RX (0x00001000)
1616 #define USB_EpIntSet_EP6TX (0x00002000)
1617 #define USB_EpIntSet_EP7RX (0x00004000)
1618 #define USB_EpIntSet_EP7TX (0x00008000)
1619 #define USB_EpIntSet_EP8RX (0x00010000)
1620 #define USB_EpIntSet_EP8TX (0x00020000)
1621 #define USB_EpIntSet_EP9RX (0x00040000)
1622 #define USB_EpIntSet_EP9TX (0x00080000)
1623 #define USB_EpIntSet_EP10RX (0x00100000)
1624 #define USB_EpIntSet_EP10TX (0x00200000)
1625 #define USB_EpIntSet_EP11RX (0x00400000)
1626 #define USB_EpIntSet_EP11TX (0x00800000)
1627 #define USB_EpIntSet_EP12RX (0x01000000)
1628 #define USB_EpIntSet_EP12TX (0x02000000)
1629 #define USB_EpIntSet_EP13RX (0x04000000)
1630 #define USB_EpIntSet_EP13TX (0x08000000)
1631 #define USB_EpIntSet_EP14RX (0x10000000)
1632 #define USB_EpIntSet_EP14TX (0x20000000)
1633 #define USB_EpIntSet_EP15RX (0x40000000)
1634 #define USB_EpIntSet_EP15TX (0x80000000)
1635 #define USB_EpIntSet_MASK (0xffffffff)
1637 #define USB_EpIntPri_EP0RX (0x00000001)
1638 #define USB_EpIntPri_EP0TX (0x00000002)
1639 #define USB_EpIntPri_EP1RX (0x00000004)
1640 #define USB_EpIntPri_EP1TX (0x00000008)
1641 #define USB_EpIntPri_EP2RX (0x00000010)
1642 #define USB_EpIntPri_EP2TX (0x00000020)
1643 #define USB_EpIntPri_EP3RX (0x00000040)
1644 #define USB_EpIntPri_EP3TX (0x00000080)
1645 #define USB_EpIntPri_EP4RX (0x00000100)
1646 #define USB_EpIntPri_EP4TX (0x00000200)
1647 #define USB_EpIntPri_EP5RX (0x00000400)
1648 #define USB_EpIntPri_EP5TX (0x00000800)
1649 #define USB_EpIntPri_EP6RX (0x00001000)
1650 #define USB_EpIntPri_EP6TX (0x00002000)
1651 #define USB_EpIntPri_EP7RX (0x00004000)
1652 #define USB_EpIntPri_EP7TX (0x00008000)
1653 #define USB_EpIntPri_EP8RX (0x00010000)
1654 #define USB_EpIntPri_EP8TX (0x00020000)
1655 #define USB_EpIntPri_EP9RX (0x00040000)
1656 #define USB_EpIntPri_EP9TX (0x00080000)
1657 #define USB_EpIntPri_EP10RX (0x00100000)
1658 #define USB_EpIntPri_EP10TX (0x00200000)
1659 #define USB_EpIntPri_EP11RX (0x00400000)
1660 #define USB_EpIntPri_EP11TX (0x00800000)
1661 #define USB_EpIntPri_EP12RX (0x01000000)
1662 #define USB_EpIntPri_EP12TX (0x02000000)
1663 #define USB_EpIntPri_EP13RX (0x04000000)
1664 #define USB_EpIntPri_EP13TX (0x08000000)
1665 #define USB_EpIntPri_EP14RX (0x10000000)
1666 #define USB_EpIntPri_EP14TX (0x20000000)
1667 #define USB_EpIntPri_EP15RX (0x40000000)
1668 #define USB_EpIntPri_EP15TX (0x80000000)
1669 #define USB_EpIntPri_MASK (0xffffffff)
1671 #define USB_EpRE_EP0 (0x00000001)
1672 #define USB_EpRE_EP1 (0x00000002)
1673 #define USB_EpRE_EP2 (0x00000004)
1674 #define USB_EpRE_EP3 (0x00000008)
1675 #define USB_EpRE_EP4 (0x00000010)
1676 #define USB_EpRE_EP5 (0x00000020)
1677 #define USB_EpRE_EP6 (0x00000040)
1678 #define USB_EpRE_EP7 (0x00000080)
1679 #define USB_EpRE_EP8 (0x00000100)
1680 #define USB_EpRE_EP9 (0x00000200)
1681 #define USB_EpRE_EP10 (0x00000400)
1682 #define USB_EpRE_EP11 (0x00000800)
1683 #define USB_EpRE_EP12 (0x00001000)
1684 #define USB_EpRE_EP13 (0x00002000)
1685 #define USB_EpRE_EP14 (0x00004000)
1686 #define USB_EpRE_EP15 (0x00008000)
1687 #define USB_EpRE_EP16 (0x00010000)
1688 #define USB_EpRE_EP17 (0x00020000)
1689 #define USB_EpRE_EP18 (0x00040000)
1690 #define USB_EpRE_EP19 (0x00080000)
1691 #define USB_EpRE_EP20 (0x00100000)
1692 #define USB_EpRE_EP21 (0x00200000)
1693 #define USB_EpRE_EP22 (0x00400000)
1694 #define USB_EpRE_EP23 (0x00800000)
1695 #define USB_EpRE_EP24 (0x01000000)
1696 #define USB_EpRE_EP25 (0x02000000)
1697 #define USB_EpRE_EP26 (0x04000000)
1698 #define USB_EpRE_EP27 (0x08000000)
1699 #define USB_EpRE_EP28 (0x10000000)
1700 #define USB_EpRE_EP29 (0x20000000)
1701 #define USB_EpRE_EP30 (0x40000000)
1702 #define USB_EpRE_EP31 (0x80000000)
1703 #define USB_EpRE_MASK (0xffffffff)
1705 #define USB_EpIn_MASK (0x0000001f)
1707 #define USB_MaxPSize_MASK (0x000003ff)
1709 #define USB_RxPLen_PKTLENGTH (0x000003ff)
1710 #define USB_RxPLen_PKTLENGTH_MASK (0x000003ff)
1711 #define USB_RxPLen_DV (0x00000400)
1712 #define USB_RxPLen_PKTRDY (0x00000800)
1713 #define USB_RxPLen_MASK (0x00000fff)
1715 #define USB_TxPLen_PKTLENGTH (0x000003ff)
1716 #define USB_TxPLen_MASK (0x000003ff)
1718 #define USB_Ctrl_RDEN (0x00000001)
1719 #define USB_Ctrl_WREN (0x00000002)
1720 #define USB_Ctrl_LOGENDPOINT (0x0000003c)
1721 #define USB_Ctrl_MASK (0x0000003f)
1723 #define USB_CmdCode_CMDPHASE (0x0000ff00)
1724 #define USB_CmdCode_CMDCODE (0x00ff0000)
1725 #define USB_CmdCode_MASK (0x00ffff00)
1727 #define USB_CmdData_MASK (0x000000ff)
1729 #define USB_DMARSt_EP0 (0x00000001)
1730 #define USB_DMARSt_EP1 (0x00000002)
1731 #define USB_DMARSt_EP2 (0x00000004)
1732 #define USB_DMARSt_EP3 (0x00000008)
1733 #define USB_DMARSt_EP4 (0x00000010)
1734 #define USB_DMARSt_EP5 (0x00000020)
1735 #define USB_DMARSt_EP6 (0x00000040)
1736 #define USB_DMARSt_EP7 (0x00000080)
1737 #define USB_DMARSt_EP8 (0x00000100)
1738 #define USB_DMARSt_EP9 (0x00000200)
1739 #define USB_DMARSt_EP10 (0x00000400)
1740 #define USB_DMARSt_EP11 (0x00000800)
1741 #define USB_DMARSt_EP12 (0x00001000)
1742 #define USB_DMARSt_EP13 (0x00002000)
1743 #define USB_DMARSt_EP14 (0x00004000)
1744 #define USB_DMARSt_EP15 (0x00008000)
1745 #define USB_DMARSt_EP16 (0x00010000)
1746 #define USB_DMARSt_EP17 (0x00020000)
1747 #define USB_DMARSt_EP18 (0x00040000)
1748 #define USB_DMARSt_EP19 (0x00080000)
1749 #define USB_DMARSt_EP20 (0x00100000)
1750 #define USB_DMARSt_EP21 (0x00200000)
1751 #define USB_DMARSt_EP22 (0x00400000)
1752 #define USB_DMARSt_EP23 (0x00800000)
1753 #define USB_DMARSt_EP24 (0x01000000)
1754 #define USB_DMARSt_EP25 (0x02000000)
1755 #define USB_DMARSt_EP26 (0x04000000)
1756 #define USB_DMARSt_EP27 (0x08000000)
1757 #define USB_DMARSt_EP28 (0x10000000)
1758 #define USB_DMARSt_EP29 (0x20000000)
1759 #define USB_DMARSt_EP30 (0x40000000)
1760 #define USB_DMARSt_EP31 (0x80000000)
1761 #define USB_DMARSt_MASK (0xffffffff)
1763 #define USB_DMARClr_EP0 (0x00000001)
1764 #define USB_DMARClr_EP1 (0x00000002)
1765 #define USB_DMARClr_EP2 (0x00000004)
1766 #define USB_DMARClr_EP3 (0x00000008)
1767 #define USB_DMARClr_EP4 (0x00000010)
1768 #define USB_DMARClr_EP5 (0x00000020)
1769 #define USB_DMARClr_EP6 (0x00000040)
1770 #define USB_DMARClr_EP7 (0x00000080)
1771 #define USB_DMARClr_EP8 (0x00000100)
1772 #define USB_DMARClr_EP9 (0x00000200)
1773 #define USB_DMARClr_EP10 (0x00000400)
1774 #define USB_DMARClr_EP11 (0x00000800)
1775 #define USB_DMARClr_EP12 (0x00001000)
1776 #define USB_DMARClr_EP13 (0x00002000)
1777 #define USB_DMARClr_EP14 (0x00004000)
1778 #define USB_DMARClr_EP15 (0x00008000)
1779 #define USB_DMARClr_EP16 (0x00010000)
1780 #define USB_DMARClr_EP17 (0x00020000)
1781 #define USB_DMARClr_EP18 (0x00040000)
1782 #define USB_DMARClr_EP19 (0x00080000)
1783 #define USB_DMARClr_EP20 (0x00100000)
1784 #define USB_DMARClr_EP21 (0x00200000)
1785 #define USB_DMARClr_EP22 (0x00400000)
1786 #define USB_DMARClr_EP23 (0x00800000)
1787 #define USB_DMARClr_EP24 (0x01000000)
1788 #define USB_DMARClr_EP25 (0x02000000)
1789 #define USB_DMARClr_EP26 (0x04000000)
1790 #define USB_DMARClr_EP27 (0x08000000)
1791 #define USB_DMARClr_EP28 (0x10000000)
1792 #define USB_DMARClr_EP29 (0x20000000)
1793 #define USB_DMARClr_EP30 (0x40000000)
1794 #define USB_DMARClr_EP31 (0x80000000)
1795 #define USB_DMARClr_MASK (0xffffffff)
1797 #define USB_DMARSet_EP0 (0x00000001)
1798 #define USB_DMARSet_EP1 (0x00000002)
1799 #define USB_DMARSet_EP2 (0x00000004)
1800 #define USB_DMARSet_EP3 (0x00000008)
1801 #define USB_DMARSet_EP4 (0x00000010)
1802 #define USB_DMARSet_EP5 (0x00000020)
1803 #define USB_DMARSet_EP6 (0x00000040)
1804 #define USB_DMARSet_EP7 (0x00000080)
1805 #define USB_DMARSet_EP8 (0x00000100)
1806 #define USB_DMARSet_EP9 (0x00000200)
1807 #define USB_DMARSet_EP10 (0x00000400)
1808 #define USB_DMARSet_EP11 (0x00000800)
1809 #define USB_DMARSet_EP12 (0x00001000)
1810 #define USB_DMARSet_EP13 (0x00002000)
1811 #define USB_DMARSet_EP14 (0x00004000)
1812 #define USB_DMARSet_EP15 (0x00008000)
1813 #define USB_DMARSet_EP16 (0x00010000)
1814 #define USB_DMARSet_EP17 (0x00020000)
1815 #define USB_DMARSet_EP18 (0x00040000)
1816 #define USB_DMARSet_EP19 (0x00080000)
1817 #define USB_DMARSet_EP20 (0x00100000)
1818 #define USB_DMARSet_EP21 (0x00200000)
1819 #define USB_DMARSet_EP22 (0x00400000)
1820 #define USB_DMARSet_EP23 (0x00800000)
1821 #define USB_DMARSet_EP24 (0x01000000)
1822 #define USB_DMARSet_EP25 (0x02000000)
1823 #define USB_DMARSet_EP26 (0x04000000)
1824 #define USB_DMARSet_EP27 (0x08000000)
1825 #define USB_DMARSet_EP28 (0x10000000)
1826 #define USB_DMARSet_EP29 (0x20000000)
1827 #define USB_DMARSet_EP30 (0x40000000)
1828 #define USB_DMARSet_EP31 (0x80000000)
1829 #define USB_DMARSet_MASK (0xffffffff)
1831 #define USB_EpDMASt_EP0 (0x00000001)
1832 #define USB_EpDMASt_EP1 (0x00000002)
1833 #define USB_EpDMASt_EP2 (0x00000004)
1834 #define USB_EpDMASt_EP3 (0x00000008)
1835 #define USB_EpDMASt_EP4 (0x00000010)
1836 #define USB_EpDMASt_EP5 (0x00000020)
1837 #define USB_EpDMASt_EP6 (0x00000040)
1838 #define USB_EpDMASt_EP7 (0x00000080)
1839 #define USB_EpDMASt_EP8 (0x00000100)
1840 #define USB_EpDMASt_EP9 (0x00000200)
1841 #define USB_EpDMASt_EP10 (0x00000400)
1842 #define USB_EpDMASt_EP11 (0x00000800)
1843 #define USB_EpDMASt_EP12 (0x00001000)
1844 #define USB_EpDMASt_EP13 (0x00002000)
1845 #define USB_EpDMASt_EP14 (0x00004000)
1846 #define USB_EpDMASt_EP15 (0x00008000)
1847 #define USB_EpDMASt_EP16 (0x00010000)
1848 #define USB_EpDMASt_EP17 (0x00020000)
1849 #define USB_EpDMASt_EP18 (0x00040000)
1850 #define USB_EpDMASt_EP19 (0x00080000)
1851 #define USB_EpDMASt_EP20 (0x00100000)
1852 #define USB_EpDMASt_EP21 (0x00200000)
1853 #define USB_EpDMASt_EP22 (0x00400000)
1854 #define USB_EpDMASt_EP23 (0x00800000)
1855 #define USB_EpDMASt_EP24 (0x01000000)
1856 #define USB_EpDMASt_EP25 (0x02000000)
1857 #define USB_EpDMASt_EP26 (0x04000000)
1858 #define USB_EpDMASt_EP27 (0x08000000)
1859 #define USB_EpDMASt_EP28 (0x10000000)
1860 #define USB_EpDMASt_EP29 (0x20000000)
1861 #define USB_EpDMASt_EP30 (0x40000000)
1862 #define USB_EpDMASt_EP31 (0x80000000)
1863 #define USB_EpDMASt_MASK (0xffffffff)
1865 #define USB_EpDMAEn_EP0 (0x00000001)
1866 #define USB_EpDMAEn_EP1 (0x00000002)
1867 #define USB_EpDMAEn_EP2 (0x00000004)
1868 #define USB_EpDMAEn_EP3 (0x00000008)
1869 #define USB_EpDMAEn_EP4 (0x00000010)
1870 #define USB_EpDMAEn_EP5 (0x00000020)
1871 #define USB_EpDMAEn_EP6 (0x00000040)
1872 #define USB_EpDMAEn_EP7 (0x00000080)
1873 #define USB_EpDMAEn_EP8 (0x00000100)
1874 #define USB_EpDMAEn_EP9 (0x00000200)
1875 #define USB_EpDMAEn_EP10 (0x00000400)
1876 #define USB_EpDMAEn_EP11 (0x00000800)
1877 #define USB_EpDMAEn_EP12 (0x00001000)
1878 #define USB_EpDMAEn_EP13 (0x00002000)
1879 #define USB_EpDMAEn_EP14 (0x00004000)
1880 #define USB_EpDMAEn_EP15 (0x00008000)
1881 #define USB_EpDMAEn_EP16 (0x00010000)
1882 #define USB_EpDMAEn_EP17 (0x00020000)
1883 #define USB_EpDMAEn_EP18 (0x00040000)
1884 #define USB_EpDMAEn_EP19 (0x00080000)
1885 #define USB_EpDMAEn_EP20 (0x00100000)
1886 #define USB_EpDMAEn_EP21 (0x00200000)
1887 #define USB_EpDMAEn_EP22 (0x00400000)
1888 #define USB_EpDMAEn_EP23 (0x00800000)
1889 #define USB_EpDMAEn_EP24 (0x01000000)
1890 #define USB_EpDMAEn_EP25 (0x02000000)
1891 #define USB_EpDMAEn_EP26 (0x04000000)
1892 #define USB_EpDMAEn_EP27 (0x08000000)
1893 #define USB_EpDMAEn_EP28 (0x10000000)
1894 #define USB_EpDMAEn_EP29 (0x20000000)
1895 #define USB_EpDMAEn_EP30 (0x40000000)
1896 #define USB_EpDMAEn_EP31 (0x80000000)
1897 #define USB_EpDMAEn_MASK (0xffffffff)
1899 #define USB_EpDMADis_EP0 (0x00000001)
1900 #define USB_EpDMADis_EP1 (0x00000002)
1901 #define USB_EpDMADis_EP2 (0x00000004)
1902 #define USB_EpDMADis_EP3 (0x00000008)
1903 #define USB_EpDMADis_EP4 (0x00000010)
1904 #define USB_EpDMADis_EP5 (0x00000020)
1905 #define USB_EpDMADis_EP6 (0x00000040)
1906 #define USB_EpDMADis_EP7 (0x00000080)
1907 #define USB_EpDMADis_EP8 (0x00000100)
1908 #define USB_EpDMADis_EP9 (0x00000200)
1909 #define USB_EpDMADis_EP10 (0x00000400)
1910 #define USB_EpDMADis_EP11 (0x00000800)
1911 #define USB_EpDMADis_EP12 (0x00001000)
1912 #define USB_EpDMADis_EP13 (0x00002000)
1913 #define USB_EpDMADis_EP14 (0x00004000)
1914 #define USB_EpDMADis_EP15 (0x00008000)
1915 #define USB_EpDMADis_EP16 (0x00010000)
1916 #define USB_EpDMADis_EP17 (0x00020000)
1917 #define USB_EpDMADis_EP18 (0x00040000)
1918 #define USB_EpDMADis_EP19 (0x00080000)
1919 #define USB_EpDMADis_EP20 (0x00100000)
1920 #define USB_EpDMADis_EP21 (0x00200000)
1921 #define USB_EpDMADis_EP22 (0x00400000)
1922 #define USB_EpDMADis_EP23 (0x00800000)
1923 #define USB_EpDMADis_EP24 (0x01000000)
1924 #define USB_EpDMADis_EP25 (0x02000000)
1925 #define USB_EpDMADis_EP26 (0x04000000)
1926 #define USB_EpDMADis_EP27 (0x08000000)
1927 #define USB_EpDMADis_EP28 (0x10000000)
1928 #define USB_EpDMADis_EP29 (0x20000000)
1929 #define USB_EpDMADis_EP30 (0x40000000)
1930 #define USB_EpDMADis_EP31 (0x80000000)
1931 #define USB_EpDMADis_MASK (0xffffffff)
1933 #define USB_DMAInstSt_EOT (0x00000001)
1934 #define USB_DMAInstSt_NDDR (0x00000002)
1935 #define USB_DMAInstSt_SE (0x00000004)
1936 #define USB_DMAInstSt_MASK (0x00000007)
1938 #define USB_DMAInstEn_EOT (0x00000001)
1939 #define USB_DMAInstEn_NDDR (0x00000002)
1940 #define USB_DMAInstEn_SE (0x00000004)
1941 #define USB_DMAInstEn_MASK (0x00000007)
1943 #define USB_EoTIntSt_EP0 (0x00000001)
1944 #define USB_EoTIntSt_EP1 (0x00000002)
1945 #define USB_EoTIntSt_EP2 (0x00000004)
1946 #define USB_EoTIntSt_EP3 (0x00000008)
1947 #define USB_EoTIntSt_EP4 (0x00000010)
1948 #define USB_EoTIntSt_EP5 (0x00000020)
1949 #define USB_EoTIntSt_EP6 (0x00000040)
1950 #define USB_EoTIntSt_EP7 (0x00000080)
1951 #define USB_EoTIntSt_EP8 (0x00000100)
1952 #define USB_EoTIntSt_EP9 (0x00000200)
1953 #define USB_EoTIntSt_EP10 (0x00000400)
1954 #define USB_EoTIntSt_EP11 (0x00000800)
1955 #define USB_EoTIntSt_EP12 (0x00001000)
1956 #define USB_EoTIntSt_EP13 (0x00002000)
1957 #define USB_EoTIntSt_EP14 (0x00004000)
1958 #define USB_EoTIntSt_EP15 (0x00008000)
1959 #define USB_EoTIntSt_EP16 (0x00010000)
1960 #define USB_EoTIntSt_EP17 (0x00020000)
1961 #define USB_EoTIntSt_EP18 (0x00040000)
1962 #define USB_EoTIntSt_EP19 (0x00080000)
1963 #define USB_EoTIntSt_EP20 (0x00100000)
1964 #define USB_EoTIntSt_EP21 (0x00200000)
1965 #define USB_EoTIntSt_EP22 (0x00400000)
1966 #define USB_EoTIntSt_EP23 (0x00800000)
1967 #define USB_EoTIntSt_EP24 (0x01000000)
1968 #define USB_EoTIntSt_EP25 (0x02000000)
1969 #define USB_EoTIntSt_EP26 (0x04000000)
1970 #define USB_EoTIntSt_EP27 (0x08000000)
1971 #define USB_EoTIntSt_EP28 (0x10000000)
1972 #define USB_EoTIntSt_EP29 (0x20000000)
1973 #define USB_EoTIntSt_EP30 (0x40000000)
1974 #define USB_EoTIntSt_EP31 (0x80000000)
1975 #define USB_EoTIntSt_MASK (0xffffffff)
1977 #define USB_EoTIntClr_EP0 (0x00000001)
1978 #define USB_EoTIntClr_EP1 (0x00000002)
1979 #define USB_EoTIntClr_EP2 (0x00000004)
1980 #define USB_EoTIntClr_EP3 (0x00000008)
1981 #define USB_EoTIntClr_EP4 (0x00000010)
1982 #define USB_EoTIntClr_EP5 (0x00000020)
1983 #define USB_EoTIntClr_EP6 (0x00000040)
1984 #define USB_EoTIntClr_EP7 (0x00000080)
1985 #define USB_EoTIntClr_EP8 (0x00000100)
1986 #define USB_EoTIntClr_EP9 (0x00000200)
1987 #define USB_EoTIntClr_EP10 (0x00000400)
1988 #define USB_EoTIntClr_EP11 (0x00000800)
1989 #define USB_EoTIntClr_EP12 (0x00001000)
1990 #define USB_EoTIntClr_EP13 (0x00002000)
1991 #define USB_EoTIntClr_EP14 (0x00004000)
1992 #define USB_EoTIntClr_EP15 (0x00008000)
1993 #define USB_EoTIntClr_EP16 (0x00010000)
1994 #define USB_EoTIntClr_EP17 (0x00020000)
1995 #define USB_EoTIntClr_EP18 (0x00040000)
1996 #define USB_EoTIntClr_EP19 (0x00080000)
1997 #define USB_EoTIntClr_EP20 (0x00100000)
1998 #define USB_EoTIntClr_EP21 (0x00200000)
1999 #define USB_EoTIntClr_EP22 (0x00400000)
2000 #define USB_EoTIntClr_EP23 (0x00800000)
2001 #define USB_EoTIntClr_EP24 (0x01000000)
2002 #define USB_EoTIntClr_EP25 (0x02000000)
2003 #define USB_EoTIntClr_EP26 (0x04000000)
2004 #define USB_EoTIntClr_EP27 (0x08000000)
2005 #define USB_EoTIntClr_EP28 (0x10000000)
2006 #define USB_EoTIntClr_EP29 (0x20000000)
2007 #define USB_EoTIntClr_EP30 (0x40000000)
2008 #define USB_EoTIntClr_EP31 (0x80000000)
2009 #define USB_EoTIntClr_MASK (0xffffffff)
2011 #define USB_EoTIntSet_EP0 (0x00000001)
2012 #define USB_EoTIntSet_EP1 (0x00000002)
2013 #define USB_EoTIntSet_EP2 (0x00000004)
2014 #define USB_EoTIntSet_EP3 (0x00000008)
2015 #define USB_EoTIntSet_EP4 (0x00000010)
2016 #define USB_EoTIntSet_EP5 (0x00000020)
2017 #define USB_EoTIntSet_EP6 (0x00000040)
2018 #define USB_EoTIntSet_EP7 (0x00000080)
2019 #define USB_EoTIntSet_EP8 (0x00000100)
2020 #define USB_EoTIntSet_EP9 (0x00000200)
2021 #define USB_EoTIntSet_EP10 (0x00000400)
2022 #define USB_EoTIntSet_EP11 (0x00000800)
2023 #define USB_EoTIntSet_EP12 (0x00001000)
2024 #define USB_EoTIntSet_EP13 (0x00002000)
2025 #define USB_EoTIntSet_EP14 (0x00004000)
2026 #define USB_EoTIntSet_EP15 (0x00008000)
2027 #define USB_EoTIntSet_EP16 (0x00010000)
2028 #define USB_EoTIntSet_EP17 (0x00020000)
2029 #define USB_EoTIntSet_EP18 (0x00040000)
2030 #define USB_EoTIntSet_EP19 (0x00080000)
2031 #define USB_EoTIntSet_EP20 (0x00100000)
2032 #define USB_EoTIntSet_EP21 (0x00200000)
2033 #define USB_EoTIntSet_EP22 (0x00400000)
2034 #define USB_EoTIntSet_EP23 (0x00800000)
2035 #define USB_EoTIntSet_EP24 (0x01000000)
2036 #define USB_EoTIntSet_EP25 (0x02000000)
2037 #define USB_EoTIntSet_EP26 (0x04000000)
2038 #define USB_EoTIntSet_EP27 (0x08000000)
2039 #define USB_EoTIntSet_EP28 (0x10000000)
2040 #define USB_EoTIntSet_EP29 (0x20000000)
2041 #define USB_EoTIntSet_EP30 (0x40000000)
2042 #define USB_EoTIntSet_EP31 (0x80000000)
2043 #define USB_EoTIntSet_MASK (0xffffffff)
2045 #define USB_NDDRIntSt_EP0 (0x00000001)
2046 #define USB_NDDRIntSt_EP1 (0x00000002)
2047 #define USB_NDDRIntSt_EP2 (0x00000004)
2048 #define USB_NDDRIntSt_EP3 (0x00000008)
2049 #define USB_NDDRIntSt_EP4 (0x00000010)
2050 #define USB_NDDRIntSt_EP5 (0x00000020)
2051 #define USB_NDDRIntSt_EP6 (0x00000040)
2052 #define USB_NDDRIntSt_EP7 (0x00000080)
2053 #define USB_NDDRIntSt_EP8 (0x00000100)
2054 #define USB_NDDRIntSt_EP9 (0x00000200)
2055 #define USB_NDDRIntSt_EP10 (0x00000400)
2056 #define USB_NDDRIntSt_EP11 (0x00000800)
2057 #define USB_NDDRIntSt_EP12 (0x00001000)
2058 #define USB_NDDRIntSt_EP13 (0x00002000)
2059 #define USB_NDDRIntSt_EP14 (0x00004000)
2060 #define USB_NDDRIntSt_EP15 (0x00008000)
2061 #define USB_NDDRIntSt_EP16 (0x00010000)
2062 #define USB_NDDRIntSt_EP17 (0x00020000)
2063 #define USB_NDDRIntSt_EP18 (0x00040000)
2064 #define USB_NDDRIntSt_EP19 (0x00080000)
2065 #define USB_NDDRIntSt_EP20 (0x00100000)
2066 #define USB_NDDRIntSt_EP21 (0x00200000)
2067 #define USB_NDDRIntSt_EP22 (0x00400000)
2068 #define USB_NDDRIntSt_EP23 (0x00800000)
2069 #define USB_NDDRIntSt_EP24 (0x01000000)
2070 #define USB_NDDRIntSt_EP25 (0x02000000)
2071 #define USB_NDDRIntSt_EP26 (0x04000000)
2072 #define USB_NDDRIntSt_EP27 (0x08000000)
2073 #define USB_NDDRIntSt_EP28 (0x10000000)
2074 #define USB_NDDRIntSt_EP29 (0x20000000)
2075 #define USB_NDDRIntSt_EP30 (0x40000000)
2076 #define USB_NDDRIntSt_EP31 (0x80000000)
2077 #define USB_NDDRIntSt_MASK (0xffffffff)
2079 #define USB_NDDRIntClr_EP0 (0x00000001)
2080 #define USB_NDDRIntClr_EP1 (0x00000002)
2081 #define USB_NDDRIntClr_EP2 (0x00000004)
2082 #define USB_NDDRIntClr_EP3 (0x00000008)
2083 #define USB_NDDRIntClr_EP4 (0x00000010)
2084 #define USB_NDDRIntClr_EP5 (0x00000020)
2085 #define USB_NDDRIntClr_EP6 (0x00000040)
2086 #define USB_NDDRIntClr_EP7 (0x00000080)
2087 #define USB_NDDRIntClr_EP8 (0x00000100)
2088 #define USB_NDDRIntClr_EP9 (0x00000200)
2089 #define USB_NDDRIntClr_EP10 (0x00000400)
2090 #define USB_NDDRIntClr_EP11 (0x00000800)
2091 #define USB_NDDRIntClr_EP12 (0x00001000)
2092 #define USB_NDDRIntClr_EP13 (0x00002000)
2093 #define USB_NDDRIntClr_EP14 (0x00004000)
2094 #define USB_NDDRIntClr_EP15 (0x00008000)
2095 #define USB_NDDRIntClr_EP16 (0x00010000)
2096 #define USB_NDDRIntClr_EP17 (0x00020000)
2097 #define USB_NDDRIntClr_EP18 (0x00040000)
2098 #define USB_NDDRIntClr_EP19 (0x00080000)
2099 #define USB_NDDRIntClr_EP20 (0x00100000)
2100 #define USB_NDDRIntClr_EP21 (0x00200000)
2101 #define USB_NDDRIntClr_EP22 (0x00400000)
2102 #define USB_NDDRIntClr_EP23 (0x00800000)
2103 #define USB_NDDRIntClr_EP24 (0x01000000)
2104 #define USB_NDDRIntClr_EP25 (0x02000000)
2105 #define USB_NDDRIntClr_EP26 (0x04000000)
2106 #define USB_NDDRIntClr_EP27 (0x08000000)
2107 #define USB_NDDRIntClr_EP28 (0x10000000)
2108 #define USB_NDDRIntClr_EP29 (0x20000000)
2109 #define USB_NDDRIntClr_EP30 (0x40000000)
2110 #define USB_NDDRIntClr_EP31 (0x80000000)
2111 #define USB_NDDRIntClr_MASK (0xffffffff)
2113 #define USB_NDDRIntSet_EP0 (0x00000001)
2114 #define USB_NDDRIntSet_EP1 (0x00000002)
2115 #define USB_NDDRIntSet_EP2 (0x00000004)
2116 #define USB_NDDRIntSet_EP3 (0x00000008)
2117 #define USB_NDDRIntSet_EP4 (0x00000010)
2118 #define USB_NDDRIntSet_EP5 (0x00000020)
2119 #define USB_NDDRIntSet_EP6 (0x00000040)
2120 #define USB_NDDRIntSet_EP7 (0x00000080)
2121 #define USB_NDDRIntSet_EP8 (0x00000100)
2122 #define USB_NDDRIntSet_EP9 (0x00000200)
2123 #define USB_NDDRIntSet_EP10 (0x00000400)
2124 #define USB_NDDRIntSet_EP11 (0x00000800)
2125 #define USB_NDDRIntSet_EP12 (0x00001000)
2126 #define USB_NDDRIntSet_EP13 (0x00002000)
2127 #define USB_NDDRIntSet_EP14 (0x00004000)
2128 #define USB_NDDRIntSet_EP15 (0x00008000)
2129 #define USB_NDDRIntSet_EP16 (0x00010000)
2130 #define USB_NDDRIntSet_EP17 (0x00020000)
2131 #define USB_NDDRIntSet_EP18 (0x00040000)
2132 #define USB_NDDRIntSet_EP19 (0x00080000)
2133 #define USB_NDDRIntSet_EP20 (0x00100000)
2134 #define USB_NDDRIntSet_EP21 (0x00200000)
2135 #define USB_NDDRIntSet_EP22 (0x00400000)
2136 #define USB_NDDRIntSet_EP23 (0x00800000)
2137 #define USB_NDDRIntSet_EP24 (0x01000000)
2138 #define USB_NDDRIntSet_EP25 (0x02000000)
2139 #define USB_NDDRIntSet_EP26 (0x04000000)
2140 #define USB_NDDRIntSet_EP27 (0x08000000)
2141 #define USB_NDDRIntSet_EP28 (0x10000000)
2142 #define USB_NDDRIntSet_EP29 (0x20000000)
2143 #define USB_NDDRIntSet_EP30 (0x40000000)
2144 #define USB_NDDRIntSet_EP31 (0x80000000)
2145 #define USB_NDDRIntSet_MASK (0xffffffff)
2147 #define USB_SysErrIntSt_EP0 (0x00000001)
2148 #define USB_SysErrIntSt_EP1 (0x00000002)
2149 #define USB_SysErrIntSt_EP2 (0x00000004)
2150 #define USB_SysErrIntSt_EP3 (0x00000008)
2151 #define USB_SysErrIntSt_EP4 (0x00000010)
2152 #define USB_SysErrIntSt_EP5 (0x00000020)
2153 #define USB_SysErrIntSt_EP6 (0x00000040)
2154 #define USB_SysErrIntSt_EP7 (0x00000080)
2155 #define USB_SysErrIntSt_EP8 (0x00000100)
2156 #define USB_SysErrIntSt_EP9 (0x00000200)
2157 #define USB_SysErrIntSt_EP10 (0x00000400)
2158 #define USB_SysErrIntSt_EP11 (0x00000800)
2159 #define USB_SysErrIntSt_EP12 (0x00001000)
2160 #define USB_SysErrIntSt_EP13 (0x00002000)
2161 #define USB_SysErrIntSt_EP14 (0x00004000)
2162 #define USB_SysErrIntSt_EP15 (0x00008000)
2163 #define USB_SysErrIntSt_EP16 (0x00010000)
2164 #define USB_SysErrIntSt_EP17 (0x00020000)
2165 #define USB_SysErrIntSt_EP18 (0x00040000)
2166 #define USB_SysErrIntSt_EP19 (0x00080000)
2167 #define USB_SysErrIntSt_EP20 (0x00100000)
2168 #define USB_SysErrIntSt_EP21 (0x00200000)
2169 #define USB_SysErrIntSt_EP22 (0x00400000)
2170 #define USB_SysErrIntSt_EP23 (0x00800000)
2171 #define USB_SysErrIntSt_EP24 (0x01000000)
2172 #define USB_SysErrIntSt_EP25 (0x02000000)
2173 #define USB_SysErrIntSt_EP26 (0x04000000)
2174 #define USB_SysErrIntSt_EP27 (0x08000000)
2175 #define USB_SysErrIntSt_EP28 (0x10000000)
2176 #define USB_SysErrIntSt_EP29 (0x20000000)
2177 #define USB_SysErrIntSt_EP30 (0x40000000)
2178 #define USB_SysErrIntSt_EP31 (0x80000000)
2179 #define USB_SysErrIntSt_MASK (0xffffffff)
2181 #define USB_SysErrIntClr_EP0 (0x00000001)
2182 #define USB_SysErrIntClr_EP1 (0x00000002)
2183 #define USB_SysErrIntClr_EP2 (0x00000004)
2184 #define USB_SysErrIntClr_EP3 (0x00000008)
2185 #define USB_SysErrIntClr_EP4 (0x00000010)
2186 #define USB_SysErrIntClr_EP5 (0x00000020)
2187 #define USB_SysErrIntClr_EP6 (0x00000040)
2188 #define USB_SysErrIntClr_EP7 (0x00000080)
2189 #define USB_SysErrIntClr_EP8 (0x00000100)
2190 #define USB_SysErrIntClr_EP9 (0x00000200)
2191 #define USB_SysErrIntClr_EP10 (0x00000400)
2192 #define USB_SysErrIntClr_EP11 (0x00000800)
2193 #define USB_SysErrIntClr_EP12 (0x00001000)
2194 #define USB_SysErrIntClr_EP13 (0x00002000)
2195 #define USB_SysErrIntClr_EP14 (0x00004000)
2196 #define USB_SysErrIntClr_EP15 (0x00008000)
2197 #define USB_SysErrIntClr_EP16 (0x00010000)
2198 #define USB_SysErrIntClr_EP17 (0x00020000)
2199 #define USB_SysErrIntClr_EP18 (0x00040000)
2200 #define USB_SysErrIntClr_EP19 (0x00080000)
2201 #define USB_SysErrIntClr_EP20 (0x00100000)
2202 #define USB_SysErrIntClr_EP21 (0x00200000)
2203 #define USB_SysErrIntClr_EP22 (0x00400000)
2204 #define USB_SysErrIntClr_EP23 (0x00800000)
2205 #define USB_SysErrIntClr_EP24 (0x01000000)
2206 #define USB_SysErrIntClr_EP25 (0x02000000)
2207 #define USB_SysErrIntClr_EP26 (0x04000000)
2208 #define USB_SysErrIntClr_EP27 (0x08000000)
2209 #define USB_SysErrIntClr_EP28 (0x10000000)
2210 #define USB_SysErrIntClr_EP29 (0x20000000)
2211 #define USB_SysErrIntClr_EP30 (0x40000000)
2212 #define USB_SysErrIntClr_EP31 (0x80000000)
2213 #define USB_SysErrIntClr_MASK (0xffffffff)
2215 #define USB_SysErrIntSet_EP0 (0x00000001)
2216 #define USB_SysErrIntSet_EP1 (0x00000002)
2217 #define USB_SysErrIntSet_EP2 (0x00000004)
2218 #define USB_SysErrIntSet_EP3 (0x00000008)
2219 #define USB_SysErrIntSet_EP4 (0x00000010)
2220 #define USB_SysErrIntSet_EP5 (0x00000020)
2221 #define USB_SysErrIntSet_EP6 (0x00000040)
2222 #define USB_SysErrIntSet_EP7 (0x00000080)
2223 #define USB_SysErrIntSet_EP8 (0x00000100)
2224 #define USB_SysErrIntSet_EP9 (0x00000200)
2225 #define USB_SysErrIntSet_EP10 (0x00000400)
2226 #define USB_SysErrIntSet_EP11 (0x00000800)
2227 #define USB_SysErrIntSet_EP12 (0x00001000)
2228 #define USB_SysErrIntSet_EP13 (0x00002000)
2229 #define USB_SysErrIntSet_EP14 (0x00004000)
2230 #define USB_SysErrIntSet_EP15 (0x00008000)
2231 #define USB_SysErrIntSet_EP16 (0x00010000)
2232 #define USB_SysErrIntSet_EP17 (0x00020000)
2233 #define USB_SysErrIntSet_EP18 (0x00040000)
2234 #define USB_SysErrIntSet_EP19 (0x00080000)
2235 #define USB_SysErrIntSet_EP20 (0x00100000)
2236 #define USB_SysErrIntSet_EP21 (0x00200000)
2237 #define USB_SysErrIntSet_EP22 (0x00400000)
2238 #define USB_SysErrIntSet_EP23 (0x00800000)
2239 #define USB_SysErrIntSet_EP24 (0x01000000)
2240 #define USB_SysErrIntSet_EP25 (0x02000000)
2241 #define USB_SysErrIntSet_EP26 (0x04000000)
2242 #define USB_SysErrIntSet_EP27 (0x08000000)
2243 #define USB_SysErrIntSet_EP28 (0x10000000)
2244 #define USB_SysErrIntSet_EP29 (0x20000000)
2245 #define USB_SysErrIntSet_EP30 (0x40000000)
2246 #define USB_SysErrIntSet_EP31 (0x80000000)
2247 #define USB_SysErrIntSet_MASK (0xffffffff)
2250 /*##############################################################################
2251 ## Memory Accelerator Module (MAM)
2252 ##############################################################################*/
2254 #define MAM_CR (*(pREG32 (0xe01fc000)))
2255 #define MAM_TIM (*(pREG32 (0xe01fc004)))
2257 #define MAM_CR_DISABLE (0x000000000)
2258 #define MAM_CR_PARTIAL (0x000000001)
2259 #define MAM_CR_FULL (0x000000002)
2260 #define MAM_CR_RSVD (0x000000003)
2261 #define MAM_CR_MASK (0x000000003)
2263 #define MAM_TIM_RSVD (0x000000000)
2264 #define MAM_TIM_1 (0x000000001)
2265 #define MAM_TIM_2 (0x000000002)
2266 #define MAM_TIM_3 (0x000000003)
2267 #define MAM_TIM_4 (0x000000004)
2268 #define MAM_TIM_5 (0x000000005)
2269 #define MAM_TIM_6 (0x000000006)
2270 #define MAM_TIM_7 (0x000000007)
2271 #define MAM_TIM_MASK (0x000000007)
2274 /*##############################################################################
2276 ##############################################################################*/
2278 #define IAP_LOCATION (0x7ffffff1)
2279 #define IAP_CMD_PREPARE (50)
2280 #define IAP_CMD_COPYRAMTOFLASH (51)
2281 #define IAP_CMD_ERASE (52)
2282 #define IAP_CMD_BLANKCHECK (53)
2283 #define IAP_CMD_READPARTID (54)
2284 #define IAP_CMD_READBOOTCODEVER (55)
2285 #define IAP_CMD_COMPARE (56)
2286 #define IAP_CMD_REINVOKEISP (57)
2288 #define IAP_RESULT_CMD_SUCCESS (0)
2289 #define IAP_RESULT_INVALID_COMMAND (1)
2290 #define IAP_RESULT_SRC_ADDR_ERROR (2)
2291 #define IAP_RESULT_DST_ADDR_ERROR (3)
2292 #define IAP_RESULT_SRC_ADDR_NOT_MAPPED (4)
2293 #define IAP_RESULT_DST_ADDR_NOT_MAPPED (5)
2294 #define IAP_RESULT_COUNT_ERROR (6)
2295 #define IAP_RESULT_INVALID_SECTOR (7)
2296 #define IAP_RESULT_SECTOR_NOT_BLANK (8)
2297 #define IAP_RESULT_SECTOR_NOT_PREPARED (9)
2298 #define IAP_RESULT_COMPARE_ERROR (10)
2299 #define IAP_RESULT_BUSY (11)
2300 #define IAP_RESULT_PARAM_ERROR (12)
2301 #define IAP_RESULT_ADDR_ERROR (13)
2302 #define IAP_RESULT_ADDR_NOT_MAPPED (14)
2303 #define IAP_RESULT_CMD_LOCKED (15)
2304 #define IAP_RESULT_INVALID_CODE (16)
2305 #define IAP_RESULT_INVALID_BAUD_RATE (17)
2306 #define IAP_RESULT_ANVALID_STOP_BIT (18)
2307 #define IAP_RESULT_CRP_ENABLED (19)
2308 #define IAP_RESULT_LAST (19)
projects / fw / openalt / blob