+#if AO_FAST_TIMER == 1
+
+# define AO_FAST_TIMER_TYPE 18
+# define stm_tim stm_tim1
+# define stm_tim_isr stm_tim1_up_isr
+# define STM_ISR_TIM_POS STM_ISR_TIM1_UP_POS
+# define STM_RCC_APBENR_TIMEN STM_RCC_APB2ENR_TIM1EN
+
+#elif AO_FAST_TIMER == 2
+
+# define AO_FAST_TIMER_TYPE 234
+# define stm_tim stm_tim2
+# define stm_tim_isr stm_tim2_isr
+# define STM_ISR_TIM_POS STM_ISR_TIM2_POS
+# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM2EN
+
+#elif AO_FAST_TIMER == 3
+
+# define AO_FAST_TIMER_TYPE 234
+# define stm_tim stm_tim3
+# define stm_tim_isr stm_tim3_isr
+# define STM_ISR_TIM_POS STM_ISR_TIM3_POS
+# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM3EN
+
+#elif AO_FAST_TIMER == 4
+
+# define AO_FAST_TIMER_TYPE 234
+# define stm_tim stm_tim4
+# define stm_tim_isr stm_tim4_isr
+# define STM_ISR_TIM_POS STM_ISR_TIM4_POS
+# define STM_RCC_APBENR_TIMEN STM_RCC_APB1ENR_TIM4EN
+
+#else
+#error AO_FAST_TIMER
+#endif
+
+#if AO_FAST_TIMER_TYPE == 18
+
+#define STM_TIM_CR1(cen) ((0 << STM_TIM18_CR1_CKD) | \
+ (0 << STM_TIM18_CR1_ARPE) | \
+ (0 << STM_TIM18_CR1_CMS) | \
+ (0 << STM_TIM18_CR1_DIR) | \
+ (0 << STM_TIM18_CR1_OPM) | \
+ (1 << STM_TIM18_CR1_URS) | \
+ (0 << STM_TIM18_CR1_UDIS) | \
+ ((cen) << STM_TIM18_CR1_CEN))
+#define STM_TIM_SR_UIF STM_TIM18_SR_UIF
+#define STM_TIM_DIER_UIE STM_TIM18_DIER_UIE
+#define STM_TIM_EGR_UG STM_TIM18_EGR_UG
+#define STM_TIM_CR2_MMS STM_TIM18_CR2_MMS
+#define STM_TIM_CR2_MMS_RESET STM_TIM18_CR2_MMS_RESET
+
+#define AO_TIM_PCLK AO_PCLK2
+
+/*
+ * According to the STM clock-configuration, timers 18 run
+ * twice as fast as the APB2 clock *if* the APB2 prescaler
+ * is greater than 1.
+ */
+
+#if AO_APB2_PRESCALER > 1
+#define AO_TIM_SCALER 2
+#else
+#define AO_TIM_SCALER 1
+#endif
+
+#define STM_RCC_APB_TIM stm_rcc.apb2enr
+
+#elif AO_FAST_TIMER_TYPE == 234
+
+#define STM_TIM_CR1(cen) ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) | \
+ (0 << STM_TIM234_CR1_ARPE) | \
+ (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) | \
+ (0 << STM_TIM234_CR1_DIR) | \
+ (0 << STM_TIM234_CR1_OPM) | \
+ (0 << STM_TIM234_CR1_URS) | \
+ (0 << STM_TIM234_CR1_UDIS) | \
+ ((cen) << STM_TIM234_CR1_CEN)) \
+
+#define AO_TIM_PCLK AO_PCLK1
+
+/*
+ * According to the STM clock-configuration, timers 234 run
+ * twice as fast as the APB1 clock *if* the APB1 prescaler
+ * is greater than 1.
+ */
+
+#if AO_APB1_PRESCALER > 1
+#define AO_TIM_SCALER 2
+#else
+#define AO_TIM_SCALER 1
+#endif
+
+#define STM_TIM_SR_UIF STM_TIM234_SR_UIF
+#define STM_TIM_DIER_UIE STM_TIM234_DIER_UIE
+#define STM_TIM_EGR_UG STM_TIM234_EGR_UG
+#define STM_TIM_CR2_MMS STM_TIM234_CR2_MMS
+#define STM_TIM_CR2_MMS_RESET STM_TIM234_CR2_MMS_RESET
+
+#define STM_RCC_APB_TIM stm_rcc.apb1enr
+
+#endif
+