#define sample(id) (*out++ = (uint16_t) lpc_adc.dr[id] >> 1)
static inline void lpc_adc_start(void) {
- lpc_adc.cr = ((ao_adc_mask_seq[ao_adc_sequence] << LPC_ADC_CR_SEL) |
+ lpc_adc.cr = (((uint32_t) ao_adc_mask_seq[ao_adc_sequence] << LPC_ADC_CR_SEL) |
(AO_ADC_CLKDIV << LPC_ADC_CR_CLKDIV) |
(0 << LPC_ADC_CR_BURST) |
(LPC_ADC_CR_CLKS_11 << LPC_ADC_CR_CLKS) |
ao_adc_init(void)
{
lpc_scb.sysahbclkctrl |= (1 << LPC_SCB_SYSAHBCLKCTRL_ADC);
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_ADC_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_ADC_PD);
/* Enable interrupt when channel is complete */
lpc_adc.inten = (1 << LPC_ADC_INTEN_ADGINTEN);
#define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
#define ao_enable_port(port) (lpc_scb.sysahbclkctrl |= (1 << LPC_SCB_SYSAHBCLKCTRL_GPIO))
-#define ao_disable_port(port) (lpc_scb.sysahbclkctrl &= ~(1 << LPC_SCB_SYSAHBCLKCTRL_GPIO))
+#define ao_disable_port(port) (lpc_scb.sysahbclkctrl &= ~(1UL << LPC_SCB_SYSAHBCLKCTRL_GPIO))
#define lpc_all_bit(port,bit) (((port) << 5) | (bit))
#define ao_enable_input(port,bit,mode) do { \
ao_enable_port(port); \
lpc_set_gpio(port,bit); \
- lpc_gpio.dir[port] &= ~(1 << bit); \
+ lpc_gpio.dir[port] &= ~(1UL << bit); \
ao_gpio_set_mode(port,bit,mode); \
} while (0)
#define ao_enable_analog(port,bit,id) do { \
ao_enable_port(port); \
- lpc_gpio.dir[port] &= ~(1 << bit); \
+ lpc_gpio.dir[port] &= ~(1UL << bit); \
lpc_ioconf.analog_reg(port,bit) = ((analog_func(id) << LPC_IOCONF_FUNC) | \
(0 << LPC_IOCONF_ADMODE)); \
} while (0)
if (beep == 0) {
lpc_ct32b1.tcr = ((0 << LPC_CT32B_TCR_CEN) |
(1 << LPC_CT32B_TCR_CRST));
- lpc_scb.sysahbclkctrl &= ~(1 << LPC_SCB_SYSAHBCLKCTRL_CT32B1);
+ lpc_scb.sysahbclkctrl &= ~(1UL << LPC_SCB_SYSAHBCLKCTRL_CT32B1);
} else {
lpc_scb.sysahbclkctrl |= (1 << LPC_SCB_SYSAHBCLKCTRL_CT32B1);
pin_isr(6)
pin_isr(7)
-#define pin_id(port,pin) ((port) * 24 + (pin));
+#define pin_id(port,pin) ((uint8_t) ((port) * 24 + (pin)))
static void
_ao_exti_set_enable(uint8_t pint)
ao_exti_setup (uint8_t port, uint8_t pin, uint8_t mode, void (*callback)(void)) {
uint8_t id = pin_id(port,pin);
uint8_t pint;
- uint32_t mask;
+ uint8_t mask;
uint8_t prio;
for (pint = 0; pint < LPC_NUM_PINT; pint++)
ao_arch_block_interrupts();
mask = (1 << pint);
ao_pint_inuse |= mask;
- ao_pint_enabled &= ~mask;
+ ao_pint_enabled &= (uint8_t) ~mask;
ao_pint_map[id] = pint;
ao_exti_callback[pint] = callback;
/* Set edge triggered */
lpc_gpio_pin.isel &= ~mask;
- ao_pint_enabled &= ~mask;
+ ao_pint_enabled &= (uint8_t) ~mask;
ao_pint_mode[pint] = mode;
_ao_exti_set_enable(pint);
uint8_t mask = 1 << pint;
ao_arch_block_interrupts();
- ao_pint_enabled &= ~mask;
+ ao_pint_enabled &= (uint8_t) ~mask;
_ao_exti_set_enable(pint);
ao_arch_release_interrupts();
}
static uint32_t
ao_lpc_addr_to_sector(uint8_t *addr)
{
- uint32_t off = addr - LPC_FLASH_BASE;
+ uint32_t off = (uint32_t) (addr - LPC_FLASH_BASE);
return off >> LPC_FLASH_SECTOR_SHIFT;
}
static uint8_t
ao_lpc_addr_is_sector_aligned(uint8_t *addr)
{
- uint32_t off = addr - LPC_FLASH_BASE;
+ uint32_t off = (uint32_t) (addr - LPC_FLASH_BASE);
return (off & LPC_FLASH_SECTOR_MASK) == 0;
}
(void) lpc_usart.iir_fcr;
while (lpc_usart.lsr & (1 << LPC_USART_LSR_RDR)) {
- char c = lpc_usart.rbr_thr;
+ char c = (char) lpc_usart.rbr_thr;
if (!ao_fifo_full(ao_usart_rx_fifo))
ao_fifo_insert(ao_usart_rx_fifo, c);
wake_input = 1;
/* DL MSB */
lpc_usart.ier = (ao_usart_speeds[speed].dl >> 8) & 0xff;
- lpc_usart.fdr = ((ao_usart_speeds[speed].divaddval << LPC_USART_FDR_DIVADDVAL) |
- (ao_usart_speeds[speed].mulval << LPC_USART_FDR_MULVAL));
+ lpc_usart.fdr = (((uint32_t) ao_usart_speeds[speed].divaddval << LPC_USART_FDR_DIVADDVAL) |
+ ((uint32_t) ao_usart_speeds[speed].mulval << LPC_USART_FDR_MULVAL));
/* Turn access to divisor latches back off */
- lpc_usart.lcr &= ~(1 << LPC_USART_LCR_DLAB);
+ lpc_usart.lcr &= ~(1UL << LPC_USART_LCR_DLAB);
}
void
while ((lpc_ssp->sr & (1 << LPC_SSP_SR_RNE)) == 0) \
; \
/* receive a byte */ \
- get lpc_ssp->dr; \
+ get (uint8_t) lpc_ssp->dr; \
} \
/* Wait for the SSP to go idle (it already should be) */ \
while (lpc_ssp->sr & (1 << LPC_SSP_SR_BSY)); \
lpc_scb.ssp0clkdiv = 1;
/* Reset the device */
- lpc_scb.presetctrl &= ~(1 << LPC_SCB_PRESETCTRL_SSP0_RST_N);
+ lpc_scb.presetctrl &= ~(1UL << LPC_SCB_PRESETCTRL_SSP0_RST_N);
lpc_scb.presetctrl |= (1 << LPC_SCB_PRESETCTRL_SSP0_RST_N);
ao_spi_channel_init(0);
#endif
lpc_scb.ssp1clkdiv = 1;
/* Reset the device */
- lpc_scb.presetctrl &= ~(1 << LPC_SCB_PRESETCTRL_SSP1_RST_N);
+ lpc_scb.presetctrl &= ~(1UL << LPC_SCB_PRESETCTRL_SSP1_RST_N);
lpc_scb.presetctrl |= (1 << LPC_SCB_PRESETCTRL_SSP1_RST_N);
ao_spi_channel_init(1);
#endif /* HAS_SPI_1 */
* make sure the flash part remains happy
*/
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_BOD_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_BOD_PD);
lpc_scb.bodctrl = ((LPC_SCB_BOD_BODRSTLEV_2_63 << LPC_SCB_BOD_BODRSTLEV) |
(LPC_SCB_BOD_BODINTVAL_RESERVED << LPC_SCB_BOD_BODINTVAL) |
(1 << LPC_SCB_BOD_BODRSTENA));
/* Turn the IRC clock back on */
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_IRC_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_IRC_PD);
ao_clock_delay();
/* Switch to the IRC clock */
/* Set PLL divider values */
lpc_scb.syspllctrl = ((AO_LPC_M << LPC_SCB_SYSPLLCTRL_MSEL) |
- (p << LPC_SCB_SYSPLLCTRL_PSEL));
+ ((uint32_t) p << LPC_SCB_SYSPLLCTRL_PSEL));
/* Turn off the external crystal clock */
lpc_scb.pdruncfg |= (1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
((AO_LPC_CLKIN > 15000000) << LPC_SCB_SYSOSCCTRL_FREQRANGE));/* set range */
/* Turn on the external crystal clock */
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSOSC_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_SYSOSC_PD);
ao_clock_delay();
/* Select crystal as PLL input */
;
/* Turn on the PLL */
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_SYSPLL_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_SYSPLL_PD);
/* Wait for it to lock */
ao_usb_set_address(uint8_t address)
{
debug("ao_usb_set_address %02x\n", address);
- lpc_usb.devcmdstat = ((address << LPC_USB_DEVCMDSTAT_DEV_ADDR) |
+ lpc_usb.devcmdstat = (((uint32_t) address << LPC_USB_DEVCMDSTAT_DEV_ADDR) |
(1 << LPC_USB_DEVCMDSTAT_DEV_EN) |
(0 << LPC_USB_DEVCMDSTAT_SETUP) |
(0 << LPC_USB_DEVCMDSTAT_PLL_ON) |
static void
ao_usb_set_ep(vuint32_t *ep, uint8_t *addr, uint16_t nbytes)
{
- *ep = ((ao_usb_sram_offset(addr) << LPC_USB_EP_OFFSET) |
- (nbytes << LPC_USB_EP_NBYTES) |
+ *ep = (((uint32_t) ao_usb_sram_offset(addr) << LPC_USB_EP_OFFSET) |
+ ((uint32_t) nbytes << LPC_USB_EP_NBYTES) |
(0 << LPC_USB_EP_ENDPOINT_ISO) |
(0 << LPC_USB_EP_RATE_FEEDBACK) |
(0 << LPC_USB_EP_TOGGLE_RESET) |
(0 << LPC_USB_EP_STALL) |
(0 << LPC_USB_EP_DISABLED) |
- (1 << LPC_USB_EP_ACTIVE));
+ (1UL << LPC_USB_EP_ACTIVE));
}
static inline uint16_t
static void
ao_usb_set_ep0(void)
{
- int e;
+ uint8_t e;
/* Everything is single buffered for now */
lpc_usb.epbufcfg = 0;
if (len > ao_usb_ep0_out_len)
len = ao_usb_ep0_out_len;
- ao_usb_ep0_out_len -= len;
+ ao_usb_ep0_out_len -= (uint8_t) len;
debug_data ("Fill EP0 len %d:", len);
memcpy(ao_usb_ep0_out_data, rx_buffer, len);
ao_usb_ep0_in_max = max;
/* Don't send more than asked for */
if (ao_usb_ep0_in_len > max)
- ao_usb_ep0_in_len = max;
+ ao_usb_ep0_in_len = (uint8_t) max;
ao_usb_ep0_flush();
}
ao_usb_get_descriptor(uint16_t value, uint16_t length)
{
const uint8_t *descriptor;
- uint8_t type = value >> 8;
- uint8_t index = value;
+ uint8_t type = (uint8_t) (value >> 8);
+ uint8_t index = (uint8_t) value;
descriptor = ao_usb_descriptors;
while (descriptor[0] != 0) {
else
len = descriptor[0];
if (len > length)
- len = length;
+ len = (uint8_t) length;
ao_usb_ep0_in_set(descriptor, len);
break;
}
break;
case AO_USB_REQ_SET_ADDRESS:
debug ("set address %d\n", ao_usb_setup.value);
- ao_usb_address = ao_usb_setup.value;
+ ao_usb_address = (uint8_t) ao_usb_setup.value;
ao_usb_address_pending = 1;
break;
case AO_USB_REQ_GET_DESCRIPTOR:
ao_usb_ep0_in_queue_byte(ao_usb_configuration);
break;
case AO_USB_REQ_SET_CONFIGURATION:
- ao_usb_configuration = ao_usb_setup.value;
+ ao_usb_configuration = (uint8_t) ao_usb_setup.value;
debug ("set configuration %d\n", ao_usb_configuration);
ao_usb_set_configuration();
break;
}
/* Check for reset */
- if (intstat & (1 << LPC_USB_INT_DEV)) {
+ if (intstat & (1UL << LPC_USB_INT_DEV)) {
if (lpc_usb.devcmdstat & (1 << LPC_USB_DEVCMDSTAT_DRES_C))
{
lpc_usb.devcmdstat |= (1 << LPC_USB_DEVCMDSTAT_DRES_C);
_rx_dbg0("out_recv top");
ao_usb_out_avail = 0;
- ao_usb_rx_count = AO_USB_OUT_SIZE - ao_usb_epn_out_count(AO_USB_OUT_EP);
+ ao_usb_rx_count = (uint8_t) (AO_USB_OUT_SIZE - ao_usb_epn_out_count(AO_USB_OUT_EP));
_rx_dbg1("out_recv count", ao_usb_rx_count);
debug ("recv %d\n", ao_usb_rx_count);
while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
ao_sleep(AO_USB_OUT_SLEEP_ADDR);
ao_arch_release_interrupts();
- return c;
+ return (char) c;
}
void
(1 << LPC_SCB_PDRUNCFG_USBPLL_PD));
/* Disable USB registers and RAM */
- lpc_scb.sysahbclkctrl &= ~((1 << LPC_SCB_SYSAHBCLKCTRL_USB) |
- (1 << LPC_SCB_SYSAHBCLKCTRL_USBRAM));
+ lpc_scb.sysahbclkctrl &= ~((1UL << LPC_SCB_SYSAHBCLKCTRL_USB) |
+ (1UL << LPC_SCB_SYSAHBCLKCTRL_USBRAM));
ao_arch_release_interrupts();
}
(1 << LPC_SCB_SYSAHBCLKCTRL_USBRAM));
/* Enable USB PHY */
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_USBPAD_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_USBPAD_PD);
/* Turn on USB PLL */
- lpc_scb.pdruncfg &= ~(1 << LPC_SCB_PDRUNCFG_USBPLL_PD);
+ lpc_scb.pdruncfg &= ~(1UL << LPC_SCB_PDRUNCFG_USBPLL_PD);
lpc_scb.usbpllclksel = (LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC << LPC_SCB_SYSPLLCLKSEL_SEL);
lpc_scb.usbpllclkuen = (0 << LPC_SCB_USBPLLCLKUEN_ENA);
debug ("ao_usb_enable\n");
/* Enable interrupts */
- lpc_usb.inten = ((1 << LPC_USB_INT_EPOUT(0)) |
- (1 << LPC_USB_INT_EPIN(0)) |
- (1 << LPC_USB_INT_EPIN(AO_USB_INT_EP)) |
- (1 << LPC_USB_INT_EPOUT(AO_USB_OUT_EP)) |
- (1 << LPC_USB_INT_EPIN(AO_USB_IN_EP)) |
- (1 << LPC_USB_INT_DEV));
+ lpc_usb.inten = ((1UL << LPC_USB_INT_EPOUT(0)) |
+ (1UL << LPC_USB_INT_EPIN(0)) |
+ (1UL << LPC_USB_INT_EPIN(AO_USB_INT_EP)) |
+ (1UL << LPC_USB_INT_EPOUT(AO_USB_OUT_EP)) |
+ (1UL << LPC_USB_INT_EPIN(AO_USB_IN_EP)) |
+ (1UL << LPC_USB_INT_DEV));
ao_arch_release_interrupts();
/* PIO1_31 */
#define LPC_IOCONF_FUNC_PIO1_31 0
-#define LPC_IOCONF_FUNC_MASK 0x7
+#define LPC_IOCONF_FUNC_MASK 0x7UL
#define ao_lpc_alternate(func) (((func) << LPC_IOCONF_FUNC) | \
(LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) | \
#define LPC_IOCONF_MODE_PULL_DOWN 1
#define LPC_IOCONF_MODE_PULL_UP 2
#define LPC_IOCONF_MODE_REPEATER 3
-#define LPC_IOCONF_MODE_MASK 3
+#define LPC_IOCONF_MODE_MASK 3UL
#define LPC_IOCONF_HYS 5
#define LPC_SCB_SYSPLLCTRL_PSEL_2 1
#define LPC_SCB_SYSPLLCTRL_PSEL_4 2
#define LPC_SCB_SYSPLLCTRL_PSEL_8 3
-#define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3
+#define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3UL
#define LPC_SCB_SYSPLLSTAT_LOCK 0
#define LPC_SCB_USBPLLCTRL_PSEL_2 1
#define LPC_SCB_USBPLLCTRL_PSEL_4 2
#define LPC_SCB_USBPLLCTRL_PSEL_8 3
-#define LPC_SCB_USBPLLCTRL_PSEL_MASK 3
+#define LPC_SCB_USBPLLCTRL_PSEL_MASK 3UL
#define LPC_SCB_USBPLLSTAT_LOCK 0
#define LPC_SCB_SYSOSCCTRL_FREQRANGE_15_25 1
#define LPC_SCB_WDTOSCCTRL_DIVSEL 0
-#define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1f
+#define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1fUL
#define LPC_SCB_WDTOSCCTRL_FREQSEL 5
#define LPC_SCB_WDTOSCCTRL_FREQSEL_0_6 1
#define LPC_SCB_WDTOSCCTRL_FREQSEL_1_05 2
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_2 0x0d
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_4 0x0e
#define LPC_SCB_WDTOSCCTRL_FREQSEL_4_6 0x0f
-#define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0f
+#define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0fUL
#define LPC_SCB_SYSRSTSTAT_POR 0
#define LPC_SCB_SYSRSTSTAT_EXTRST 1
#define LPC_SCB_SYSPLLCLKSEL_SEL 0
#define LPC_SCB_SYSPLLCLKSEL_SEL_IRC 0
#define LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC 1
-#define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3
+#define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3UL
#define LPC_SCB_SYSPLLCLKUEN_ENA 0
#define LPC_SCB_USBPLLCLKSEL_SEL 0
#define LPC_SCB_USBPLLCLKSEL_SEL_IRC 0
#define LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC 1
-#define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3
+#define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3UL
#define LPC_SCB_USBPLLCLKUEN_ENA 0
#define LPC_SCB_MAINCLKSEL_SEL_PLL_INPUT 1
#define LPC_SCB_MAINCLKSEL_SEL_WATCHDOG 2
#define LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT 3
-#define LPC_SCB_MAINCLKSEL_SEL_MASK 3
+#define LPC_SCB_MAINCLKSEL_SEL_MASK 3UL
#define LPC_SCB_MAINCLKUEN_ENA 0
#define LPC_USART_IIR_INTID_CTI 6
#define LPC_USART_IIR_INTID_THRE 1
#define LPC_USART_IIR_INTID_MS 0
-#define LPC_USART_IIR_INTID_MASK 7
+#define LPC_USART_IIR_INTID_MASK 7UL
#define LPC_USART_IIR_FIFOEN 6
#define LPC_USART_IIR_ABEOINT 8
#define LPC_USART_IIR_ABTOINT 9
#define LPC_USART_LCR_WLS_6 1
#define LPC_USART_LCR_WLS_7 2
#define LPC_USART_LCR_WLS_8 3
-#define LPC_USART_LCR_WLS_MASK 3
+#define LPC_USART_LCR_WLS_MASK 3UL
#define LPC_USART_LCR_SBS 2
#define LPC_USART_LCR_SBS_1 0
#define LPC_USART_LCR_SBS_2 1
-#define LPC_USART_LCR_SBS_MASK 1
+#define LPC_USART_LCR_SBS_MASK 1UL
#define LPC_USART_LCR_PE 3
#define LPC_USART_LCR_PS 4
#define LPC_USART_LCR_PS_ODD 0
#define LPC_USART_LCR_PS_EVEN 1
#define LPC_USART_LCR_PS_ONE 2
#define LPC_USART_LCR_PS_ZERO 3
-#define LPC_USART_LCR_PS_MASK 3
+#define LPC_USART_LCR_PS_MASK 3UL
#define LPC_USART_LCR_BC 6
#define LPC_USART_LCR_DLAB 7
#define lpc_usb (*(struct lpc_usb *) 0x40080000)
#define LPC_USB_DEVCMDSTAT_DEV_ADDR 0
-#define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7f
+#define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7fUL
#define LPC_USB_DEVCMDSTAT_DEV_EN 7
#define LPC_USB_DEVCMDSTAT_SETUP 8
#define LPC_USB_DEVCMDSTAT_PLL_ON 9
#define LPC_USB_DEVCMDSTAT_VBUSDEBOUNCED 28
#define LPC_USB_INFO_FRAME_NR 0
-#define LPC_USB_INFO_FRAME_NR_MASK 0x3ff
+#define LPC_USB_INFO_FRAME_NR_MASK 0x3ffUL
#define LPC_USB_INFO_ERR_CODE 11
#define LPC_USB_INFO_ERR_CODE_NO_ERROR 0
#define LPC_USB_INFO_ERR_CODE_PID_ENCODING_ERROR 1
#define LPC_USB_INFO_ERR_CODE_BITSTUFF_ERROR 0xd
#define LPC_USB_INFO_ERR_CODE_SYNC_ERROR 0xe
#define LPC_USB_INFO_ERR_CODE_WRONG_DATA_TOGGLE 0xf
-#define LPC_USB_INFO_ERR_CODE_MASK 0xf
+#define LPC_USB_INFO_ERR_CODE_MASK 0xfUL
#define LPC_USB_EPLISTSTART_EP_LIST 0
#define LPC_USB_DATABUFSTART_DA_BUF 0
#define LPC_USB_LPM_HIRD_HW 0
-#define LPC_USB_LPM_HIRD_HW_MASK 0xf
+#define LPC_USB_LPM_HIRD_HW_MASK 0xfUL
#define LPC_USB_LPM_HIRD_SW 4
-#define LPC_USB_LPM_HIRD_SW_MASK 0xf
+#define LPC_USB_LPM_HIRD_SW_MASK 0xfUL
#define LPC_USB_LPM_DATA_PENDING 8
#define LPC_USB_EPSKIP_SKIP 0
#define LPC_USB_EP_RATE_FEEDBACK 27
#define LPC_USB_EP_ENDPOINT_ISO 26
#define LPC_USB_EP_NBYTES 16
-#define LPC_USB_EP_NBYTES_MASK 0x3ff
+#define LPC_USB_EP_NBYTES_MASK 0x3ffUL
#define LPC_USB_EP_OFFSET 0
#define LPC_ISR_PIN_INT0_POS 0
#define IRQ_PRIO_REG(irq) ((irq) >> 2)
#define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
-#define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
+#define IRQ_PRIO_MASK(irq) (0xffUL << IRQ_PRIO_BIT(irq))
static inline void
lpc_nvic_set_priority(int irq, uint8_t prio) {