altos: Packet reception tuning for cc1120 driver

This adjusts the cc1120 receive parameters to increase sensitivity at
the expense of reporting many more invalid packets to the UI.

Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/src/drivers/ao_cc1120.h b/src/drivers/ao_cc1120.h
index a1d78c01b1d80b145262ad7f04f9bae5750cb1a2..5d24c49a4be946d84d1dfede605d07e827bda57f 100644 (file)
--- a/src/drivers/ao_cc1120.h
+++ b/src/drivers/ao_cc1120.h
@@ -294,7 +294,7 @@
 #define  CC1120_SETTLING_CFG_FS_AUTOCAL_MASK           3
 #define  CC1120_SETTLING_CFG_LOCK_TIME         1
 #define  CC1120_SETTLING_CFG_LOCK_TIME_50_20           0
-#define  CC1120_SETTLING_CFG_LOCK_TIME_70_30           1
+#define  CC1120_SETTLING_CFG_LOCK_TIME_75_30           1
 #define  CC1120_SETTLING_CFG_LOCK_TIME_100_40          2
 #define  CC1120_SETTLING_CFG_LOCK_TIME_150_60          3
 #define  CC1120_SETTLING_CFG_LOCK_TIME_MASK            3

diff --git a/src/drivers/ao_cc1120_CC1120.h b/src/drivers/ao_cc1120_CC1120.h
index 399abc4db7b635c321f71f54c447b232735c5a29..21a31a89d16f6c261373b597d03d4cbd25769a61 100644 (file)
--- a/src/drivers/ao_cc1120_CC1120.h
+++ b/src/drivers/ao_cc1120_CC1120.h
@@ -31,20 +31,23 @@
         CC1120_SYNC0,                          0x91,       /* Sync Word Configuration [7:0] */\r
 \r
         CC1120_SYNC_CFG1,                                 /* Sync Word Detection Configuration */\r
-               (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_ENABLED << CC1120_SYNC_CFG1_DEM_CFG) |\r
-               (0x07 << CC1120_SYNC_CFG1_SYNC_THR),\r
+               (CC1120_SYNC_CFG1_DEM_CFG_PQT_GATING_DISABLED << CC1120_SYNC_CFG1_DEM_CFG) |\r
+               (0xc << CC1120_SYNC_CFG1_SYNC_THR),\r
         CC1120_SYNC_CFG0,\r
                (CC1120_SYNC_CFG0_SYNC_MODE_16_BITS << CC1120_SYNC_CFG0_SYNC_MODE) |\r
-               (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_2 << CC1120_SYNC_CFG0_SYNC_NUM_ERROR),\r
-        CC1120_DCFILT_CFG,                     0x1c,       /* Digital DC Removal Configuration */\r
+               (CC1120_SYNC_CFG0_SYNC_NUM_ERROR_DISABLED << CC1120_SYNC_CFG0_SYNC_NUM_ERROR),\r
+        CC1120_DCFILT_CFG,                     0x15,       /* Digital DC Removal Configuration */\r
         CC1120_PREAMBLE_CFG1,                             /* Preamble Length Configuration */\r
                (CC1120_PREAMBLE_CFG1_NUM_PREAMBLE_4_BYTES << CC1120_PREAMBLE_CFG1_NUM_PREAMBLE) |\r
                (CC1120_PREAMBLE_CFG1_PREAMBLE_WORD_AA << CC1120_PREAMBLE_CFG1_PREAMBLE_WORD),\r
         CC1120_PREAMBLE_CFG0,\r
-               (1 << CC1120_PREAMBLE_CFG0_PQT_EN) |\r
-               (0x6 << CC1120_PREAMBLE_CFG0_PQT),\r
-        CC1120_FREQ_IF_CFG,                    0x40,       /* RX Mixer Frequency Configuration */\r
-        CC1120_IQIC,                           0x46,       /* Digital Image Channel Compensation Configuration */\r
+               (0 << CC1120_PREAMBLE_CFG0_PQT_EN) |\r
+               (0xe << CC1120_PREAMBLE_CFG0_PQT),\r
+\r
+       /* Adjust PQT lower to accept fewer packets */\r
+\r
+        CC1120_FREQ_IF_CFG,                    0x3a,       /* RX Mixer Frequency Configuration */\r
+        CC1120_IQIC,                           0x00,       /* Digital Image Channel Compensation Configuration */\r
         CC1120_CHAN_BW,                        0x02,       /* Channel Filter Configuration */\r
 \r
         CC1120_MDMCFG1,                                   /* General Modem Parameter Configuration */\r
@@ -53,12 +56,12 @@
                (0 << CC1120_MDMCFG1_MANCHESTER_EN) |\r
                (0 << CC1120_MDMCFG1_INVERT_DATA_EN) |\r
                (0 << CC1120_MDMCFG1_COLLISION_DETECT_EN) |\r
-               (CC1120_MDMCFG1_DVGA_GAIN_9 << CC1120_MDMCFG1_DVGA_GAIN) |\r
+               (CC1120_MDMCFG1_DVGA_GAIN_0 << CC1120_MDMCFG1_DVGA_GAIN) |\r
                (0 << CC1120_MDMCFG1_SINGLE_ADC_EN),\r
-        CC1120_MDMCFG0,                        0x05,       /* General Modem Parameter Configuration */\r
+        CC1120_MDMCFG0,                        0x0d,       /* General Modem Parameter Configuration */\r
 \r
        /* AGC reference = 10 * log10(receive BW) - 4 = 10 * log10(100e3) - 4 = 46 */\r
-        CC1120_AGC_REF,                        46,         /* AGC Reference Level Configuration */\r
+        CC1120_AGC_REF,                        0x36,         /* AGC Reference Level Configuration */\r
 \r
        /* Carrier sense threshold - 25dB above the noise */\r
         CC1120_AGC_CS_THR,                     25,         /* Carrier Sense Threshold Configuration */\r
@@ -93,7 +96,7 @@
 \r
         CC1120_SETTLING_CFG,                              /* Frequency Synthesizer Calibration and Settling Configuration */\r
                (CC1120_SETTLING_CFG_FS_AUTOCAL_IDLE_TO_ON << CC1120_SETTLING_CFG_FS_AUTOCAL) |\r
-               (CC1120_SETTLING_CFG_LOCK_TIME_50_20 << CC1120_SETTLING_CFG_LOCK_TIME) |\r
+               (CC1120_SETTLING_CFG_LOCK_TIME_75_30 << CC1120_SETTLING_CFG_LOCK_TIME) |\r
                (CC1120_SETTLING_CFG_FSREG_TIME_60 << CC1120_SETTLING_CFG_FSREG_TIME),\r
 \r
         CC1120_FS_CFG,                                    /* Frequency Synthesizer Configuration */\r
@@ -109,7 +112,7 @@
         CC1120_PKT_CFG1,                       0x45,       /* Packet Configuration, Reg 1 */\r
         CC1120_PKT_CFG0,                       0x00,       /* Packet Configuration, Reg 0 */\r
 #endif\r
-        CC1120_RFEND_CFG1,                     0x0f,       /* RFEND Configuration, Reg 1 */\r
+        CC1120_RFEND_CFG1,                     0x0e,       /* RFEND Configuration, Reg 1 */\r
         CC1120_RFEND_CFG0,                     0x00,       /* RFEND Configuration, Reg 0 */\r
        //        CC1120_PA_CFG2,                        0x3f,       /* Power Amplifier Configuration, Reg 2 */\r
        CC1120_PA_CFG2,                        0x3f,       /* Power Amplifier Configuration, Reg 2 */\r
@@ -117,8 +120,8 @@
         CC1120_PA_CFG0,                        0x7b,       /* Power Amplifier Configuration, Reg 0 */\r
         CC1120_PKT_LEN,                        0xff,       /* Packet Length Configuration */\r
         CC1120_IF_MIX_CFG,                     0x00,       /* IF Mix Configuration */\r
-        CC1120_FREQOFF_CFG,                    0x22,       /* Frequency Offset Correction Configuration */\r
-        CC1120_TOC_CFG,                        0x0b,       /* Timing Offset Correction Configuration */\r
+        CC1120_FREQOFF_CFG,                    0x20,       /* Frequency Offset Correction Configuration */\r
+        CC1120_TOC_CFG,                        0x0a,       /* Timing Offset Correction Configuration */\r
         CC1120_MARC_SPARE,                     0x00,       /* MARC Spare */\r
         CC1120_ECG_CFG,                        0x00,       /* External Clock Frequency Configuration */\r
         CC1120_SOFT_TX_DATA_CFG,               0x00,       /* Soft TX Data Configuration */\r
@@ -167,7 +170,7 @@
         CC1120_XOSC4,                          0xa0,       /* Crystal Oscillator Configuration, Reg 4 */\r
         CC1120_XOSC3,                          0x03,       /* Crystal Oscillator Configuration, Reg 3 */\r
         CC1120_XOSC2,                          0x04,       /* Crystal Oscillator Configuration, Reg 2 */\r
-        CC1120_XOSC1,                          0x01,       /* Crystal Oscillator Configuration, Reg 1 */\r
+        CC1120_XOSC1,                          0x03,       /* Crystal Oscillator Configuration, Reg 1 */\r
         CC1120_XOSC0,                          0x00,       /* Crystal Oscillator Configuration, Reg 0 */\r
         CC1120_ANALOG_SPARE,                   0x00,       /*  */\r
         CC1120_PA_CFG3,                        0x00,       /* Power Amplifier Configuration, Reg 3 */\r
@@ -196,31 +199,10 @@
         CC1120_AGC_GAIN2,                      0xd1,       /* AGC Gain, Reg 2 */\r
         CC1120_AGC_GAIN1,                      0x00,       /* AGC Gain, Reg 1 */\r
         CC1120_AGC_GAIN0,                      0x3f,       /* AGC Gain, Reg 0 */\r
-        CC1120_SOFT_RX_DATA_OUT,               0x00,       /* Soft Decision Symbol Data */\r
-        CC1120_SOFT_TX_DATA_IN,                0x00,       /* Soft TX Data Input Register */\r
-        CC1120_ASK_SOFT_RX_DATA,               0x30,       /* AGC ASK Soft Decision Output */\r
         CC1120_RNDGEN,                         0x7f,       /* Random Number Value */\r
-        CC1120_MAGN2,                          0x00,       /* Signal Magnitude after CORDIC [16] */\r
-        CC1120_MAGN1,                          0x00,       /* Signal Magnitude after CORDIC [15:8] */\r
-        CC1120_MAGN0,                          0x00,       /* Signal Magnitude after CORDIC [7:0] */\r
-        CC1120_ANG1,                           0x00,       /* Signal Angular after CORDIC [9:8] */\r
-        CC1120_ANG0,                           0x00,       /* Signal Angular after CORDIC [7:0] */\r
-        CC1120_CHFILT_I2,                      0x08,       /* Channel Filter Data Real Part [18:16] */\r
-        CC1120_CHFILT_I1,                      0x00,       /* Channel Filter Data Real Part [15:8] */\r
-        CC1120_CHFILT_I0,                      0x00,       /* Channel Filter Data Real Part [7:0] */\r
-        CC1120_CHFILT_Q2,                      0x00,       /* Channel Filter Data Imaginary Part [18:16] */\r
-        CC1120_CHFILT_Q1,                      0x00,       /* Channel Filter Data Imaginary Part [15:8] */\r
-        CC1120_CHFILT_Q0,                      0x00,       /* Channel Filter Data Imaginary Part [7:0] */\r
-        CC1120_GPIO_STATUS,                    0x00,       /* GPIO Status */\r
         CC1120_FSCAL_CTRL,                     0x01,       /*  */\r
         CC1120_PHASE_ADJUST,                   0x00,       /*  */\r
-        CC1120_PARTNUMBER,                     0x00,       /* Part Number */\r
-        CC1120_PARTVERSION,                    0x00,       /* Part Revision */\r
         CC1120_SERIAL_STATUS,                  0x00,       /* Serial Status */\r
-        CC1120_RX_STATUS,                      0x01,       /* RX Status */\r
-        CC1120_TX_STATUS,                      0x00,       /* TX Status */\r
-        CC1120_MARC_STATUS1,                   0x00,       /* MARC Status, Reg 1 */\r
-        CC1120_MARC_STATUS0,                   0x00,       /* MARC Status, Reg 0 */\r
         CC1120_PA_IFAMP_TEST,                  0x00,       /*  */\r
         CC1120_FSRF_TEST,                      0x00,       /*  */\r
         CC1120_PRE_TEST,                       0x00,       /*  */\r