No bugs identified
Signed-off-by: Keith Packard <keithp@keithp.com>
15 files changed:
stm_spi->dr = 0xff;
while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
;
stm_spi->dr = 0xff;
while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
;
+ return (uint8_t) stm_spi->dr;
#define ao_disable_port(port) do { \
if ((port) == &stm_gpioa) \
#define ao_disable_port(port) do { \
if ((port) == &stm_gpioa) \
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOAEN); \
else if ((port) == &stm_gpiob) \
else if ((port) == &stm_gpiob) \
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOBEN); \
else if ((port) == &stm_gpioc) \
else if ((port) == &stm_gpioc) \
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOCEN); \
else if ((port) == &stm_gpiod) \
else if ((port) == &stm_gpiod) \
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIODEN); \
else if ((port) == &stm_gpioe) \
else if ((port) == &stm_gpioe) \
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOEEN); \
{
if (beep == 0) {
stm_beeper.cr1 = 0;
{
if (beep == 0) {
stm_beeper.cr1 = 0;
- stm_rcc.apb1enr &= ~(1 << RCC_BEEPER);
+ stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER);
- stm_rcc.apb1enr |= (1 << RCC_BEEPER);
+ stm_rcc.apb1enr |= (1UL << RCC_BEEPER);
stm_beeper.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
(STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) |
stm_beeper.cr2 = ((0 << STM_TIM234_CR2_TI1S) |
(STM_TIM234_CR2_MMS_RESET << STM_TIM234_CR2_MMS) |
stm_afr_set(BEEPER_PORT, BEEPER_PIN, BEEPER_AFR);
/* Leave the timer off until requested */
stm_afr_set(BEEPER_PORT, BEEPER_PIN, BEEPER_AFR);
/* Leave the timer off until requested */
- stm_rcc.apb1enr &= ~(1 << RCC_BEEPER);
+ stm_rcc.apb1enr &= ~(1UL << RCC_BEEPER);
/* Reset the chip to turn off the port and the power interface clock */
ao_gpio_set_mode(&AO_BOOT_APPLICATION_GPIO, AO_BOOT_APPLICATION_PIN, 0);
ao_disable_port(&AO_BOOT_APPLICATION_GPIO);
/* Reset the chip to turn off the port and the power interface clock */
ao_gpio_set_mode(&AO_BOOT_APPLICATION_GPIO, AO_BOOT_APPLICATION_PIN, 0);
ao_disable_port(&AO_BOOT_APPLICATION_GPIO);
- stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_PWREN);
+ stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_PWREN);
return v == AO_BOOT_APPLICATION_VALUE;
}
return v == AO_BOOT_APPLICATION_VALUE;
}
ao_dma_start(uint8_t index)
{
ao_dma_done[index] = 0;
ao_dma_start(uint8_t index)
{
ao_dma_done[index] = 0;
- stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
+ stm_dma.channel[index].ccr |= (1UL << STM_DMA_CCR_EN);
}
void
ao_dma_done_transfer(uint8_t index)
{
}
void
ao_dma_done_transfer(uint8_t index)
{
- stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
+ stm_dma.channel[index].ccr &= ~(1UL << STM_DMA_CCR_EN);
#ifndef LEAVE_DMA_ON
ao_arch_critical(
if (--ao_dma_active == 0)
#ifndef LEAVE_DMA_ON
ao_arch_critical(
if (--ao_dma_active == 0)
- stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
+ stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_DMA1EN);
);
#endif
if (ao_dma_allocated[index])
);
#endif
if (ao_dma_allocated[index])
mask = 0xff << shift;
w = (*addr & ~mask) | (d << shift);
mask = 0xff << shift;
w = (*addr & ~mask) | (d << shift);
- ao_intflash_write32(pos & ~3, w);
+ ao_intflash_write32(pos & (uint16_t)~3, w);
uint8_t
ao_eeprom_write(ao_pos_t pos32, void *v, uint16_t len)
{
uint8_t
ao_eeprom_write(ao_pos_t pos32, void *v, uint16_t len)
{
+ uint16_t pos = (uint16_t) pos32;
uint8_t *d = v;
if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total)
uint8_t *d = v;
if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total)
if ((pos & 3) == 0 && len >= 4) {
uint32_t w;
if ((pos & 3) == 0 && len >= 4) {
uint32_t w;
- w = d[0] | (d[1] << 8) | (d[2] << 16) | (d[3] << 24);
+ w = (uint32_t) d[0] | ((uint32_t) d[1] << 8) | ((uint32_t) d[2] << 16) | ((uint32_t) d[3] << 24);
ao_intflash_write32(pos, w);
pos += 4;
d += 4;
ao_intflash_write32(pos, w);
pos += 4;
d += 4;
if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total)
return 0;
while (len--)
if (pos >= ao_eeprom_total || pos + len > ao_eeprom_total)
return 0;
while (len--)
- *d++ = ao_intflash_read(pos++);
+ *d++ = ao_intflash_read((uint16_t) (pos++));
}
static void ao_exti_range_isr(uint8_t first, uint8_t last, uint16_t mask) {
}
static void ao_exti_range_isr(uint8_t first, uint8_t last, uint16_t mask) {
- uint16_t pending = (ao_last_exti = stm_exti.pr) & mask;
+ uint16_t pending = (uint16_t) (ao_last_exti = stm_exti.pr) & mask;
uint8_t pin;
static uint16_t last_mask;
static uint8_t last_pin;
uint8_t pin;
static uint16_t last_mask;
static uint8_t last_pin;
if (sr1 & (1 << STM_I2C_SR1_SB))
stm_i2c->dr = ao_i2c_addr[index];
if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
if (sr1 & (1 << STM_I2C_SR1_SB))
stm_i2c->dr = ao_i2c_addr[index];
if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
- stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
+ stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
ao_i2c_state[index] = I2C_RUNNING;
ao_wakeup(&ao_i2c_state[index]);
}
if (sr1 & (1 << STM_I2C_SR1_BTF)) {
ao_i2c_state[index] = I2C_RUNNING;
ao_wakeup(&ao_i2c_state[index]);
}
if (sr1 & (1 << STM_I2C_SR1_BTF)) {
- stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
+ stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
ao_wakeup(&ao_i2c_state[index]);
}
if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
if (ao_i2c_recv_len[index]) {
ao_wakeup(&ao_i2c_state[index]);
}
if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
if (ao_i2c_recv_len[index]) {
- *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
+ *(ao_i2c_recv_data[index]++) = (uint8_t) stm_i2c->dr;
if (!--ao_i2c_recv_len[index])
ao_wakeup(&ao_i2c_recv_len[index]);
}
if (!--ao_i2c_recv_len[index])
ao_wakeup(&ao_i2c_recv_len[index]);
}
sr1 = stm_i2c->sr1;
if (sr1 & (1 << STM_I2C_SR1_AF)) {
ao_i2c_state[index] = I2C_ERROR;
sr1 = stm_i2c->sr1;
if (sr1 & (1 << STM_I2C_SR1_AF)) {
ao_i2c_state[index] = I2C_ERROR;
- stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
+ stm_i2c->sr1 = sr1 & ~(1UL << STM_I2C_SR1_AF);
ao_wakeup(&ao_i2c_state[index]);
}
}
ao_wakeup(&ao_i2c_state[index]);
}
}
-static inline int ao_lcd_stm_seg_enabled(int seg) {
+static inline int ao_lcd_stm_seg_enabled(uint32_t seg) {
if (seg < 32)
return (AO_LCD_STM_SEG_ENABLED_0 >> seg) & 1;
else
return (AO_LCD_STM_SEG_ENABLED_1 >> (seg - 32)) & 1;
}
if (seg < 32)
return (AO_LCD_STM_SEG_ENABLED_0 >> seg) & 1;
else
return (AO_LCD_STM_SEG_ENABLED_1 >> (seg - 32)) & 1;
}
-static inline int ao_lcd_stm_com_enabled(int com) {
+static inline int ao_lcd_stm_com_enabled(uint32_t com) {
return (AO_LCD_STM_COM_ENABLED >> com) & 1;
}
return (AO_LCD_STM_COM_ENABLED >> com) & 1;
}
#ifdef AO_SEGMENT_MAP
#if AO_LCD_PER_DIGIT
#ifdef AO_SEGMENT_MAP
#if AO_LCD_PER_DIGIT
- n = digit * AO_LCD_SEGMENTS + segment;
+ n = (uint8_t) (digit * AO_LCD_SEGMENTS + segment);
com = ao_lcd_map[n].com;
seg = ao_lcd_map[n].seg;
#else
com = ao_lcd_map[n].com;
seg = ao_lcd_map[n].seg;
#else
#endif
n = (seg >> 5) & 1;
if (value)
#endif
n = (seg >> 5) & 1;
if (value)
- stm_lcd.ram[com * 2 + n] |= (1 << (seg & 0x1f));
+ stm_lcd.ram[com * 2 + n] |= (1UL << (seg & 0x1f));
- stm_lcd.ram[com * 2 + n] &= ~(1 << (seg & 0x1f));
+ stm_lcd.ram[com * 2 + n] &= ~(1UL << (seg & 0x1f));
unsigned int s, c;
uint32_t csr;
unsigned int s, c;
uint32_t csr;
- stm_rcc.ahbenr |= ((AO_LCD_STM_USES_GPIOA << STM_RCC_AHBENR_GPIOAEN) |
- (AO_LCD_STM_USES_GPIOB << STM_RCC_AHBENR_GPIOBEN) |
- (AO_LCD_STM_USES_GPIOC << STM_RCC_AHBENR_GPIOCEN) |
- (AO_LCD_STM_USES_GPIOD << STM_RCC_AHBENR_GPIODEN) |
- (AO_LCD_STM_USES_GPIOE << STM_RCC_AHBENR_GPIOEEN));
+ stm_rcc.ahbenr |= (((uint32_t) AO_LCD_STM_USES_GPIOA << STM_RCC_AHBENR_GPIOAEN) |
+ ((uint32_t) AO_LCD_STM_USES_GPIOB << STM_RCC_AHBENR_GPIOBEN) |
+ ((uint32_t) AO_LCD_STM_USES_GPIOC << STM_RCC_AHBENR_GPIOCEN) |
+ ((uint32_t) AO_LCD_STM_USES_GPIOD << STM_RCC_AHBENR_GPIODEN) |
+ ((uint32_t) AO_LCD_STM_USES_GPIOE << STM_RCC_AHBENR_GPIOEEN));
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_LCDEN);
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_LCDEN);
void
ao_led_set(AO_LED_TYPE colors)
{
void
ao_led_set(AO_LED_TYPE colors)
{
- AO_LED_TYPE on = colors & LEDS_AVAILABLE;
- AO_LED_TYPE off = ~colors & LEDS_AVAILABLE;
+ AO_LED_TYPE on = colors & (AO_LED_TYPE) LEDS_AVAILABLE;
+ AO_LED_TYPE off = (AO_LED_TYPE) (~colors & (AO_LED_TYPE) LEDS_AVAILABLE);
ao_led_off(off);
ao_led_on(on);
ao_led_off(off);
ao_led_on(on);
#ifdef LED_PORT
stm_rcc.ahbenr |= (1 << LED_PORT_ENABLE);
#ifdef LED_PORT
stm_rcc.ahbenr |= (1 << LED_PORT_ENABLE);
- LED_PORT->odr &= ~LEDS_AVAILABLE;
+ LED_PORT->odr &= ~(uint32_t) LEDS_AVAILABLE;
#else
#ifdef LED_PORT_0
stm_rcc.ahbenr |= (1 << LED_PORT_0_ENABLE);
#else
#ifdef LED_PORT_0
stm_rcc.ahbenr |= (1 << LED_PORT_0_ENABLE);
uint16_t hi, lo, second_hi;
do {
uint16_t hi, lo, second_hi;
do {
- hi = stm_tim2.cnt;
- lo = stm_tim4.cnt;
- second_hi = stm_tim2.cnt;
+ hi = (uint16_t) stm_tim2.cnt;
+ lo = (uint16_t) stm_tim4.cnt;
+ second_hi = (uint16_t) stm_tim2.cnt;
} while (hi != second_hi);
return ((uint32_t) hi << 16) | lo;
}
} while (hi != second_hi);
return ((uint32_t) hi << 16) | lo;
}
uint8_t ch;
uint16_t val;
uint8_t ch;
uint16_t val;
- ch = ao_cmd_decimal();
- val = ao_cmd_decimal();
+ ch = (uint8_t) ao_cmd_decimal();
+ val = (uint16_t) ao_cmd_decimal();
if (ao_cmd_status != ao_cmd_success)
return;
if (ao_cmd_status != ao_cmd_success)
return;
{
if (usart->reg->sr & (1 << STM_USART_SR_RXNE)) {
if (!ao_fifo_full(usart->rx_fifo)) {
{
if (usart->reg->sr & (1 << STM_USART_SR_RXNE)) {
if (!ao_fifo_full(usart->rx_fifo)) {
- ao_fifo_insert(usart->rx_fifo, usart->reg->dr);
+ ao_fifo_insert(usart->rx_fifo, (char) usart->reg->dr);
ao_wakeup(&usart->rx_fifo);
if (is_stdin)
ao_wakeup(&ao_stdin_ready);
ao_wakeup(&usart->rx_fifo);
if (is_stdin)
ao_wakeup(&ao_stdin_ready);
- usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_RXNEIE);
_ao_usart_rx(usart, is_stdin);
if (!_ao_usart_tx_start(usart))
_ao_usart_rx(usart, is_stdin);
if (!_ao_usart_tx_start(usart))
- usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TXEIE);
if (usart->reg->sr & (1 << STM_USART_SR_TC)) {
usart->tx_running = 0;
if (usart->reg->sr & (1 << STM_USART_SR_TC)) {
usart->tx_running = 0;
- usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE);
+ usart->reg->cr1 &= ~(1UL << STM_USART_CR1_TCIE);
if (usart->draining) {
usart->draining = 0;
ao_wakeup(&usart->tx_fifo);
if (usart->draining) {
usart->draining = 0;
ao_wakeup(&usart->tx_fifo);
-_ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout)
+_ao_usart_sleep_for(struct ao_stm_usart *usart, AO_TICK_TYPE timeout)
{
return ao_sleep_for(&usart->rx_fifo, timeout);
}
{
return ao_sleep_for(&usart->rx_fifo, timeout);
}
-_ao_serial1_sleep_for(uint16_t timeout)
+_ao_serial1_sleep_for(AO_TICK_TYPE timeout)
{
return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
}
{
return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
}
-_ao_serial2_sleep_for(uint16_t timeout)
+_ao_serial2_sleep_for(AO_TICK_TYPE timeout)
{
return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
}
{
return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
}
-_ao_serial3_sleep_for(uint16_t timeout)
+_ao_serial3_sleep_for(AO_TICK_TYPE timeout)
{
return _ao_usart_sleep_for(&ao_stm_usart3, timeout);
}
{
return _ao_usart_sleep_for(&ao_stm_usart3, timeout);
}
ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart,
void (*isr)(void),
struct stm_gpio *port_rts,
ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart,
void (*isr)(void),
struct stm_gpio *port_rts,
struct stm_gpio *port_cts,
struct stm_gpio *port_cts,
{
/* Pull RTS low to note that there's space in the FIFO
*/
{
/* Pull RTS low to note that there's space in the FIFO
*/
stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
(1 << STM_SYSTICK_CSR_TICKINT) |
(STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
(1 << STM_SYSTICK_CSR_TICKINT) |
(STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
- stm_nvic.shpr15_12 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
+ stm_nvic.shpr15_12 |= (uint32_t) AO_STM_NVIC_CLOCK_PRIORITY << 24;
while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
ao_arch_nop();
while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
ao_arch_nop();
- stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
+ stm_rcc.cfgr = (stm_rcc.cfgr & ~(uint32_t) (STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
(STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
/* wait for system to switch to MSI */
(STM_RCC_CFGR_SW_MSI << STM_RCC_CFGR_SW);
/* wait for system to switch to MSI */
#if AO_HSE_BYPASS
stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
#else
#if AO_HSE_BYPASS
stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
#else
- stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
+ stm_rcc.cr &= ~(uint32_t) (1 << STM_RCC_CR_HSEBYP);
#endif
/* Enable HSE clock */
stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
#endif
/* Enable HSE clock */
stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
stm_rcc.cfgr = cfgr;
/* Disable the PLL */
stm_rcc.cfgr = cfgr;
/* Disable the PLL */
- stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
- while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
+ stm_rcc.cr &= ~(1UL << STM_RCC_CR_PLLON);
+ while (stm_rcc.cr & (1UL << STM_RCC_CR_PLLRDY))
asm("nop");
/* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
asm("nop");
/* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
/* PLL source */
cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
/* PLL source */
- cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
+ cfgr &= ~(1UL << STM_RCC_CFGR_PLLSRC);
cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
stm_rcc.cfgr = cfgr;
cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
stm_rcc.cfgr = cfgr;
static void
ao_usb_set_ep0(void)
{
static void
ao_usb_set_ep0(void)
{
return;
while (bytes >= 2) {
debug_data (" %02x %02x", src[0], src[1]);
return;
while (bytes >= 2) {
debug_data (" %02x %02x", src[0], src[1]);
- ao_usb_write_short((src[1] << 8) | src[0], base, offset);
+ ao_usb_write_short((uint16_t) ((uint16_t) (src[1] << 8) | (uint16_t) src[0]), base, offset);
offset += 2;
src += 2;
bytes -= 2;
offset += 2;
src += 2;
bytes -= 2;
static inline uint16_t
ao_usb_read_short(uint32_t *base, uint16_t offset)
{
static inline uint16_t
ao_usb_read_short(uint32_t *base, uint16_t offset)
{
- return base[offset>>1];
+ return (uint16_t) (base[offset>>1]);
}
while (bytes >= 2) {
uint16_t s = ao_usb_read_short(base, offset);
}
while (bytes >= 2) {
uint16_t s = ao_usb_read_short(base, offset);
- dst[0] = s;
- dst[1] = s >> 8;
+ dst[0] = (uint8_t) s;
+ dst[1] = (uint8_t) (s >> 8);
debug_data (" %02x %02x", dst[0], dst[1]);
offset += 2;
dst += 2;
debug_data (" %02x %02x", dst[0], dst[1]);
offset += 2;
dst += 2;
if (len > ao_usb_ep0_out_len)
len = ao_usb_ep0_out_len;
if (len > ao_usb_ep0_out_len)
len = ao_usb_ep0_out_len;
- ao_usb_ep0_out_len -= len;
+ ao_usb_ep0_out_len -= (uint8_t) len;
/* Pull all of the data out of the packet */
debug_data ("Fill EP0 len %d:", len);
/* Pull all of the data out of the packet */
debug_data ("Fill EP0 len %d:", len);
{
/* Don't send more than asked for */
if (ao_usb_ep0_in_len > max)
{
/* Don't send more than asked for */
if (ao_usb_ep0_in_len > max)
- ao_usb_ep0_in_len = max;
+ ao_usb_ep0_in_len = (uint8_t) max;
ao_usb_get_descriptor(uint16_t value, uint16_t length)
{
const uint8_t *descriptor;
ao_usb_get_descriptor(uint16_t value, uint16_t length)
{
const uint8_t *descriptor;
- uint8_t type = value >> 8;
- uint8_t index = value;
+ uint8_t type = (uint8_t) (value >> 8);
+ uint8_t index = (uint8_t) value;
descriptor = ao_usb_descriptors;
while (descriptor[0] != 0) {
descriptor = ao_usb_descriptors;
while (descriptor[0] != 0) {
else
len = descriptor[0];
if (len > length)
else
len = descriptor[0];
if (len > length)
+ len = (uint8_t) length;
ao_usb_ep0_in_set(descriptor, len);
break;
}
ao_usb_ep0_in_set(descriptor, len);
break;
}
break;
case AO_USB_REQ_SET_ADDRESS:
debug ("set address %d\n", ao_usb_setup.value);
break;
case AO_USB_REQ_SET_ADDRESS:
debug ("set address %d\n", ao_usb_setup.value);
- ao_usb_address = ao_usb_setup.value;
+ ao_usb_address = (uint8_t) ao_usb_setup.value;
ao_usb_address_pending = 1;
break;
case AO_USB_REQ_GET_DESCRIPTOR:
ao_usb_address_pending = 1;
break;
case AO_USB_REQ_GET_DESCRIPTOR:
ao_usb_ep0_in_queue_byte(ao_usb_configuration);
break;
case AO_USB_REQ_SET_CONFIGURATION:
ao_usb_ep0_in_queue_byte(ao_usb_configuration);
break;
case AO_USB_REQ_SET_CONFIGURATION:
- ao_usb_configuration = ao_usb_setup.value;
+ ao_usb_configuration = (uint8_t) ao_usb_setup.value;
debug ("set configuration %d\n", ao_usb_configuration);
ao_usb_set_configuration();
break;
debug ("set configuration %d\n", ao_usb_configuration);
ao_usb_set_configuration();
break;
epr_write = epr;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
epr_write = epr;
epr_write &= STM_USB_EPR_PRESERVE_MASK;
epr_write |= STM_USB_EPR_INVARIANT;
- epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
- epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
+ epr_write &= ~(1UL << STM_USB_EPR_CTR_RX);
+ epr_write &= ~(1UL << STM_USB_EPR_CTR_TX);
stm_usb.epr[ep] = epr_write;
switch (ep) {
stm_usb.epr[ep] = epr_write;
switch (ep) {
if (istr & (1 << STM_USB_ISTR_RESET)) {
++reset_count;
if (istr & (1 << STM_USB_ISTR_RESET)) {
++reset_count;
- stm_usb.istr &= ~(1 << STM_USB_ISTR_RESET);
+ stm_usb.istr &= ~(1UL << STM_USB_ISTR_RESET);
ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
ao_usb_ep0_handle(ao_usb_ep0_receive);
}
ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
ao_usb_ep0_handle(ao_usb_ep0_receive);
}
stm_usb_fs_wkup_isr(void)
{
/* USB wakeup, just clear the bit for now */
stm_usb_fs_wkup_isr(void)
{
/* USB wakeup, just clear the bit for now */
- stm_usb.istr &= ~(1 << STM_USB_ISTR_WKUP);
+ stm_usb.istr &= ~(1UL << STM_USB_ISTR_WKUP);
}
/* Queue the current IN buffer for transmission */
}
/* Queue the current IN buffer for transmission */
_rx_dbg0("out_recv top");
ao_usb_out_avail = 0;
_rx_dbg0("out_recv top");
ao_usb_out_avail = 0;
- ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
+ ao_usb_rx_count = (uint8_t) (ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK);
_rx_dbg1("out_recv count", ao_usb_rx_count);
debug ("recv %d\n", ao_usb_rx_count);
_rx_dbg1("out_recv count", ao_usb_rx_count);
debug ("recv %d\n", ao_usb_rx_count);
while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
ao_sleep(AO_USB_OUT_SLEEP_ADDR);
ao_arch_release_interrupts();
while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
ao_sleep(AO_USB_OUT_SLEEP_ADDR);
ao_arch_release_interrupts();
}
#ifndef HAS_USB_DISABLE
}
#ifndef HAS_USB_DISABLE
stm_usb.istr = 0;
/* Disable USB pull-up */
stm_usb.istr = 0;
/* Disable USB pull-up */
- stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
+ stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU);
/* Switch off the device */
stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
/* Disable the interface */
/* Switch off the device */
stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
/* Disable the interface */
- stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
+ stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN);
ao_arch_release_interrupts();
}
#endif
ao_arch_release_interrupts();
}
#endif
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
/* Disable USB pull-up */
stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
/* Disable USB pull-up */
- stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
+ stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU);
/* Enable USB device */
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
/* Enable USB device */
stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
};
#define STM_MODER_SHIFT(pin) ((pin) << 1)
};
#define STM_MODER_SHIFT(pin) ((pin) << 1)
-#define STM_MODER_MASK 3
+#define STM_MODER_MASK 3UL
#define STM_MODER_INPUT 0
#define STM_MODER_OUTPUT 1
#define STM_MODER_ALTERNATE 2
#define STM_MODER_INPUT 0
#define STM_MODER_OUTPUT 1
#define STM_MODER_ALTERNATE 2
static inline void
stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->moder = ((gpio->moder &
static inline void
stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->moder = ((gpio->moder &
- ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
+ (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
value << STM_MODER_SHIFT(pin));
}
value << STM_MODER_SHIFT(pin));
}
}
#define STM_OTYPER_SHIFT(pin) (pin)
}
#define STM_OTYPER_SHIFT(pin) (pin)
-#define STM_OTYPER_MASK 1
+#define STM_OTYPER_MASK 1UL
#define STM_OTYPER_PUSH_PULL 0
#define STM_OTYPER_OPEN_DRAIN 1
static inline void
stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->otyper = ((gpio->otyper &
#define STM_OTYPER_PUSH_PULL 0
#define STM_OTYPER_OPEN_DRAIN 1
static inline void
stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
gpio->otyper = ((gpio->otyper &
- ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
+ (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
value << STM_OTYPER_SHIFT(pin));
}
value << STM_OTYPER_SHIFT(pin));
}
}
#define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
}
#define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
-#define STM_OSPEEDR_MASK 3
+#define STM_OSPEEDR_MASK 3UL
#define STM_OSPEEDR_400kHz 0
#define STM_OSPEEDR_2MHz 1
#define STM_OSPEEDR_10MHz 2
#define STM_OSPEEDR_400kHz 0
#define STM_OSPEEDR_2MHz 1
#define STM_OSPEEDR_10MHz 2
static inline void
stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->ospeedr = ((gpio->ospeedr &
static inline void
stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->ospeedr = ((gpio->ospeedr &
- ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
+ (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
value << STM_OSPEEDR_SHIFT(pin));
}
value << STM_OSPEEDR_SHIFT(pin));
}
}
#define STM_PUPDR_SHIFT(pin) ((pin) << 1)
}
#define STM_PUPDR_SHIFT(pin) ((pin) << 1)
-#define STM_PUPDR_MASK 3
+#define STM_PUPDR_MASK 3UL
#define STM_PUPDR_NONE 0
#define STM_PUPDR_PULL_UP 1
#define STM_PUPDR_PULL_DOWN 2
#define STM_PUPDR_NONE 0
#define STM_PUPDR_PULL_UP 1
#define STM_PUPDR_PULL_DOWN 2
static inline void
stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->pupdr = ((gpio->pupdr &
static inline void
stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
gpio->pupdr = ((gpio->pupdr &
- ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
+ (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
value << STM_PUPDR_SHIFT(pin));
}
value << STM_PUPDR_SHIFT(pin));
}
}
#define STM_AFR_SHIFT(pin) ((pin) << 2)
}
#define STM_AFR_SHIFT(pin) ((pin) << 2)
-#define STM_AFR_MASK 0xf
+#define STM_AFR_MASK 0xfUL
#define STM_AFR_NONE 0
#define STM_AFR_AF0 0x0
#define STM_AFR_AF1 0x1
#define STM_AFR_NONE 0
#define STM_AFR_AF0 0x0
#define STM_AFR_AF1 0x1
stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
if (pin < 8)
gpio->afrl = ((gpio->afrl &
stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
if (pin < 8)
gpio->afrl = ((gpio->afrl &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
value << STM_AFR_SHIFT(pin));
else {
pin -= 8;
gpio->afrh = ((gpio->afrh &
value << STM_AFR_SHIFT(pin));
else {
pin -= 8;
gpio->afrh = ((gpio->afrh &
- ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
+ (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
value << STM_AFR_SHIFT(pin));
}
}
value << STM_AFR_SHIFT(pin));
}
}
static inline uint16_t
stm_gpio_get_all(struct stm_gpio *gpio) {
static inline uint16_t
stm_gpio_get_all(struct stm_gpio *gpio) {
+ return (uint16_t) gpio->idr;
#define STM_USART_CR2_LINEN (14) /* LIN mode enable */
#define STM_USART_CR2_STOP (12) /* STOP bits */
#define STM_USART_CR2_LINEN (14) /* LIN mode enable */
#define STM_USART_CR2_STOP (12) /* STOP bits */
-#define STM_USART_CR2_STOP_MASK 3
+#define STM_USART_CR2_STOP_MASK 3UL
#define STM_USART_CR2_STOP_1 0
#define STM_USART_CR2_STOP_0_5 1
#define STM_USART_CR2_STOP_2 2
#define STM_USART_CR2_STOP_1 0
#define STM_USART_CR2_STOP_0_5 1
#define STM_USART_CR2_STOP_2 2
#define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
#define STM_USART_CR2_LBDL (5) /* lin break detection length */
#define STM_USART_CR2_ADD (0)
#define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
#define STM_USART_CR2_LBDL (5) /* lin break detection length */
#define STM_USART_CR2_ADD (0)
-#define STM_USART_CR2_ADD_MASK 0xf
+#define STM_USART_CR2_ADD_MASK 0xfUL
#define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
#define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
#define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
#define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
#define STM_TIM1011_CR1_CKD_1 0
#define STM_TIM1011_CR1_CKD_2 1
#define STM_TIM1011_CR1_CKD_4 2
#define STM_TIM1011_CR1_CKD_1 0
#define STM_TIM1011_CR1_CKD_2 1
#define STM_TIM1011_CR1_CKD_4 2
-#define STM_TIM1011_CR1_CKD_MASK 3
+#define STM_TIM1011_CR1_CKD_MASK 3UL
#define STM_TIM1011_CR1_ARPE 7
#define STM_TIM1011_CR1_URS 2
#define STM_TIM1011_CR1_UDIS 1
#define STM_TIM1011_CR1_ARPE 7
#define STM_TIM1011_CR1_URS 2
#define STM_TIM1011_CR1_UDIS 1
#define STM_TIM1011_SMCR_ETPS_2 1
#define STM_TIM1011_SMCR_ETPS_4 2
#define STM_TIM1011_SMCR_ETPS_8 3
#define STM_TIM1011_SMCR_ETPS_2 1
#define STM_TIM1011_SMCR_ETPS_4 2
#define STM_TIM1011_SMCR_ETPS_8 3
-#define STM_TIM1011_SMCR_ETPS_MASK 3
+#define STM_TIM1011_SMCR_ETPS_MASK 3UL
#define STM_TIM1011_SMCR_ETF 8
#define STM_TIM1011_SMCR_ETF_NONE 0
#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
#define STM_TIM1011_SMCR_ETF 8
#define STM_TIM1011_SMCR_ETF_NONE 0
#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
-#define STM_TIM1011_SMCR_ETF_MASK 15
+#define STM_TIM1011_SMCR_ETF_MASK 15UL
#define STM_TIM1011_DIER_CC1E 1
#define STM_TIM1011_DIER_UIE 0
#define STM_TIM1011_DIER_CC1E 1
#define STM_TIM1011_DIER_UIE 0
#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM1011_CCMR1_OC1M_MASK 7
+#define STM_TIM1011_CCMR1_OC1M_MASK 7UL
#define STM_TIM1011_CCMR1_OC1PE 3
#define STM_TIM1011_CCMR1_OC1FE 2
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCMR1_OC1PE 3
#define STM_TIM1011_CCMR1_OC1FE 2
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM1011_CCMR1_CC1S_MASK 3
+#define STM_TIM1011_CCMR1_CC1S_MASK 3UL
#define STM_TIM1011_CCMR1_IC1F_NONE 0
#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
#define STM_TIM1011_CCMR1_IC1F_NONE 0
#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
-#define STM_TIM1011_CCMR1_IC1F_MASK 15
+#define STM_TIM1011_CCMR1_IC1F_MASK 15UL
#define STM_TIM1011_CCMR1_IC1PSC 2
#define STM_TIM1011_CCMR1_IC1PSC_1 0
#define STM_TIM1011_CCMR1_IC1PSC_2 1
#define STM_TIM1011_CCMR1_IC1PSC_4 2
#define STM_TIM1011_CCMR1_IC1PSC_8 3
#define STM_TIM1011_CCMR1_IC1PSC 2
#define STM_TIM1011_CCMR1_IC1PSC_1 0
#define STM_TIM1011_CCMR1_IC1PSC_2 1
#define STM_TIM1011_CCMR1_IC1PSC_4 2
#define STM_TIM1011_CCMR1_IC1PSC_8 3
-#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
+#define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCER_CC1NP 3
#define STM_TIM1011_CCMR1_CC1S 0
#define STM_TIM1011_CCER_CC1NP 3
#define STM_TIM1011_TI1_RMP_LSI 1
#define STM_TIM1011_TI1_RMP_LSE 2
#define STM_TIM1011_TI1_RMP_RTC 3
#define STM_TIM1011_TI1_RMP_LSI 1
#define STM_TIM1011_TI1_RMP_LSE 2
#define STM_TIM1011_TI1_RMP_RTC 3
-#define STM_TIM1011_TI1_RMP_MASK 3
+#define STM_TIM1011_TI1_RMP_MASK 3UL
#define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
#define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
#define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
#define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
#define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
#define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
-#define STM_RCC_CR_RTCPRE_HSE_MASK 3
+#define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
#define STM_RCC_CR_CSSON (28)
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CR_CSSON (28)
#define STM_RCC_CR_PLLRDY (25)
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
#define STM_RCC_CFGR_MCOPRE_DIV_4 2
#define STM_RCC_CFGR_MCOPRE_DIV_8 3
#define STM_RCC_CFGR_MCOPRE_DIV_16 4
-#define STM_RCC_CFGR_MCOPRE_MASK 7
+#define STM_RCC_CFGR_MCOPRE_MASK 7UL
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
#define STM_RCC_CFGR_MCOSEL (24)
#define STM_RCC_CFGR_MCOSEL_DISABLE 0
#define STM_RCC_CFGR_MCOSEL_PLL 5
#define STM_RCC_CFGR_MCOSEL_LSI 6
#define STM_RCC_CFGR_MCOSEL_LSE 7
#define STM_RCC_CFGR_MCOSEL_PLL 5
#define STM_RCC_CFGR_MCOSEL_LSI 6
#define STM_RCC_CFGR_MCOSEL_LSE 7
-#define STM_RCC_CFGR_MCOSEL_MASK 7
+#define STM_RCC_CFGR_MCOSEL_MASK 7UL
#define STM_RCC_CFGR_PLLDIV (22)
#define STM_RCC_CFGR_PLLDIV_2 1
#define STM_RCC_CFGR_PLLDIV_3 2
#define STM_RCC_CFGR_PLLDIV_4 3
#define STM_RCC_CFGR_PLLDIV (22)
#define STM_RCC_CFGR_PLLDIV_2 1
#define STM_RCC_CFGR_PLLDIV_3 2
#define STM_RCC_CFGR_PLLDIV_4 3
-#define STM_RCC_CFGR_PLLDIV_MASK 3
+#define STM_RCC_CFGR_PLLDIV_MASK 3UL
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_3 0
#define STM_RCC_CFGR_PLLMUL (18)
#define STM_RCC_CFGR_PLLMUL_3 0
#define STM_RCC_CFGR_PLLMUL_24 6
#define STM_RCC_CFGR_PLLMUL_32 7
#define STM_RCC_CFGR_PLLMUL_48 8
#define STM_RCC_CFGR_PLLMUL_24 6
#define STM_RCC_CFGR_PLLMUL_32 7
#define STM_RCC_CFGR_PLLMUL_48 8
-#define STM_RCC_CFGR_PLLMUL_MASK 0xf
+#define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PLLSRC (16)
#define STM_RCC_CFGR_PPRE2_DIV_4 5
#define STM_RCC_CFGR_PPRE2_DIV_8 6
#define STM_RCC_CFGR_PPRE2_DIV_16 7
#define STM_RCC_CFGR_PPRE2_DIV_4 5
#define STM_RCC_CFGR_PPRE2_DIV_8 6
#define STM_RCC_CFGR_PPRE2_DIV_16 7
-#define STM_RCC_CFGR_PPRE2_MASK 7
+#define STM_RCC_CFGR_PPRE2_MASK 7UL
#define STM_RCC_CFGR_PPRE1 (8)
#define STM_RCC_CFGR_PPRE1_DIV_1 0
#define STM_RCC_CFGR_PPRE1 (8)
#define STM_RCC_CFGR_PPRE1_DIV_1 0
#define STM_RCC_CFGR_PPRE1_DIV_4 5
#define STM_RCC_CFGR_PPRE1_DIV_8 6
#define STM_RCC_CFGR_PPRE1_DIV_16 7
#define STM_RCC_CFGR_PPRE1_DIV_4 5
#define STM_RCC_CFGR_PPRE1_DIV_8 6
#define STM_RCC_CFGR_PPRE1_DIV_16 7
-#define STM_RCC_CFGR_PPRE1_MASK 7
+#define STM_RCC_CFGR_PPRE1_MASK 7UL
#define STM_RCC_CFGR_HPRE (4)
#define STM_RCC_CFGR_HPRE_DIV_1 0
#define STM_RCC_CFGR_HPRE (4)
#define STM_RCC_CFGR_HPRE_DIV_1 0
#define STM_RCC_CFGR_HPRE_DIV_128 0xd
#define STM_RCC_CFGR_HPRE_DIV_256 0xe
#define STM_RCC_CFGR_HPRE_DIV_512 0xf
#define STM_RCC_CFGR_HPRE_DIV_128 0xd
#define STM_RCC_CFGR_HPRE_DIV_256 0xe
#define STM_RCC_CFGR_HPRE_DIV_512 0xf
-#define STM_RCC_CFGR_HPRE_MASK 0xf
+#define STM_RCC_CFGR_HPRE_MASK 0xfUL
#define STM_RCC_CFGR_SWS (2)
#define STM_RCC_CFGR_SWS_MSI 0
#define STM_RCC_CFGR_SWS_HSI 1
#define STM_RCC_CFGR_SWS_HSE 2
#define STM_RCC_CFGR_SWS_PLL 3
#define STM_RCC_CFGR_SWS (2)
#define STM_RCC_CFGR_SWS_MSI 0
#define STM_RCC_CFGR_SWS_HSI 1
#define STM_RCC_CFGR_SWS_HSE 2
#define STM_RCC_CFGR_SWS_PLL 3
-#define STM_RCC_CFGR_SWS_MASK 3
+#define STM_RCC_CFGR_SWS_MASK 3UL
#define STM_RCC_CFGR_SW (0)
#define STM_RCC_CFGR_SW_MSI 0
#define STM_RCC_CFGR_SW_HSI 1
#define STM_RCC_CFGR_SW_HSE 2
#define STM_RCC_CFGR_SW_PLL 3
#define STM_RCC_CFGR_SW (0)
#define STM_RCC_CFGR_SW_MSI 0
#define STM_RCC_CFGR_SW_HSI 1
#define STM_RCC_CFGR_SW_HSE 2
#define STM_RCC_CFGR_SW_PLL 3
-#define STM_RCC_CFGR_SW_MASK 3
+#define STM_RCC_CFGR_SW_MASK 3UL
#define STM_RCC_AHBENR_DMA1EN (24)
#define STM_RCC_AHBENR_FLITFEN (15)
#define STM_RCC_AHBENR_DMA1EN (24)
#define STM_RCC_AHBENR_FLITFEN (15)
#define STM_RCC_CSR_RTCSEL_LSE 1
#define STM_RCC_CSR_RTCSEL_LSI 2
#define STM_RCC_CSR_RTCSEL_HSE 3
#define STM_RCC_CSR_RTCSEL_LSE 1
#define STM_RCC_CSR_RTCSEL_LSI 2
#define STM_RCC_CSR_RTCSEL_HSE 3
-#define STM_RCC_CSR_RTCSEL_MASK 3
+#define STM_RCC_CSR_RTCSEL_MASK 3UL
#define STM_RCC_CSR_LSEBYP (10)
#define STM_RCC_CSR_LSERDY (9)
#define STM_RCC_CSR_LSEBYP (10)
#define STM_RCC_CSR_LSERDY (9)
#define STM_PWR_CR_LPRUN (14)
#define STM_PWR_CR_VOS (11)
#define STM_PWR_CR_LPRUN (14)
#define STM_PWR_CR_VOS (11)
-#define STM_PWR_CR_VOS_1_8 1
-#define STM_PWR_CR_VOS_1_5 2
-#define STM_PWR_CR_VOS_1_2 3
-#define STM_PWR_CR_VOS_MASK 3
+#define STM_PWR_CR_VOS_1_8 1UL
+#define STM_PWR_CR_VOS_1_5 2UL
+#define STM_PWR_CR_VOS_1_2 3UL
+#define STM_PWR_CR_VOS_MASK 3UL
#define STM_PWR_CR_FWU (10)
#define STM_PWR_CR_ULP (9)
#define STM_PWR_CR_FWU (10)
#define STM_PWR_CR_ULP (9)
#define STM_PWR_CR_PLS_2_9 5
#define STM_PWR_CR_PLS_3_1 6
#define STM_PWR_CR_PLS_EXT 7
#define STM_PWR_CR_PLS_2_9 5
#define STM_PWR_CR_PLS_3_1 6
#define STM_PWR_CR_PLS_EXT 7
-#define STM_PWR_CR_PLS_MASK 7
+#define STM_PWR_CR_PLS_MASK 7UL
#define STM_PWR_CR_PVDE (4)
#define STM_PWR_CR_CSBF (3)
#define STM_PWR_CR_PVDE (4)
#define STM_PWR_CR_CSBF (3)
#define STM_TIM67_CR2_MMS_RESET 0
#define STM_TIM67_CR2_MMS_ENABLE 1
#define STM_TIM67_CR2_MMS_UPDATE 2
#define STM_TIM67_CR2_MMS_RESET 0
#define STM_TIM67_CR2_MMS_ENABLE 1
#define STM_TIM67_CR2_MMS_UPDATE 2
-#define STM_TIM67_CR2_MMS_MASK 7
+#define STM_TIM67_CR2_MMS_MASK 7UL
#define STM_TIM67_DIER_UDE (8)
#define STM_TIM67_DIER_UIE (0)
#define STM_TIM67_DIER_UDE (8)
#define STM_TIM67_DIER_UIE (0)
#define STM_LCD_CR_BIAS_1_4 0
#define STM_LCD_CR_BIAS_1_2 1
#define STM_LCD_CR_BIAS_1_3 2
#define STM_LCD_CR_BIAS_1_4 0
#define STM_LCD_CR_BIAS_1_2 1
#define STM_LCD_CR_BIAS_1_3 2
-#define STM_LCD_CR_BIAS_MASK 3
+#define STM_LCD_CR_BIAS_MASK 3UL
#define STM_LCD_CR_DUTY (2)
#define STM_LCD_CR_DUTY_STATIC 0
#define STM_LCD_CR_DUTY (2)
#define STM_LCD_CR_DUTY_STATIC 0
#define STM_LCD_CR_DUTY_1_3 2
#define STM_LCD_CR_DUTY_1_4 3
#define STM_LCD_CR_DUTY_1_8 4
#define STM_LCD_CR_DUTY_1_3 2
#define STM_LCD_CR_DUTY_1_4 3
#define STM_LCD_CR_DUTY_1_8 4
-#define STM_LCD_CR_DUTY_MASK 7
+#define STM_LCD_CR_DUTY_MASK 7UL
#define STM_LCD_CR_VSEL (1)
#define STM_LCD_CR_LCDEN (0)
#define STM_LCD_CR_VSEL (1)
#define STM_LCD_CR_LCDEN (0)
#define STM_LCD_FCR_PS_8192 0xd
#define STM_LCD_FCR_PS_16384 0xe
#define STM_LCD_FCR_PS_32768 0xf
#define STM_LCD_FCR_PS_8192 0xd
#define STM_LCD_FCR_PS_16384 0xe
#define STM_LCD_FCR_PS_32768 0xf
-#define STM_LCD_FCR_PS_MASK 0xf
+#define STM_LCD_FCR_PS_MASK 0xfUL
#define STM_LCD_FCR_DIV (18)
#define STM_LCD_FCR_DIV_16 0x0
#define STM_LCD_FCR_DIV (18)
#define STM_LCD_FCR_DIV_16 0x0
#define STM_LCD_FCR_DIV_29 0xd
#define STM_LCD_FCR_DIV_30 0xe
#define STM_LCD_FCR_DIV_31 0xf
#define STM_LCD_FCR_DIV_29 0xd
#define STM_LCD_FCR_DIV_30 0xe
#define STM_LCD_FCR_DIV_31 0xf
-#define STM_LCD_FCR_DIV_MASK 0xf
+#define STM_LCD_FCR_DIV_MASK 0xfUL
#define STM_LCD_FCR_BLINK (16)
#define STM_LCD_FCR_BLINK_DISABLE 0
#define STM_LCD_FCR_BLINK_SEG0_COM0 1
#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
#define STM_LCD_FCR_BLINK (16)
#define STM_LCD_FCR_BLINK_DISABLE 0
#define STM_LCD_FCR_BLINK_SEG0_COM0 1
#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
-#define STM_LCD_FCR_BLINK_MASK 3
+#define STM_LCD_FCR_BLINK_MASK 3UL
#define STM_LCD_FCR_BLINKF (13)
#define STM_LCD_FCR_BLINKF_8 0
#define STM_LCD_FCR_BLINKF (13)
#define STM_LCD_FCR_BLINKF_8 0
#define STM_LCD_FCR_BLINKF_256 5
#define STM_LCD_FCR_BLINKF_512 6
#define STM_LCD_FCR_BLINKF_1024 7
#define STM_LCD_FCR_BLINKF_256 5
#define STM_LCD_FCR_BLINKF_512 6
#define STM_LCD_FCR_BLINKF_1024 7
-#define STM_LCD_FCR_BLINKF_MASK 7
+#define STM_LCD_FCR_BLINKF_MASK 7UL
#define STM_LCD_FCR_CC (10)
#define STM_LCD_FCR_CC (10)
-#define STM_LCD_FCR_CC_MASK 7
+#define STM_LCD_FCR_CC_MASK 7UL
#define STM_LCD_FCR_DEAD (7)
#define STM_LCD_FCR_DEAD (7)
-#define STM_LCD_FCR_DEAD_MASK 7
+#define STM_LCD_FCR_DEAD_MASK 7UL
#define STM_LCD_FCR_PON (4)
#define STM_LCD_FCR_PON (4)
-#define STM_LCD_FCR_PON_MASK 7
+#define STM_LCD_FCR_PON_MASK 7UL
#define STM_LCD_FCR_UDDIE (3)
#define STM_LCD_FCR_SOFIE (1)
#define STM_LCD_FCR_UDDIE (3)
#define STM_LCD_FCR_SOFIE (1)
uint32_t v;
v = stm_nvic.ipr[n];
uint32_t v;
v = stm_nvic.ipr[n];
- v &= ~IRQ_PRIO_MASK(irq);
+ v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
v |= (prio) << IRQ_PRIO_BIT(irq);
stm_nvic.ipr[n] = v;
}
v |= (prio) << IRQ_PRIO_BIT(irq);
stm_nvic.ipr[n] = v;
}
extern struct stm_mpu stm_mpu;
#define STM_MPU_TYPER_IREGION 16
extern struct stm_mpu stm_mpu;
#define STM_MPU_TYPER_IREGION 16
-#define STM_MPU_TYPER_IREGION_MASK 0xff
+#define STM_MPU_TYPER_IREGION_MASK 0xffUL
#define STM_MPU_TYPER_DREGION 8
#define STM_MPU_TYPER_DREGION 8
-#define STM_MPU_TYPER_DREGION_MASK 0xff
+#define STM_MPU_TYPER_DREGION_MASK 0xffUL
#define STM_MPU_TYPER_SEPARATE 0
#define STM_MPU_CR_PRIVDEFENA 2
#define STM_MPU_TYPER_SEPARATE 0
#define STM_MPU_CR_PRIVDEFENA 2
#define STM_MPU_CR_ENABLE 0
#define STM_MPU_RNR_REGION 0
#define STM_MPU_CR_ENABLE 0
#define STM_MPU_RNR_REGION 0
-#define STM_MPU_RNR_REGION_MASK 0xff
+#define STM_MPU_RNR_REGION_MASK 0xffUL
#define STM_MPU_RBAR_ADDR 5
#define STM_MPU_RBAR_ADDR 5
-#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
+#define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL
#define STM_MPU_RBAR_VALID 4
#define STM_MPU_RBAR_REGION 0
#define STM_MPU_RBAR_VALID 4
#define STM_MPU_RBAR_REGION 0
-#define STM_MPU_RBAR_REGION_MASK 0xf
+#define STM_MPU_RBAR_REGION_MASK 0xfUL
#define STM_MPU_RASR_XN 28
#define STM_MPU_RASR_AP 24
#define STM_MPU_RASR_XN 28
#define STM_MPU_RASR_AP 24
#define STM_MPU_RASR_AP_RW_RW 3
#define STM_MPU_RASR_AP_RO_NONE 5
#define STM_MPU_RASR_AP_RO_RO 6
#define STM_MPU_RASR_AP_RW_RW 3
#define STM_MPU_RASR_AP_RO_NONE 5
#define STM_MPU_RASR_AP_RO_RO 6
-#define STM_MPU_RASR_AP_MASK 7
+#define STM_MPU_RASR_AP_MASK 7UL
#define STM_MPU_RASR_TEX 19
#define STM_MPU_RASR_TEX 19
-#define STM_MPU_RASR_TEX_MASK 7
+#define STM_MPU_RASR_TEX_MASK 7UL
#define STM_MPU_RASR_S 18
#define STM_MPU_RASR_C 17
#define STM_MPU_RASR_B 16
#define STM_MPU_RASR_SRD 8
#define STM_MPU_RASR_S 18
#define STM_MPU_RASR_C 17
#define STM_MPU_RASR_B 16
#define STM_MPU_RASR_SRD 8
-#define STM_MPU_RASR_SRD_MASK 0xff
+#define STM_MPU_RASR_SRD_MASK 0xffUL
#define STM_MPU_RASR_SIZE 1
#define STM_MPU_RASR_SIZE 1
-#define STM_MPU_RASR_SIZE_MASK 0x1f
+#define STM_MPU_RASR_SIZE_MASK 0x1fUL
#define STM_MPU_RASR_ENABLE 0
#define isr_decl(name) void stm_ ## name ## _isr(void)
#define STM_MPU_RASR_ENABLE 0
#define isr_decl(name) void stm_ ## name ## _isr(void)
#define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
#define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
#define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
#define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
#define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
#define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
-#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
+#define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL
#define STM_SYSCFG_PMC_USB_PU 0
#define STM_SYSCFG_PMC_USB_PU 0
static inline void
stm_exticr_set(struct stm_gpio *gpio, int pin) {
static inline void
stm_exticr_set(struct stm_gpio *gpio, int pin) {
- uint8_t reg = pin >> 2;
+ uint8_t reg = (uint8_t) (pin >> 2);
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
uint8_t shift = (pin & 3) << 2;
uint8_t val = 0;
else if (gpio == &stm_gpioe)
val = STM_SYSCFG_EXTICR_PE;
else if (gpio == &stm_gpioe)
val = STM_SYSCFG_EXTICR_PE;
- stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
+ stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_ISR(index) ((index) << 2)
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_ISR(index) ((index) << 2)
-#define STM_DMA_ISR_MASK 0xf
+#define STM_DMA_ISR_MASK 0xfUL
#define STM_DMA_ISR_TEIF 3
#define STM_DMA_ISR_HTIF 2
#define STM_DMA_ISR_TCIF 1
#define STM_DMA_ISR_GIF 0
#define STM_DMA_IFCR(index) ((index) << 2)
#define STM_DMA_ISR_TEIF 3
#define STM_DMA_ISR_HTIF 2
#define STM_DMA_ISR_TCIF 1
#define STM_DMA_ISR_GIF 0
#define STM_DMA_IFCR(index) ((index) << 2)
-#define STM_DMA_IFCR_MASK 0xf
+#define STM_DMA_IFCR_MASK 0xfUL
#define STM_DMA_IFCR_CTEIF 3
#define STM_DMA_IFCR_CHTIF 2
#define STM_DMA_IFCR_CTCIF 1
#define STM_DMA_IFCR_CTEIF 3
#define STM_DMA_IFCR_CHTIF 2
#define STM_DMA_IFCR_CTCIF 1
#define STM_SPI_CR1_BR_PCLK_64 5
#define STM_SPI_CR1_BR_PCLK_128 6
#define STM_SPI_CR1_BR_PCLK_256 7
#define STM_SPI_CR1_BR_PCLK_64 5
#define STM_SPI_CR1_BR_PCLK_128 6
#define STM_SPI_CR1_BR_PCLK_256 7
-#define STM_SPI_CR1_BR_MASK 7
+#define STM_SPI_CR1_BR_MASK 7UL
#define STM_SPI_CR1_MSTR 2
#define STM_SPI_CR1_CPOL 1
#define STM_SPI_CR1_MSTR 2
#define STM_SPI_CR1_CPOL 1
#define STM_ADC_CR1_RES_10 1
#define STM_ADC_CR1_RES_8 2
#define STM_ADC_CR1_RES_6 3
#define STM_ADC_CR1_RES_10 1
#define STM_ADC_CR1_RES_8 2
#define STM_ADC_CR1_RES_6 3
-#define STM_ADC_CR1_RES_MASK 3
+#define STM_ADC_CR1_RES_MASK 3UL
#define STM_ADC_CR1_AWDEN 23
#define STM_ADC_CR1_JAWDEN 22
#define STM_ADC_CR1_PDI 17
#define STM_ADC_CR1_AWDEN 23
#define STM_ADC_CR1_JAWDEN 22
#define STM_ADC_CR1_PDI 17
#define STM_ADC_CR1_DISCNUM_6 5
#define STM_ADC_CR1_DISCNUM_7 6
#define STM_ADC_CR1_DISCNUM_8 7
#define STM_ADC_CR1_DISCNUM_6 5
#define STM_ADC_CR1_DISCNUM_7 6
#define STM_ADC_CR1_DISCNUM_8 7
-#define STM_ADC_CR1_DISCNUM_MASK 7
+#define STM_ADC_CR1_DISCNUM_MASK 7UL
#define STM_ADC_CR1_JDISCEN 12
#define STM_ADC_CR1_DISCEN 11
#define STM_ADC_CR1_JAUTO 10
#define STM_ADC_CR1_JDISCEN 12
#define STM_ADC_CR1_DISCEN 11
#define STM_ADC_CR1_JAUTO 10
#define STM_ADC_CR1_AWDIE 6
#define STM_ADC_CR1_EOCIE 5
#define STM_ADC_CR1_AWDCH 0
#define STM_ADC_CR1_AWDIE 6
#define STM_ADC_CR1_EOCIE 5
#define STM_ADC_CR1_AWDCH 0
-#define STM_ADC_CR1_AWDCH_MASK 0x1f
+#define STM_ADC_CR1_AWDCH_MASK 0x1fUL
#define STM_ADC_CR2_SWSTART 30
#define STM_ADC_CR2_EXTEN 28
#define STM_ADC_CR2_SWSTART 30
#define STM_ADC_CR2_EXTEN 28
#define STM_ADC_CR2_EXTEN_RISING 1
#define STM_ADC_CR2_EXTEN_FALLING 2
#define STM_ADC_CR2_EXTEN_BOTH 3
#define STM_ADC_CR2_EXTEN_RISING 1
#define STM_ADC_CR2_EXTEN_FALLING 2
#define STM_ADC_CR2_EXTEN_BOTH 3
-#define STM_ADC_CR2_EXTEN_MASK 3
+#define STM_ADC_CR2_EXTEN_MASK 3UL
#define STM_ADC_CR2_EXTSEL 24
#define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
#define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
#define STM_ADC_CR2_EXTSEL 24
#define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
#define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
#define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
#define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
#define STM_ADC_CR2_EXTSEL_EXTI_11 15
#define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
#define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
#define STM_ADC_CR2_EXTSEL_EXTI_11 15
-#define STM_ADC_CR2_EXTSEL_MASK 15
+#define STM_ADC_CR2_EXTSEL_MASK 15UL
#define STM_ADC_CR2_JWSTART 22
#define STM_ADC_CR2_JEXTEN 20
#define STM_ADC_CR2_JEXTEN_DISABLE 0
#define STM_ADC_CR2_JEXTEN_RISING 1
#define STM_ADC_CR2_JEXTEN_FALLING 2
#define STM_ADC_CR2_JEXTEN_BOTH 3
#define STM_ADC_CR2_JWSTART 22
#define STM_ADC_CR2_JEXTEN 20
#define STM_ADC_CR2_JEXTEN_DISABLE 0
#define STM_ADC_CR2_JEXTEN_RISING 1
#define STM_ADC_CR2_JEXTEN_FALLING 2
#define STM_ADC_CR2_JEXTEN_BOTH 3
-#define STM_ADC_CR2_JEXTEN_MASK 3
+#define STM_ADC_CR2_JEXTEN_MASK 3UL
#define STM_ADC_CR2_JEXTSEL 16
#define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
#define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
#define STM_ADC_CR2_JEXTSEL 16
#define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
#define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
#define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
#define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
#define STM_ADC_CR2_JEXTSEL_EXTI_15 15
#define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
#define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
#define STM_ADC_CR2_JEXTSEL_EXTI_15 15
-#define STM_ADC_CR2_JEXTSEL_MASK 15
+#define STM_ADC_CR2_JEXTSEL_MASK 15UL
#define STM_ADC_CR2_ALIGN 11
#define STM_ADC_CR2_EOCS 10
#define STM_ADC_CR2_DDS 9
#define STM_ADC_CR2_ALIGN 11
#define STM_ADC_CR2_EOCS 10
#define STM_ADC_CR2_DDS 9
#define STM_ADC_CR2_DELS_63 5
#define STM_ADC_CR2_DELS_127 6
#define STM_ADC_CR2_DELS_255 7
#define STM_ADC_CR2_DELS_63 5
#define STM_ADC_CR2_DELS_127 6
#define STM_ADC_CR2_DELS_255 7
-#define STM_ADC_CR2_DELS_MASK 7
+#define STM_ADC_CR2_DELS_MASK 7UL
#define STM_ADC_CR2_CONT 1
#define STM_ADC_CR2_ADON 0
#define STM_ADC_CR2_CONT 1
#define STM_ADC_CR2_ADON 0
#define STM_ADC_CCR_ADCPRE_HSI_1 0
#define STM_ADC_CCR_ADCPRE_HSI_2 1
#define STM_ADC_CCR_ADCPRE_HSI_4 2
#define STM_ADC_CCR_ADCPRE_HSI_1 0
#define STM_ADC_CCR_ADCPRE_HSI_2 1
#define STM_ADC_CCR_ADCPRE_HSI_4 2
-#define STM_ADC_CCR_ADCPRE_MASK 3
+#define STM_ADC_CCR_ADCPRE_MASK 3UL
struct stm_temp_cal {
uint16_t vref;
struct stm_temp_cal {
uint16_t vref;
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_24_MHZ 24
#define STM_I2C_CR2_FREQ_32_MHZ 32
#define STM_I2C_CR2_FREQ_16_MHZ 16
#define STM_I2C_CR2_FREQ_24_MHZ 24
#define STM_I2C_CR2_FREQ_32_MHZ 32
-#define STM_I2C_CR2_FREQ_MASK 0x3f
+#define STM_I2C_CR2_FREQ_MASK 0x3fUL
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_I2C_SR1_SMBALERT 15
#define STM_I2C_SR1_TIMEOUT 14
#define STM_I2C_SR1_SB 0
#define STM_I2C_SR2_PEC 8
#define STM_I2C_SR1_SB 0
#define STM_I2C_SR2_PEC 8
-#define STM_I2C_SR2_PEC_MASK 0xff00
+#define STM_I2C_SR2_PEC_MASK 0xff00UL
#define STM_I2C_SR2_DUALF 7
#define STM_I2C_SR2_SMBHOST 6
#define STM_I2C_SR2_SMBDEFAULT 5
#define STM_I2C_SR2_DUALF 7
#define STM_I2C_SR2_SMBHOST 6
#define STM_I2C_SR2_SMBDEFAULT 5
#define STM_I2C_CCR_FS 15
#define STM_I2C_CCR_DUTY 14
#define STM_I2C_CCR_CCR 0
#define STM_I2C_CCR_FS 15
#define STM_I2C_CCR_DUTY 14
#define STM_I2C_CCR_CCR 0
-#define STM_I2C_CCR_MASK 0x7ff
+#define STM_I2C_CCR_MASK 0x7ffUL
struct stm_tim234 {
vuint32_t cr1;
struct stm_tim234 {
vuint32_t cr1;
#define STM_TIM234_CR1_CKD_1 0
#define STM_TIM234_CR1_CKD_2 1
#define STM_TIM234_CR1_CKD_4 2
#define STM_TIM234_CR1_CKD_1 0
#define STM_TIM234_CR1_CKD_2 1
#define STM_TIM234_CR1_CKD_4 2
-#define STM_TIM234_CR1_CKD_MASK 3
+#define STM_TIM234_CR1_CKD_MASK 3UL
#define STM_TIM234_CR1_ARPE 7
#define STM_TIM234_CR1_CMS 5
#define STM_TIM234_CR1_CMS_EDGE 0
#define STM_TIM234_CR1_CMS_CENTER_1 1
#define STM_TIM234_CR1_CMS_CENTER_2 2
#define STM_TIM234_CR1_CMS_CENTER_3 3
#define STM_TIM234_CR1_ARPE 7
#define STM_TIM234_CR1_CMS 5
#define STM_TIM234_CR1_CMS_EDGE 0
#define STM_TIM234_CR1_CMS_CENTER_1 1
#define STM_TIM234_CR1_CMS_CENTER_2 2
#define STM_TIM234_CR1_CMS_CENTER_3 3
-#define STM_TIM234_CR1_CMS_MASK 3
+#define STM_TIM234_CR1_CMS_MASK 3UL
#define STM_TIM234_CR1_DIR 4
#define STM_TIM234_CR1_DIR_UP 0
#define STM_TIM234_CR1_DIR_DOWN 1
#define STM_TIM234_CR1_DIR 4
#define STM_TIM234_CR1_DIR_UP 0
#define STM_TIM234_CR1_DIR_DOWN 1
#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
#define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
#define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
#define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
-#define STM_TIM234_CR2_MMS_MASK 7
+#define STM_TIM234_CR2_MMS_MASK 7UL
#define STM_TIM234_CR2_CCDS 3
#define STM_TIM234_SMCR_ETP 15
#define STM_TIM234_CR2_CCDS 3
#define STM_TIM234_SMCR_ETP 15
#define STM_TIM234_SMCR_ETPS_DIV_2 1
#define STM_TIM234_SMCR_ETPS_DIV_4 2
#define STM_TIM234_SMCR_ETPS_DIV_8 3
#define STM_TIM234_SMCR_ETPS_DIV_2 1
#define STM_TIM234_SMCR_ETPS_DIV_4 2
#define STM_TIM234_SMCR_ETPS_DIV_8 3
-#define STM_TIM234_SMCR_ETPS_MASK 3
+#define STM_TIM234_SMCR_ETPS_MASK 3UL
#define STM_TIM234_SMCR_ETF 8
#define STM_TIM234_SMCR_ETF_NONE 0
#define STM_TIM234_SMCR_ETF_INT_N_2 1
#define STM_TIM234_SMCR_ETF 8
#define STM_TIM234_SMCR_ETF_NONE 0
#define STM_TIM234_SMCR_ETF_INT_N_2 1
#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
#define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
#define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
#define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
-#define STM_TIM234_SMCR_ETF_MASK 15
+#define STM_TIM234_SMCR_ETF_MASK 15UL
#define STM_TIM234_SMCR_MSM 7
#define STM_TIM234_SMCR_TS 4
#define STM_TIM234_SMCR_TS_ITR0 0
#define STM_TIM234_SMCR_MSM 7
#define STM_TIM234_SMCR_TS 4
#define STM_TIM234_SMCR_TS_ITR0 0
#define STM_TIM234_SMCR_TS_TI1FP1 5
#define STM_TIM234_SMCR_TS_TI2FP2 6
#define STM_TIM234_SMCR_TS_ETRF 7
#define STM_TIM234_SMCR_TS_TI1FP1 5
#define STM_TIM234_SMCR_TS_TI2FP2 6
#define STM_TIM234_SMCR_TS_ETRF 7
-#define STM_TIM234_SMCR_TS_MASK 7
+#define STM_TIM234_SMCR_TS_MASK 7UL
#define STM_TIM234_SMCR_OCCS 3
#define STM_TIM234_SMCR_SMS 0
#define STM_TIM234_SMCR_SMS_DISABLE 0
#define STM_TIM234_SMCR_OCCS 3
#define STM_TIM234_SMCR_SMS 0
#define STM_TIM234_SMCR_SMS_DISABLE 0
#define STM_TIM234_SMCR_SMS_GATED_MODE 5
#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
#define STM_TIM234_SMCR_SMS_GATED_MODE 5
#define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
#define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
-#define STM_TIM234_SMCR_SMS_MASK 7
+#define STM_TIM234_SMCR_SMS_MASK 7UL
#define STM_TIM234_DIER_TDE 14
#define STM_TIM234_DIER_CC4DE 12
#define STM_TIM234_DIER_TDE 14
#define STM_TIM234_DIER_CC4DE 12
#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
#define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC2M_MASK 7
+#define STM_TIM234_CCMR1_OC2M_MASK 7UL
#define STM_TIM234_CCMR1_OC2PE 11
#define STM_TIM234_CCMR1_OC2FE 10
#define STM_TIM234_CCMR1_CC2S 8
#define STM_TIM234_CCMR1_OC2PE 11
#define STM_TIM234_CCMR1_OC2FE 10
#define STM_TIM234_CCMR1_CC2S 8
#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
#define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
#define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
#define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC2S_MASK 3
+#define STM_TIM234_CCMR1_CC2S_MASK 3UL
#define STM_TIM234_CCMR1_OC1CE 7
#define STM_TIM234_CCMR1_OC1M 4
#define STM_TIM234_CCMR1_OC1CE 7
#define STM_TIM234_CCMR1_OC1M 4
#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
#define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
#define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM234_CCMR1_OC1M_MASK 7
+#define STM_TIM234_CCMR1_OC1M_MASK 7UL
#define STM_TIM234_CCMR1_OC1PE 3
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_OC1PE 3
#define STM_TIM234_CCMR1_OC1FE 2
#define STM_TIM234_CCMR1_CC1S 0
#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
#define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
#define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
#define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM234_CCMR1_CC1S_MASK 3
+#define STM_TIM234_CCMR1_CC1S_MASK 3UL
#define STM_TIM234_CCMR1_IC2F 12
#define STM_TIM234_CCMR1_IC2F_NONE 0
#define STM_TIM234_CCMR1_IC2F 12
#define STM_TIM234_CCMR1_IC2F_NONE 0
#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
#define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC4M_MASK 7
+#define STM_TIM234_CCMR2_OC4M_MASK 7UL
#define STM_TIM234_CCMR2_OC4PE 11
#define STM_TIM234_CCMR2_OC4FE 10
#define STM_TIM234_CCMR2_CC4S 8
#define STM_TIM234_CCMR2_OC4PE 11
#define STM_TIM234_CCMR2_OC4FE 10
#define STM_TIM234_CCMR2_CC4S 8
#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
#define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
#define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
#define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC4S_MASK 3
+#define STM_TIM234_CCMR2_CC4S_MASK 3UL
#define STM_TIM234_CCMR2_OC3CE 7
#define STM_TIM234_CCMR2_OC3M 4
#define STM_TIM234_CCMR2_OC3CE 7
#define STM_TIM234_CCMR2_OC3M 4
#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
#define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
#define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
-#define STM_TIM234_CCMR2_OC3M_MASK 7
+#define STM_TIM234_CCMR2_OC3M_MASK 7UL
#define STM_TIM234_CCMR2_OC3PE 3
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_OC3PE 3
#define STM_TIM234_CCMR2_OC3FE 2
#define STM_TIM234_CCMR2_CC3S 0
#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
#define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
#define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
#define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
-#define STM_TIM234_CCMR2_CC3S_MASK 3
+#define STM_TIM234_CCMR2_CC3S_MASK 3UL
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
#define STM_TIM234_CCER_CC4NP 15
#define STM_TIM234_CCER_CC4P 13
#define STM_USB_EPR_STAT_RX_STALL 1
#define STM_USB_EPR_STAT_RX_NAK 2
#define STM_USB_EPR_STAT_RX_VALID 3
#define STM_USB_EPR_STAT_RX_STALL 1
#define STM_USB_EPR_STAT_RX_NAK 2
#define STM_USB_EPR_STAT_RX_VALID 3
-#define STM_USB_EPR_STAT_RX_MASK 3
+#define STM_USB_EPR_STAT_RX_MASK 3UL
#define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
#define STM_USB_EPR_SETUP 11
#define STM_USB_EPR_EP_TYPE 9
#define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
#define STM_USB_EPR_SETUP 11
#define STM_USB_EPR_EP_TYPE 9
#define STM_USB_EPR_EP_TYPE_CONTROL 1
#define STM_USB_EPR_EP_TYPE_ISO 2
#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
#define STM_USB_EPR_EP_TYPE_CONTROL 1
#define STM_USB_EPR_EP_TYPE_ISO 2
#define STM_USB_EPR_EP_TYPE_INTERRUPT 3
-#define STM_USB_EPR_EP_TYPE_MASK 3
+#define STM_USB_EPR_EP_TYPE_MASK 3UL
#define STM_USB_EPR_EP_KIND 8
#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
#define STM_USB_EPR_EP_KIND 8
#define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
#define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
#define STM_USB_EPR_STAT_TX_NAK 2
#define STM_USB_EPR_STAT_TX_VALID 3
#define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
#define STM_USB_EPR_STAT_TX_NAK 2
#define STM_USB_EPR_STAT_TX_VALID 3
#define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
-#define STM_USB_EPR_STAT_TX_MASK 3
+#define STM_USB_EPR_STAT_TX_MASK 3UL
-#define STM_USB_EPR_EA_MASK 0xf
+#define STM_USB_EPR_EA_MASK 0xfUL
#define STM_USB_CNTR_CTRM 15
#define STM_USB_CNTR_PMAOVRM 14
#define STM_USB_CNTR_CTRM 15
#define STM_USB_CNTR_PMAOVRM 14
#define STM_USB_ISTR_ESOF 8
#define STM_USB_ISTR_DIR 4
#define STM_USB_ISTR_EP_ID 0
#define STM_USB_ISTR_ESOF 8
#define STM_USB_ISTR_DIR 4
#define STM_USB_ISTR_EP_ID 0
-#define STM_USB_ISTR_EP_ID_MASK 0xf
+#define STM_USB_ISTR_EP_ID_MASK 0xfUL
#define STM_USB_FNR_RXDP 15
#define STM_USB_FNR_RXDM 14
#define STM_USB_FNR_LCK 13
#define STM_USB_FNR_LSOF 11
#define STM_USB_FNR_RXDP 15
#define STM_USB_FNR_RXDM 14
#define STM_USB_FNR_LCK 13
#define STM_USB_FNR_LSOF 11
-#define STM_USB_FNR_LSOF_MASK 0x3
+#define STM_USB_FNR_LSOF_MASK 0x3UL
-#define STM_USB_FNR_FN_MASK 0x7ff
+#define STM_USB_FNR_FN_MASK 0x7ffUL
#define STM_USB_DADDR_EF 7
#define STM_USB_DADDR_ADD 0
#define STM_USB_DADDR_EF 7
#define STM_USB_DADDR_ADD 0
-#define STM_USB_DADDR_ADD_MASK 0x7f
+#define STM_USB_DADDR_ADD_MASK 0x7fUL
extern struct stm_usb stm_usb;
extern struct stm_usb stm_usb;
#define STM_USB_BDT_COUNT_RX_BL_SIZE 15
#define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
#define STM_USB_BDT_COUNT_RX_BL_SIZE 15
#define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
-#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
+#define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL
#define STM_USB_BDT_COUNT_RX_COUNT_RX 0
#define STM_USB_BDT_COUNT_RX_COUNT_RX 0
-#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
+#define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ffUL
#define STM_USB_BDT_SIZE 8
#define STM_USB_BDT_SIZE 8