--- /dev/null
+/*
+ * Copyright © 2013 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <ao.h>
+#include <ao_cc115l.h>
+#include <ao_exti.h>
+#include <ao_telemetry.h>
+#include <ao_fec.h>
+
+#define AO_RADIO_MAX_SEND sizeof (struct ao_telemetry_generic)
+
+static uint8_t ao_radio_mutex;
+
+static uint8_t ao_radio_wake; /* radio ready. Also used as sleep address */
+static uint8_t ao_radio_abort; /* radio operation should abort */
+static uint8_t ao_radio_mcu_wake; /* MARC status change */
+static uint8_t ao_radio_marcstate; /* Last read MARC state value */
+
+#define CC115L_DEBUG AO_FEC_DEBUG
+#define CC115L_TRACE 1
+
+extern const uint32_t ao_radio_cal;
+
+#define FOSC 26000000
+
+#define ao_radio_select() ao_spi_get_mask(AO_CC115L_SPI_CS_PORT,(1 << AO_CC115L_SPI_CS_PIN),AO_CC115L_SPI_BUS,AO_SPI_SPEED_4MHz)
+#define ao_radio_deselect() ao_spi_put_mask(AO_CC115L_SPI_CS_PORT,(1 << AO_CC115L_SPI_CS_PIN),AO_CC115L_SPI_BUS)
+#define ao_radio_spi_send(d,l) ao_spi_send((d), (l), AO_CC115L_SPI_BUS)
+#define ao_radio_spi_send_fixed(d,l) ao_spi_send_fixed((d), (l), AO_CC115L_SPI_BUS)
+#define ao_radio_spi_recv(d,l) ao_spi_recv((d), (l), AO_CC115L_SPI_BUS)
+#define ao_radio_duplex(o,i,l) ao_spi_duplex((o), (i), (l), AO_CC115L_SPI_BUS)
+
+static uint8_t
+ao_radio_reg_read(uint16_t addr)
+{
+ uint8_t datao[2], datai[2];
+ uint8_t d;
+
+#if CC115L_TRACE
+ printf("\t\tao_radio_reg_read (%04x): ", addr); flush();
+#endif
+ datao[0] = ((1 << CC115L_READ) |
+ (0 << CC115L_BURST) |
+ addr);
+ ao_radio_select();
+ ao_radio_duplex(datao, datai, 2);
+ ao_radio_deselect();
+#if CC115L_TRACE
+ printf (" %02x\n", datai[1]);
+#endif
+ return datai[1];
+}
+
+static void
+ao_radio_reg_write(uint16_t addr, uint8_t value)
+{
+ uint8_t data[2];
+ uint8_t d;
+
+#if CC115L_TRACE
+ printf("\t\tao_radio_reg_write (%04x): %02x\n", addr, value);
+#endif
+ data[0] = ((0 << CC115L_READ) |
+ (0 << CC115L_BURST) |
+ addr);
+ data[1] = value;
+ ao_radio_select();
+ ao_radio_spi_send(data, 2);
+ ao_radio_deselect();
+}
+
+static void
+ao_radio_burst_read_start (uint16_t addr)
+{
+ uint8_t data[1];
+ uint8_t d;
+
+ data[0] = ((1 << CC115L_READ) |
+ (1 << CC115L_BURST) |
+ addr);
+ ao_radio_select();
+ ao_radio_spi_send(data, 1);
+}
+
+static void
+ao_radio_burst_read_stop (void)
+{
+ ao_radio_deselect();
+}
+
+
+static uint8_t
+ao_radio_strobe(uint8_t addr)
+{
+ uint8_t in;
+
+#if CC115L_TRACE
+ printf("\t\tao_radio_strobe (%02x): ", addr); flush();
+#endif
+ ao_radio_select();
+ ao_radio_duplex(&addr, &in, 1);
+ ao_radio_deselect();
+#if CC115L_TRACE
+ printf("%02x\n", in); flush();
+#endif
+ return in;
+}
+
+static uint8_t
+ao_radio_fifo_write_start(void)
+{
+ uint8_t addr = ((0 << CC115L_READ) |
+ (1 << CC115L_BURST) |
+ CC115L_FIFO);
+ uint8_t status;
+
+ ao_radio_select();
+ ao_radio_duplex(&addr, &status, 1);
+ return status;
+}
+
+static inline uint8_t ao_radio_fifo_write_stop(uint8_t status) {
+ ao_radio_deselect();
+ return status;
+}
+
+static uint8_t
+ao_radio_fifo_write(uint8_t *data, uint8_t len)
+{
+ uint8_t status = ao_radio_fifo_write_start();
+ ao_radio_spi_send(data, len);
+ return ao_radio_fifo_write_stop(status);
+}
+
+static uint8_t
+ao_radio_fifo_write_fixed(uint8_t data, uint8_t len)
+{
+ uint8_t status = ao_radio_fifo_write_start();
+ ao_radio_spi_send_fixed(data, len);
+ return ao_radio_fifo_write_stop(status);
+}
+
+static uint8_t
+ao_radio_tx_fifo_space(void)
+{
+ return CC115L_FIFO_SIZE - (ao_radio_reg_read(CC115L_TXBYTES) & CC115L_TXBYTES_NUM_TX_BYTES_MASK);
+}
+
+static uint8_t
+ao_radio_status(void)
+{
+ return ao_radio_strobe (CC115L_SNOP);
+}
+
+#define ao_radio_rdf_value 0x55
+
+static uint8_t
+ao_radio_get_marcstate(void)
+{
+ return ao_radio_reg_read(CC115L_MARCSTATE) & CC115L_MARCSTATE_MASK;
+}
+
+static void
+ao_radio_mcu_wakeup_isr(void)
+{
+ ao_radio_mcu_wake = 1;
+ ao_wakeup(&ao_radio_wake);
+}
+
+
+static void
+ao_radio_check_marcstate(void)
+{
+ ao_radio_mcu_wake = 0;
+ ao_radio_marcstate = ao_radio_get_marcstate();
+
+ /* Anyt other than 'tx finished' means an error occurred */
+ if (ao_radio_marcstate != CC115L_MARCSTATE_TX_END)
+ ao_radio_abort = 1;
+}
+
+static void
+ao_radio_isr(void)
+{
+ ao_exti_disable(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN);
+ ao_radio_wake = 1;
+ ao_wakeup(&ao_radio_wake);
+}
+
+static void
+ao_radio_start_tx(void)
+{
+ ao_exti_set_callback(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN, ao_radio_isr);
+ ao_exti_enable(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN);
+ ao_exti_enable(AO_CC115L_MCU_WAKEUP_PORT, AO_CC115L_MCU_WAKEUP_PIN);
+ ao_radio_strobe(CC115L_STX);
+}
+
+static void
+ao_radio_idle(void)
+{
+ for (;;) {
+ uint8_t state = ao_radio_strobe(CC115L_SIDLE);
+ if ((state >> CC115L_STATUS_STATE) == CC115L_STATUS_STATE_IDLE)
+ break;
+ }
+ /* Flush any pending TX bytes */
+ ao_radio_strobe(CC115L_SFTX);
+}
+
+/*
+ * Packet deviation is 20.5kHz
+ *
+ * fdev = fosc >> 17 * (8 + dev_m) << dev_e
+ *
+ * 26e6 / (2 ** 17) * (8 + 5) * (2 ** 3) = 20630Hz
+ */
+
+#define PACKET_DEV_E 3
+#define PACKET_DEV_M 5
+
+/*
+ * For our packet data, set the symbol rate to 38400 Baud
+ *
+ * (256 + DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 28
+ *
+ * (256 + 131) * (2 ** 10) / (2**28) * 26e6 = 38383
+ *
+ * DATARATE_M = 131
+ * DATARATE_E = 10
+ */
+#define PACKET_DRATE_E 10
+#define PACKET_DRATE_M 131
+
+static const uint16_t packet_setup[] = {
+ CC115L_DEVIATN, ((PACKET_DEV_E << CC115L_DEVIATN_DEVIATION_E) |
+ (PACKET_DEV_M << CC115L_DEVIATN_DEVIATION_M)),
+ CC115L_MDMCFG4, ((0xf << 4) |
+ (PACKET_DRATE_E << CC115L_MDMCFG4_DRATE_E)),
+ CC115L_MDMCFG3, (PACKET_DRATE_M),
+};
+
+
+/*
+ * RDF deviation is 5kHz
+ *
+ * fdev = fosc >> 17 * (8 + dev_m) << dev_e
+ *
+ * 26e6 / (2 ** 17) * (8 + 4) * (2 ** 1) = 4761Hz
+ */
+
+#define RDF_DEV_E 1
+#define RDF_DEV_M 4
+
+/*
+ * For our RDF beacon, set the symbol rate to 2kBaud (for a 1kHz tone)
+ *
+ * (256 + DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 28
+ *
+ * (256 + 67) * (2 ** 6) / (2**28) * 26e6 = 2002
+ *
+ * DATARATE_M = 67
+ * DATARATE_E = 6
+ *
+ * To make the tone last for 200ms, we need 2000 * .2 = 400 bits or 50 bytes
+ */
+#define RDF_DRATE_E 6
+#define RDF_DRATE_M 67
+#define RDF_PACKET_LEN 50
+
+static const uint16_t rdf_setup[] = {
+ CC115L_DEVIATN, ((RDF_DEV_E << CC115L_DEVIATN_DEVIATION_E) |
+ (RDF_DEV_M << CC115L_DEVIATN_DEVIATION_M)),
+ CC115L_MDMCFG4, ((0xf << 4) |
+ (RDF_DRATE_E << CC115L_MDMCFG4_DRATE_E)),
+ CC115L_MDMCFG3, (RDF_DRATE_M),
+};
+
+/*
+ * APRS deviation is the same as RDF
+ */
+
+#define APRS_DEV_E RDF_DEV_E
+#define APRS_DEV_M RDF_DEV_E
+
+/*
+ * For our APRS beacon, set the symbol rate to 9.6kBaud (8x oversampling for 1200 baud data rate)
+ *
+ * (256 + DATARATE_M) * 2 ** DATARATE_E
+ * Rdata = -------------------------------------- * fosc
+ * 2 ** 28
+ *
+ * (256 + 131) * (2 ** 8) / (2**28) * 26e6 = 9596
+ *
+ * DATARATE_M = 131
+ * DATARATE_E = 8
+ *
+ */
+#define APRS_DRATE_E 8
+#define APRS_DRATE_M 131
+
+static const uint16_t aprs_setup[] = {
+ CC115L_DEVIATN, ((APRS_DEV_E << CC115L_DEVIATN_DEVIATION_E) |
+ (APRS_DEV_M << CC115L_DEVIATN_DEVIATION_M)),
+ CC115L_MDMCFG4, ((0xf << 4) |
+ (APRS_DRATE_E << CC115L_MDMCFG4_DRATE_E)),
+ CC115L_MDMCFG3, (APRS_DRATE_M),
+};
+
+#define AO_PKTCTRL0_INFINITE ((CC115L_PKTCTRL0_PKT_FORMAT_NORMAL << CC115L_PKTCTRL0_PKT_FORMAT) | \
+ (0 << CC115L_PKTCTRL0_PKT_CRC_EN) | \
+ (CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_INFINITE << CC115L_PKTCTRL0_PKT_LENGTH_CONFIG))
+#define AO_PKTCTRL0_FIXED ((CC115L_PKTCTRL0_PKT_FORMAT_NORMAL << CC115L_PKTCTRL0_PKT_FORMAT) | \
+ (0 << CC115L_PKTCTRL0_PKT_CRC_EN) | \
+ (CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_FIXED << CC115L_PKTCTRL0_PKT_LENGTH_CONFIG))
+
+static uint16_t ao_radio_mode;
+
+#define AO_RADIO_MODE_BITS_PACKET_TX 1
+#define AO_RADIO_MODE_BITS_TX_BUF 2
+#define AO_RADIO_MODE_BITS_TX_FINISH 4
+#define AO_RADIO_MODE_BITS_RDF 8
+#define AO_RADIO_MODE_BITS_APRS 16
+#define AO_RADIO_MODE_BITS_INFINITE 32
+#define AO_RADIO_MODE_BITS_FIXED 64
+
+#define AO_RADIO_MODE_NONE 0
+#define AO_RADIO_MODE_PACKET_TX_BUF (AO_RADIO_MODE_BITS_PACKET_TX | AO_RADIO_MODE_BITS_TX_BUF)
+#define AO_RADIO_MODE_PACKET_TX_FINISH (AO_RADIO_MODE_BITS_PACKET_TX | AO_RADIO_MODE_BITS_TX_FINISH)
+#define AO_RADIO_MODE_RDF (AO_RADIO_MODE_BITS_RDF | AO_RADIO_MODE_BITS_TX_FINISH)
+#define AO_RADIO_MODE_APRS_BUF (AO_RADIO_MODE_BITS_APRS | AO_RADIO_MODE_BITS_INFINITE | AO_RADIO_MODE_BITS_TX_BUF)
+#define AO_RADIO_MODE_APRS_LAST_BUF (AO_RADIO_MODE_BITS_APRS | AO_RADIO_MODE_BITS_FIXED | AO_RADIO_MODE_BITS_TX_BUF)
+#define AO_RADIO_MODE_APRS_FINISH (AO_RADIO_MODE_BITS_APRS | AO_RADIO_MODE_BITS_FIXED | AO_RADIO_MODE_BITS_TX_FINISH)
+
+static void
+ao_radio_set_mode(uint16_t new_mode)
+{
+ uint16_t changes;
+ int i;
+
+ if (new_mode == ao_radio_mode)
+ return;
+
+ changes = new_mode & (~ao_radio_mode);
+ if (changes & AO_RADIO_MODE_BITS_PACKET_TX)
+ for (i = 0; i < sizeof (packet_setup) / sizeof (packet_setup[0]); i += 2)
+ ao_radio_reg_write(packet_setup[i], packet_setup[i+1]);
+
+ if (changes & AO_RADIO_MODE_BITS_TX_BUF)
+ ao_radio_reg_write(AO_CC115L_INT_GPIO_IOCFG, CC115L_IOCFG_GPIO_CFG_TXFIFO_THR);
+
+ if (changes & AO_RADIO_MODE_BITS_TX_FINISH)
+ ao_radio_reg_write(AO_CC115L_INT_GPIO_IOCFG, CC115L_IOCFG_GPIO_CFG_PKT_SYNC_TX | (1 << CC115L_IOCFG_GPIO_INV));
+
+ if (changes & AO_RADIO_MODE_BITS_RDF)
+ for (i = 0; i < sizeof (rdf_setup) / sizeof (rdf_setup[0]); i += 2)
+ ao_radio_reg_write(rdf_setup[i], rdf_setup[i+1]);
+
+ if (changes & AO_RADIO_MODE_BITS_APRS)
+ for (i = 0; i < sizeof (aprs_setup) / sizeof (aprs_setup[0]); i += 2)
+ ao_radio_reg_write(aprs_setup[i], aprs_setup[i+1]);
+
+ if (changes & AO_RADIO_MODE_BITS_INFINITE)
+ ao_radio_reg_write(CC115L_PKTCTRL0, AO_PKTCTRL0_INFINITE);
+
+ if (changes & AO_RADIO_MODE_BITS_FIXED)
+ ao_radio_reg_write(CC115L_PKTCTRL0, AO_PKTCTRL0_FIXED);
+
+ ao_radio_mode = new_mode;
+}
+
+static const uint16_t radio_setup[] = {
+#include "ao_rf_cc115l.h"
+};
+
+static uint8_t ao_radio_configured = 0;
+
+static void
+ao_radio_setup(void)
+{
+ int i;
+
+ ao_radio_strobe(CC115L_SRES);
+
+ for (i = 0; i < sizeof (radio_setup) / sizeof (radio_setup[0]); i += 2)
+ ao_radio_reg_write(radio_setup[i], radio_setup[i+1]);
+
+ ao_radio_mode = 0;
+
+ ao_config_get();
+
+ ao_radio_configured = 1;
+}
+
+static void
+ao_radio_set_len(uint8_t len)
+{
+ static uint8_t last_len;
+
+ if (len != last_len) {
+ ao_radio_reg_write(CC115L_PKTLEN, len);
+ last_len = len;
+ }
+}
+
+static void
+ao_radio_get(uint8_t len)
+{
+ static uint32_t last_radio_setting;
+
+ ao_mutex_get(&ao_radio_mutex);
+ if (!ao_radio_configured)
+ ao_radio_setup();
+ if (ao_config.radio_setting != last_radio_setting) {
+ ao_radio_reg_write(CC115L_FREQ2, ao_config.radio_setting >> 16);
+ ao_radio_reg_write(CC115L_FREQ1, ao_config.radio_setting >> 8);
+ ao_radio_reg_write(CC115L_FREQ0, ao_config.radio_setting);
+ last_radio_setting = ao_config.radio_setting;
+ }
+ ao_radio_set_len(len);
+}
+
+#define ao_radio_put() ao_mutex_put(&ao_radio_mutex)
+
+static void
+ao_rdf_start(uint8_t len)
+{
+ ao_radio_abort = 0;
+ ao_radio_get(len);
+
+ ao_radio_set_mode(AO_RADIO_MODE_RDF);
+ ao_radio_wake = 0;
+
+}
+
+static void
+ao_rdf_run(void)
+{
+ ao_radio_start_tx();
+
+ ao_arch_block_interrupts();
+ while (!ao_radio_wake && !ao_radio_abort && !ao_radio_mcu_wake)
+ ao_sleep(&ao_radio_wake);
+ ao_arch_release_interrupts();
+ if (ao_radio_mcu_wake)
+ ao_radio_check_marcstate();
+ if (!ao_radio_wake)
+ ao_radio_idle();
+ ao_radio_put();
+}
+
+void
+ao_radio_rdf(void)
+{
+ ao_rdf_start(AO_RADIO_RDF_LEN);
+
+ ao_radio_fifo_write_fixed(ao_radio_rdf_value, AO_RADIO_RDF_LEN);
+
+ ao_rdf_run();
+}
+
+void
+ao_radio_continuity(uint8_t c)
+{
+ uint8_t i;
+ uint8_t status;
+
+ ao_rdf_start(AO_RADIO_CONT_TOTAL_LEN);
+
+ status = ao_radio_fifo_write_start();
+ for (i = 0; i < 3; i++) {
+ ao_radio_spi_send_fixed(0x00, AO_RADIO_CONT_PAUSE_LEN);
+ if (i < c)
+ ao_radio_spi_send_fixed(ao_radio_rdf_value, AO_RADIO_CONT_TONE_LEN);
+ else
+ ao_radio_spi_send_fixed(0x00, AO_RADIO_CONT_TONE_LEN);
+ }
+ ao_radio_spi_send_fixed(0x00, AO_RADIO_CONT_PAUSE_LEN);
+ status = ao_radio_fifo_write_stop(status);
+ (void) status;
+ ao_rdf_run();
+}
+
+void
+ao_radio_rdf_abort(void)
+{
+ ao_radio_abort = 1;
+ ao_wakeup(&ao_radio_wake);
+}
+
+static void
+ao_radio_test_cmd(void)
+{
+ uint8_t mode = 2;
+ static uint8_t radio_on;
+ ao_cmd_white();
+ if (ao_cmd_lex_c != '\n') {
+ ao_cmd_decimal();
+ mode = (uint8_t) ao_cmd_lex_u32;
+ }
+ mode++;
+ if ((mode & 2) && !radio_on) {
+#if HAS_MONITOR
+ ao_monitor_disable();
+#endif
+#if PACKET_HAS_SLAVE
+ ao_packet_slave_stop();
+#endif
+ ao_radio_get(0xff);
+ ao_radio_strobe(CC115L_STX);
+#if CC115L_TRACE
+ { int t;
+ for (t = 0; t < 10; t++) {
+ printf ("status: %02x\n", ao_radio_status());
+ ao_delay(AO_MS_TO_TICKS(100));
+ }
+ }
+#endif
+ radio_on = 1;
+ }
+ if (mode == 3) {
+ printf ("Hit a character to stop..."); flush();
+ getchar();
+ putchar('\n');
+ }
+ if ((mode & 1) && radio_on) {
+ ao_radio_idle();
+ ao_radio_put();
+ radio_on = 0;
+#if HAS_MONITOR
+ ao_monitor_enable();
+#endif
+ }
+}
+
+static void
+ao_radio_wait_isr(void)
+{
+ ao_arch_block_interrupts();
+ while (!ao_radio_wake && !ao_radio_mcu_wake && !ao_radio_abort)
+ ao_sleep(&ao_radio_wake);
+ ao_arch_release_interrupts();
+ if (ao_radio_mcu_wake)
+ ao_radio_check_marcstate();
+}
+
+static uint8_t
+ao_radio_wait_tx(uint8_t wait_fifo)
+{
+ uint8_t fifo_space = 0;
+
+ do {
+ ao_radio_wait_isr();
+ if (!wait_fifo)
+ return 0;
+ fifo_space = ao_radio_tx_fifo_space();
+ } while (!fifo_space && !ao_radio_abort);
+ return fifo_space;
+}
+
+static uint8_t tx_data[(AO_RADIO_MAX_SEND + 4) * 2];
+
+void
+ao_radio_send(const void *d, uint8_t size)
+{
+ uint8_t marc_status;
+ uint8_t *e = tx_data;
+ uint8_t encode_len;
+ uint8_t this_len;
+ uint8_t started = 0;
+ uint8_t fifo_space;
+
+ encode_len = ao_fec_encode(d, size, tx_data);
+
+ ao_radio_get(encode_len);
+
+ started = 0;
+ fifo_space = CC115L_FIFO_SIZE;
+ while (encode_len) {
+ this_len = encode_len;
+
+ ao_radio_wake = 0;
+ if (this_len > fifo_space) {
+ this_len = fifo_space;
+ ao_radio_set_mode(AO_RADIO_MODE_PACKET_TX_BUF);
+ } else {
+ ao_radio_set_mode(AO_RADIO_MODE_PACKET_TX_FINISH);
+ }
+
+ ao_radio_fifo_write(e, this_len);
+ e += this_len;
+ encode_len -= this_len;
+
+ if (!started) {
+ ao_radio_start_tx();
+ started = 1;
+ } else {
+ ao_exti_enable(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN);
+ }
+
+ fifo_space = ao_radio_wait_tx(encode_len != 0);
+ if (ao_radio_abort) {
+ ao_radio_idle();
+ break;
+ }
+ }
+ ao_radio_put();
+}
+
+#define AO_RADIO_LOTS 64
+
+void
+ao_radio_send_lots(ao_radio_fill_func fill)
+{
+ uint8_t buf[AO_RADIO_LOTS], *b;
+ int cnt;
+ int total = 0;
+ uint8_t done = 0;
+ uint8_t started = 0;
+ uint8_t fifo_space;
+
+ ao_radio_get(0xff);
+ fifo_space = CC115L_FIFO_SIZE;
+ while (!done) {
+ cnt = (*fill)(buf, sizeof(buf));
+ if (cnt < 0) {
+ done = 1;
+ cnt = -cnt;
+ }
+ total += cnt;
+
+ /* At the last buffer, set the total length */
+ if (done)
+ ao_radio_set_len(total & 0xff);
+
+ b = buf;
+ while (cnt) {
+ uint8_t this_len = cnt;
+
+ /* Wait for some space in the fifo */
+ while (!ao_radio_abort && (fifo_space = ao_radio_tx_fifo_space()) == 0) {
+ ao_radio_wake = 0;
+ ao_radio_wait_isr();
+ }
+ if (ao_radio_abort)
+ break;
+ if (this_len > fifo_space)
+ this_len = fifo_space;
+
+ cnt -= this_len;
+
+ if (done) {
+ if (cnt)
+ ao_radio_set_mode(AO_RADIO_MODE_APRS_LAST_BUF);
+ else
+ ao_radio_set_mode(AO_RADIO_MODE_APRS_FINISH);
+ } else
+ ao_radio_set_mode(AO_RADIO_MODE_APRS_BUF);
+
+ ao_radio_fifo_write(b, this_len);
+ b += this_len;
+
+ if (!started) {
+ ao_radio_start_tx();
+ started = 1;
+ } else
+ ao_exti_enable(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN);
+ }
+ if (ao_radio_abort) {
+ ao_radio_idle();
+ break;
+ }
+ /* Wait for the transmitter to go idle */
+ ao_radio_wake = 0;
+ ao_radio_wait_isr();
+ }
+ ao_radio_put();
+}
+
+static char *cc115l_state_name[] = {
+ [CC115L_STATUS_STATE_IDLE] = "IDLE",
+ [CC115L_STATUS_STATE_TX] = "TX",
+ [CC115L_STATUS_STATE_FSTXON] = "FSTXON",
+ [CC115L_STATUS_STATE_CALIBRATE] = "CALIBRATE",
+ [CC115L_STATUS_STATE_SETTLING] = "SETTLING",
+ [CC115L_STATUS_STATE_TX_FIFO_UNDERFLOW] = "TX_FIFO_UNDERFLOW",
+};
+
+static void ao_radio_show(void) {
+ uint8_t status = ao_radio_status();
+ int i;
+
+ ao_radio_get(0xff);
+ status = ao_radio_status();
+ printf ("Status: %02x\n", status);
+ printf ("CHIP_RDY: %d\n", (status >> CC115L_STATUS_CHIP_RDY) & 1);
+ printf ("STATE: %s\n", cc115l_state_name[(status >> CC115L_STATUS_STATE) & CC115L_STATUS_STATE_MASK]);
+ printf ("MARC: %02x\n", ao_radio_get_marcstate());
+
+ ao_radio_put();
+}
+
+static void ao_radio_beep(void) {
+ ao_radio_rdf();
+}
+
+static void ao_radio_packet(void) {
+ static const uint8_t packet[] = {
+#if 1
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+#else
+ 3, 1, 2, 3
+#endif
+ };
+
+ ao_radio_send(packet, sizeof (packet));
+}
+
+#if HAS_APRS
+#include <ao_aprs.h>
+
+static void
+ao_radio_aprs()
+{
+ ao_packet_slave_stop();
+ ao_aprs_send();
+}
+#endif
+
+static const struct ao_cmds ao_radio_cmds[] = {
+ { ao_radio_test_cmd, "C <1 start, 0 stop, none both>\0Radio carrier test" },
+#if CC115L_DEBUG
+#if HAS_APRS
+ { ao_radio_aprs, "G\0Send APRS packet" },
+#endif
+ { ao_radio_show, "R\0Show CC115L status" },
+ { ao_radio_beep, "b\0Emit an RDF beacon" },
+ { ao_radio_packet, "p\0Send a test packet" },
+#endif
+ { 0, NULL }
+};
+
+void
+ao_radio_init(void)
+{
+ int i;
+
+ ao_radio_configured = 0;
+ ao_spi_init_cs (AO_CC115L_SPI_CS_PORT, (1 << AO_CC115L_SPI_CS_PIN));
+
+#if 0
+ AO_CC115L_SPI_CS_PORT->bsrr = ((uint32_t) (1 << AO_CC115L_SPI_CS_PIN));
+ for (i = 0; i < 10000; i++) {
+ if ((SPI_2_PORT->idr & (1 << SPI_2_MISO_PIN)) == 0)
+ break;
+ }
+ AO_CC115L_SPI_CS_PORT->bsrr = (1 << AO_CC115L_SPI_CS_PIN);
+ if (i == 10000)
+ ao_panic(AO_PANIC_SELF_TEST_CC115L);
+#endif
+
+ /* Enable the EXTI interrupt for the appropriate pin */
+ ao_enable_port(AO_CC115L_INT_PORT);
+ ao_exti_setup(AO_CC115L_INT_PORT, AO_CC115L_INT_PIN,
+ AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_HIGH,
+ ao_radio_isr);
+
+ /* Enable the hacked up GPIO3 pin */
+ ao_enable_port(AO_CC115L_MCU_WAKEUP_PORT);
+ ao_exti_setup(AO_CC115L_MCU_WAKEUP_PORT, AO_CC115L_MCU_WAKEUP_PIN,
+ AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_MED,
+ ao_radio_mcu_wakeup_isr);
+
+ ao_cmd_register(&ao_radio_cmds[0]);
+}
--- /dev/null
+/*
+ * Copyright © 2013 Keith Packard <keithp@keithp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#ifndef _AO_CC115L_H_
+#define _AO_CC115L_H_
+
+#define CC115L_BURST 6
+#define CC115L_READ 7
+
+/* Register space */
+#define CC115L_IOCFG2 0x00 /* GDO2 Output Pin Configuration */
+#define CC115L_IOCFG1 0x01 /* GDO1 Output Pin Configuration */
+#define CC115L_IOCFG0 0x02 /* GDO0 Output Pin Configuration */
+
+#define CC115L_IOCFG_GPIO1_DS 7
+#define CC115L_IOCFG_GPIO_INV 6
+
+#define CC115L_IOCFG_GPIO_CFG 0
+#define CC115L_IOCFG_GPIO_CFG_TXFIFO_THR 2
+#define CC115L_IOCFG_GPIO_CFG_TXFIFO_THR_PKT 3
+#define CC115L_IOCFG_GPIO_CFG_TXFIFO_UNDERFLOW 5
+#define CC115L_IOCFG_GPIO_CFG_PKT_SYNC_TX 6
+#define CC115L_IOCFG_GPIO_CFG_PLL_LOCKED 10
+#define CC115L_IOCFG_GPIO_CFG_SERIAL_CLK 11
+#define CC115L_IOCFG_GPIO_CFG_SYNC_DATA 12
+#define CC115L_IOCFG_GPIO_CFG_ASYNC_DATA 13
+#define CC115L_IOCFG_GPIO_CFG_PA_PD 27
+#define CC115L_IOCFG_GPIO_CFG_CHIP_RDYn 41
+#define CC115L_IOCFG_GPIO_CFG_XOSC_STABLE 43
+#define CC115L_IOCFG_GPIO_CFG_HIGHZ 46
+#define CC115L_IOCFG_GPIO_CFG_HW_0 47
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_1 48
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_1_5 49
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_2 50
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_3 51
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_4 52
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_6 53
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_8 54
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_12 55
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_16 56
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_24 57
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_32 58
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_48 59
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_64 60
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_96 61
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_128 62
+#define CC115L_IOCFG_GPIO_CFG_CLK_XOSC_192 63
+#define CC115L_IOCFG_GPIO_CFG_MASK 0x3f
+
+#define CC115L_FIFOTHR 0x03 /* TX FIFO Thresholds */
+#define CC115L_FIFOTHR_THR_MASK 0x0f
+#define CC115L_FIFOTHR_THR_61 0
+#define CC115L_FIFOTHR_THR_57 1
+#define CC115L_FIFOTHR_THR_53 2
+#define CC115L_FIFOTHR_THR_49 3
+#define CC115L_FIFOTHR_THR_45 4
+#define CC115L_FIFOTHR_THR_41 5
+#define CC115L_FIFOTHR_THR_37 6
+#define CC115L_FIFOTHR_THR_33 7
+#define CC115L_FIFOTHR_THR_29 8
+#define CC115L_FIFOTHR_THR_25 9
+#define CC115L_FIFOTHR_THR_21 10
+#define CC115L_FIFOTHR_THR_17 11
+#define CC115L_FIFOTHR_THR_13 12
+#define CC115L_FIFOTHR_THR_9 13
+#define CC115L_FIFOTHR_THR_5 14
+#define CC115L_FIFOTHR_THR_1 15
+
+#define CC115L_SYNC1 0x04 /* Sync Word, High Byte */
+#define CC115L_SYNC0 0x05 /* Sync Word, Low Byte */
+#define CC115L_PKTLEN 0x06 /* Packet Length */
+#define CC115L_PKTCTRL0 0x08 /* Packet Automation Control */
+#define CC115L_PKTCTRL0_PKT_FORMAT 4
+#define CC115L_PKTCTRL0_PKT_FORMAT_NORMAL 0
+#define CC115L_PKTCTRL0_PKT_FORMAT_SYNC_SERIAL 1
+#define CC115L_PKTCTRL0_PKT_FORMAT_RANDOM 2
+#define CC115L_PKTCTRL0_PKT_FORMAT_ASYNC_SERIAL 3
+#define CC115L_PKTCTRL0_PKT_FORMAT_MASK 3
+#define CC115L_PKTCTRL0_PKT_CRC_EN 2
+#define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG 0
+#define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_FIXED 0
+#define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_VARIABLE 1
+#define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_INFINITE 2
+#define CC115L_PKTCTRL0_PKT_LENGTH_CONFIG_MASK 3
+#define CC115L_CHANNR 0x0a /* Channel Number */
+#define CC115L_FSCTRL0 0x0c /* Frequency Synthesizer Control */
+#define CC115L_FREQ2 0x0d /* Frequency Control Word, High Byte */
+#define CC115L_FREQ1 0x0e /* Frequency Control Word, Middle Byte */
+#define CC115L_FREQ0 0x0f /* Frequency Control Word, Low Byte */
+#define CC115L_MDMCFG4 0x10 /* Modem Configuration */
+#define CC115L_MDMCFG4_DRATE_E 0
+#define CC115L_MDMCFG3 0x11 /* Modem Configuration */
+#define CC115L_MDMCFG2 0x12 /* Modem Configuration */
+#define CC115L_MDMCFG2_MOD_FORMAT 4
+#define CC115L_MDMCFG2_MOD_FORMAT_2FSK 0
+#define CC115L_MDMCFG2_MOD_FORMAT_GFSK 1
+#define CC115L_MDMCFG2_MOD_FORMAT_OOK 3
+#define CC115L_MDMCFG2_MOD_FORMAT_4FSK 4
+#define CC115L_MDMCFG2_MOD_FORMAT_MASK 7
+#define CC115L_MDMCFG2_MANCHESTER_EN 3
+#define CC115L_MDMCFG2_SYNC_MODE 0
+#define CC115L_MDMCFG2_SYNC_MODE_NONE 0
+#define CC115L_MDMCFG2_SYNC_MODE_16BITS 1
+#define CC115L_MDMCFG2_SYNC_MODE_32BITS 3
+#define CC115L_MDMCFG2_SYNC_MODE_MASK 3
+#define CC115L_MDMCFG1 0x13 /* Modem Configuration */
+#define CC115L_MDMCFG1_NUM_PREAMBLE 4
+#define CC115L_MDMCFG1_NUM_PREAMBLE_2 0
+#define CC115L_MDMCFG1_NUM_PREAMBLE_3 1
+#define CC115L_MDMCFG1_NUM_PREAMBLE_4 2
+#define CC115L_MDMCFG1_NUM_PREAMBLE_6 3
+#define CC115L_MDMCFG1_NUM_PREAMBLE_8 4
+#define CC115L_MDMCFG1_NUM_PREAMBLE_12 5
+#define CC115L_MDMCFG1_NUM_PREAMBLE_16 6
+#define CC115L_MDMCFG1_NUM_PREAMBLE_24 7
+#define CC115L_MDMCFG1_NUM_PREAMBLE_MASK 7
+#define CC115L_MDMCFG1_CHANSPC_E 0
+#define CC115L_MDMCFG0 0x14 /* Modem Configuration */
+#define CC115L_DEVIATN 0x15 /* Modem Deviation Setting */
+#define CC115L_DEVIATN_DEVIATION_E 4
+#define CC115L_DEVIATN_DEVIATION_E_MASK 7
+#define CC115L_DEVIATN_DEVIATION_M 0
+#define CC115L_DEVIATN_DEVIATION_M_MASK 7
+#define CC115L_MCSM1 0x17 /* Main Radio Control State Machine Configuration */
+#define CC115L_MCSM1_TXOFF_MODE 0
+#define CC115L_MCSM1_TXOFF_MODE_IDLE 0
+#define CC115L_MCSM1_TXOFF_MODE_FSTXON 1
+#define CC115L_MCSM1_TXOFF_MODE_TX 2
+#define CC115L_MCSM1_TXOFF_MODE_MASK 3
+#define CC115L_MCSM0 0x18 /* Main Radio Control State Machine Configuration */
+#define CC115L_MCSM0_FS_AUTOCAL 4
+#define CC115L_MCSM0_FS_AUTOCAL_NEVER 0
+#define CC115L_MCSM0_FS_AUTOCAL_IDLE_TO_TX 1
+#define CC115L_MCSM0_FS_AUTOCAL_TX_TO_IDLE 2
+#define CC115L_MCSM0_FS_AUTOCAL_4TH_TX_TO_IDLE 3
+#define CC115L_MCSM0_FS_AUTOCAL_MASK 3
+#define CC115L_MCSM0_PO_TIMEOUT 2
+#define CC115L_MCSM0_PO_TIMEOUT_1 0
+#define CC115L_MCSM0_PO_TIMEOUT_16 1
+#define CC115L_MCSM0_PO_TIMEOUT_64 2
+#define CC115L_MCSM0_PO_TIMEOUT_256 3
+#define CC115L_MCSM0_PO_TIMEOUT_MASK 3
+#define CC115L_MCSM0_XOSC_FORCE_ON 0
+#define CC115L_RESERVED_0X20 0x20 /* Use setting from SmartRF Studio */
+#define CC115L_FREND0 0x22 /* Front End TX Configuration */
+#define CC115L_FSCAL3 0x23 /* Frequency Synthesizer Calibration */
+#define CC115L_FSCAL2 0x24 /* Frequency Synthesizer Calibration */
+#define CC115L_FSCAL1 0x25 /* Frequency Synthesizer Calibration */
+#define CC115L_FSCAL0 0x26 /* Frequency Synthesizer Calibration */
+#define CC115L_RESERVED_0X29 0x29 /* Use setting from SmartRF Studio */
+#define CC115L_RESERVED_0X2A 0x2a /* Use setting from SmartRF Studio */
+#define CC115L_RESERVED_0X2B 0x2b /* Use setting from SmartRF Studio */
+#define CC115L_TEST2 0x2c /* Various Test Settings */
+#define CC115L_TEST1 0x2d /* Various Test Settings */
+#define CC115L_TEST0 0x2e /* Various Test Settings */
+
+/* Status registers (use BURST bit to select these) */
+#define CC115L_PARTNUM (0x30|(1<<CC115L_BURST)) /* Part number for CC115L */
+#define CC115L_VERSION (0x31|(1<<CC115L_BURST)) /* Current version number */
+#define CC115L_MARCSTATE (0x35|(1<<CC115L_BURST)) /* Control state machine state */
+#define CC115L_MARCSTATE_MASK 0x1f
+#define CC115L_MARCSTATE_SLEEP 0x00
+#define CC115L_MARCSTATE_IDLE 0x01
+#define CC115L_MARCSTATE_XOFF 0x02
+#define CC115L_MARCSTATE_VCOON_MC 0x03
+#define CC115L_MARCSTATE_REGON_MC 0x04
+#define CC115L_MARCSTATE_MANCAL 0x05
+#define CC115L_MARCSTATE_VCOON 0x06
+#define CC115L_MARCSTATE_REGON 0x07
+#define CC115L_MARCSTATE_STARTCAL 0x08
+#define CC115L_MARCSTATE_BWBOOST 0x09
+#define CC115L_MARCSTATE_FS_LOCK 0x0a
+#define CC115L_MARCSTATE_ENDCAL 0x0c
+#define CC115L_MARCSTATE_FSTXON 0x12
+#define CC115L_MARCSTATE_TX 0x13
+#define CC115L_MARCSTATE_TX_END 0x14
+#define CC115L_MARCSTATE_TX_UNDERFLOW 0x16
+#define CC115L_PKTSTATUS (0x38|(1<<CC115L_BURST)) /* Current GDOx status and packet status */
+#define CC115L_TXBYTES (0x3a|(1<<CC115L_BURST)) /* Underflow and number of bytes in the TX FIFO */
+#define CC115L_TXBYTES_TXFIFO_UNDERFLOW 7
+#define CC115L_TXBYTES_NUM_TX_BYTES 0
+#define CC115L_TXBYTES_NUM_TX_BYTES_MASK 0x7f
+
+/* Command strobes (no BURST bit for these) */
+#define CC115L_SRES 0x30
+#define CC115L_SFSTXON 0x31
+#define CC115L_SXOFF 0x32
+#define CC115L_SCAL 0x33
+#define CC115L_STX 0x35
+#define CC115L_SIDLE 0x36
+#define CC115L_SPWD 0x39
+#define CC115L_SFTX 0x3b
+#define CC115L_SNOP 0x3d
+
+#define CC115L_FIFO 0x3f
+
+#define CC115L_FIFO_SIZE 64
+
+/* Status byte */
+#define CC115L_STATUS_CHIP_RDY 7
+#define CC115L_STATUS_STATE 4
+#define CC115L_STATUS_STATE_IDLE 0
+#define CC115L_STATUS_STATE_TX 2
+#define CC115L_STATUS_STATE_FSTXON 3
+#define CC115L_STATUS_STATE_CALIBRATE 4
+#define CC115L_STATUS_STATE_SETTLING 5
+#define CC115L_STATUS_STATE_TX_FIFO_UNDERFLOW 7
+#define CC115L_STATUS_STATE_MASK 7
+
+#define CC115L_STATUS_FIFO_BYTES_AVAILABLE 0
+#endif /* _AO_CC115L_H_ */
--- /dev/null
+/***************************************************************
+ * SmartRF Studio(tm) Export
+ *
+ * Radio register settings specifed with address, value
+ *
+ * RF device: CC115L
+ *
+ ***************************************************************/
+
+
+ CC115L_IOCFG2, 0x2e, /* GDO2 Output Pin Configuration */
+ CC115L_IOCFG1, 0x2e, /* GDO1 Output Pin Configuration */
+ CC115L_IOCFG0, 0x06, /* GDO0 Output Pin Configuration */
+ CC115L_FIFOTHR, 0x47, /* TX FIFO Thresholds */
+ CC115L_SYNC1, 0xd3, /* Sync Word, High Byte */
+ CC115L_SYNC0, 0x91, /* Sync Word, Low Byte */
+ CC115L_PKTLEN, 0xff, /* Packet Length */
+ CC115L_PKTCTRL0, 0x05, /* Packet Automation Control */
+ CC115L_CHANNR, 0x00, /* Channel number */
+ CC115L_FSCTRL0, 0x00, /* Frequency Synthesizer Control */
+ CC115L_FREQ2, 0x10, /* Frequency Control Word, High Byte */
+ CC115L_FREQ1, 0xb6, /* Frequency Control Word, Middle Byte */
+ CC115L_FREQ0, 0xa5, /* Frequency Control Word, Low Byte */
+ CC115L_MDMCFG4, 0xfa, /* Modem Configuration */
+ CC115L_MDMCFG3, 0x83, /* Modem Configuration */
+ CC115L_MDMCFG2, 0x13, /* Modem Configuration */
+ CC115L_MDMCFG1, 0x21, /* Modem Configuration */
+ CC115L_MDMCFG0, 0xf8, /* Modem Configuration */
+ CC115L_DEVIATN, 0x35, /* Modem Deviation Setting */
+ CC115L_MCSM1, 0x30, /* Main Radio Control State Machine Configuration */
+ CC115L_MCSM0, 0x18, /* Main Radio Control State Machine Configuration */
+ CC115L_RESERVED_0X20, 0xfb, /* Use setting from SmartRF Studio */
+ CC115L_FREND0, 0x10, /* Front End TX Configuration */
+ CC115L_FSCAL3, 0xe9, /* Frequency Synthesizer Calibration */
+ CC115L_FSCAL2, 0x2a, /* Frequency Synthesizer Calibration */
+ CC115L_FSCAL1, 0x00, /* Frequency Synthesizer Calibration */
+ CC115L_FSCAL0, 0x1f, /* Frequency Synthesizer Calibration */
+ CC115L_RESERVED_0X29, 0x89, /* Use setting from SmartRF Studio */
+ CC115L_RESERVED_0X2A, 0x127, /* Use setting from SmartRF Studio */
+ CC115L_RESERVED_0X2B, 0x63, /* Use setting from SmartRF Studio */
+ CC115L_TEST2, 0x81, /* Various Test Settings */
+ CC115L_TEST1, 0x35, /* Various Test Settings */
+ CC115L_TEST0, 0x09, /* Various Test Settings */
+ CC115L_PARTNUM, 0x00, /* Chip ID */
+ CC115L_VERSION, 0x09, /* Chip ID */
+ CC115L_MARCSTATE, 0x00, /* Main Radio Control State Machine State */
+ CC115L_PKTSTATUS, 0x00, /* Current GDOx Status and Packet Status */
+ CC115L_TXBYTES, 0x00, /* Underflow and Number of Bytes */
+
projects / fw / altos / commitdiff