altos: Add STM32F0 beep and SPI byte API.
authorKeith Packard <keithp@keithp.com>
Sat, 2 Jul 2016 18:00:01 +0000 (20:00 +0200)
committerKeith Packard <keithp@keithp.com>
Thu, 14 Jul 2016 22:12:58 +0000 (15:12 -0700)
Signed-off-by: Keith Packard <keithp@keithp.com>
src/stmf0/ao_arch.h
src/stmf0/ao_arch_funcs.h
src/stmf0/ao_spi_stm.c
src/stmf0/stm32f0.h

index 8327725..a36482b 100644 (file)
@@ -115,21 +115,14 @@ extern const uint32_t ao_radio_cal;
 #endif
 
 #define AO_HCLK                (AO_SYSCLK / AO_AHB_PRESCALER)
-#define AO_PCLK1       (AO_HCLK / AO_APB1_PRESCALER)
-#define AO_PCLK2       (AO_HCLK / AO_APB2_PRESCALER)
+#define AO_PCLK                (AO_HCLK / AO_APB_PRESCALER)
 #define AO_SYSTICK     (AO_HCLK)
 #define AO_PANIC_DELAY_SCALE  (AO_SYSCLK / 12000000)
 
-#if AO_APB1_PRESCALER == 1
-#define AO_TIM23467_CLK                AO_PCLK1
+#if AO_APB_PRESCALER == 1
+#define AO_TIM_CLK             AO_PCLK
 #else
-#define AO_TIM23467_CLK                (2 * AO_PCLK1)
-#endif
-
-#if AO_APB2_PRESCALER == 1
-#define AO_TIM91011_CLK                AO_PCLK2
-#else
-#define AO_TIM91011_CLK                (2 * AO_PCLK2)
+#define AO_TIM_CLK             (2 * AO_PCLK)
 #endif
 
 #define AO_STM_NVIC_HIGH_PRIORITY      (0 << 6)
index 01a20c7..8b6234c 100644 (file)
@@ -83,7 +83,57 @@ void
 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
 
 void
-ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
+ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
+
+void
+ao_spi_start_bytes(uint8_t spi_index);
+
+void
+ao_spi_stop_bytes(uint8_t spi_index);
+
+static inline void
+ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
+{
+       struct stm_spi  *stm_spi;
+
+       switch (AO_SPI_INDEX(spi_index)) {
+       case 0:
+               stm_spi = &stm_spi1;
+               break;
+       case 1:
+               stm_spi = &stm_spi2;
+               break;
+       }
+
+       while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+               ;
+       stm_spi->dr = byte;
+       while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+               ;
+       (void) stm_spi->dr;
+}
+
+static inline uint8_t
+ao_spi_recv_byte(uint8_t spi_index)
+{
+       struct stm_spi  *stm_spi;
+
+       switch (AO_SPI_INDEX(spi_index)) {
+       case 0:
+               stm_spi = &stm_spi1;
+               break;
+       case 1:
+               stm_spi = &stm_spi2;
+               break;
+       }
+
+       while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
+               ;
+       stm_spi->dr = 0xff;
+       while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
+               ;
+       return stm_spi->dr;
+}
 
 void
 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
index 4eb4a2d..0448ad8 100644 (file)
@@ -42,8 +42,6 @@ static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
 
 static uint8_t spi_dev_null;
 
-
-
 #define SPI_CR2        ((0 << STM_SPI_CR2_LDMA_TX) |                           \
                 (0 << STM_SPI_CR2_LDMA_RX) |                           \
                 (1 << STM_SPI_CR2_FRXTH) |                             \
@@ -63,12 +61,86 @@ static uint8_t      spi_dev_null;
                         (0 << STM_SPI_CR2_TXDMAEN) |   \
                         (0 << STM_SPI_CR2_RXDMAEN))
 
+#if DEBUG
+static struct {
+       uint8_t task;
+       uint8_t which;
+       AO_TICK_TYPE tick;
+       uint16_t len;
+} spi_tasks[64];
+static uint8_t spi_task_index;
+
+static void
+validate_spi(struct stm_spi *stm_spi, int which, uint16_t len)
+{
+       uint32_t        sr = stm_spi->sr;
+
+       if (stm_spi != &stm_spi2)
+               return;
+       spi_tasks[spi_task_index].task = ao_cur_task ? ao_cur_task->task_id : 0;
+       spi_tasks[spi_task_index].which = which;
+       spi_tasks[spi_task_index].tick = ao_time();
+       spi_tasks[spi_task_index].len = len;
+       spi_task_index = (spi_task_index + 1) & (63);
+       if (sr & (1 << STM_SPI_SR_FRE))
+               ao_panic(0x40 | 1);
+       if (sr & (1 << STM_SPI_SR_BSY))
+               ao_panic(0x40 | 2);
+       if (sr & (1 << STM_SPI_SR_OVR))
+               ao_panic(0x40 | 3);
+       if (sr & (1 << STM_SPI_SR_MODF))
+               ao_panic(0x40 | 4);
+       if (sr & (1 << STM_SPI_SR_UDR))
+               ao_panic(0x40 | 5);
+       if ((sr & (1 << STM_SPI_SR_TXE)) == 0)
+               ao_panic(0x40 | 6);
+       if (sr & (1 << STM_SPI_SR_RXNE))
+               ao_panic(0x40 | 7);
+       if (which != 5 && which != 6 && which != 13)
+               if (ao_cur_task->task_id != ao_spi_mutex[1])
+                       ao_panic(0x40 | 8);
+}
+#else
+#define validate_spi(stm_spi, which, len) do { (void) (which); (void) (len); } while (0)
+#endif
+
+static void
+ao_spi_run(uint8_t id, uint8_t which, uint16_t len)
+{
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+       uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+       uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
+
+       validate_spi(stm_spi, which, len);
+
+       stm_spi->cr2 = SPI_CR2_DMA;
+
+       ao_dma_start(miso_dma_index);
+       ao_dma_start(mosi_dma_index);
+
+       ao_arch_critical(
+               while (!ao_dma_done[miso_dma_index])
+                       ao_sleep(&ao_dma_done[miso_dma_index]);
+               );
+
+       while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0);
+       while (stm_spi->sr & (1 << STM_SPI_SR_BSY));
+
+       validate_spi(stm_spi, which+1, len);
+
+       stm_spi->cr2 = 0;
+
+       ao_dma_done_transfer(mosi_dma_index);
+       ao_dma_done_transfer(miso_dma_index);
+}
+
 void
 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
 {
-       struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
-       uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
-       uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+       uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+       uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 
        /* Set up the transmit DMA to deliver data */
        ao_dma_set_transfer(mosi_dma_index,
@@ -85,9 +157,6 @@ ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
                            (0 << STM_DMA_CCR_TCIE));
 
-       /* Clear RXNE */
-       (void) stm_spi->dr;
-
        /* Set up the receive DMA -- when this is done, we know the SPI unit
         * is idle. Without this, we'd have to poll waiting for the BSY bit to
         * be cleared
@@ -106,24 +175,16 @@ ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
                            (1 << STM_DMA_CCR_TCIE));
 
-       stm_spi->cr2 = SPI_CR2_DMA;
-
-       ao_dma_start(miso_dma_index);
-       ao_dma_start(mosi_dma_index);
-       ao_arch_critical(
-               while (!ao_dma_done[miso_dma_index])
-                       ao_sleep(&ao_dma_done[miso_dma_index]);
-               );
-       ao_dma_done_transfer(mosi_dma_index);
-       ao_dma_done_transfer(miso_dma_index);
+       ao_spi_run(id, 1, len);
 }
 
 void
 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
 {
-       struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
-       uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
-       uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+       uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+       uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 
        /* Set up the transmit DMA to deliver data */
        ao_dma_set_transfer(mosi_dma_index,
@@ -140,9 +201,6 @@ ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
                            (0 << STM_DMA_CCR_TCIE));
 
-       /* Clear RXNE */
-       (void) stm_spi->dr;
-
        /* Set up the receive DMA -- when this is done, we know the SPI unit
         * is idle. Without this, we'd have to poll waiting for the BSY bit to
         * be cleared
@@ -161,40 +219,67 @@ ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
                            (1 << STM_DMA_CCR_TCIE));
 
-       stm_spi->cr2 = SPI_CR2_DMA;
-       ao_dma_start(miso_dma_index);
-       ao_dma_start(mosi_dma_index);
-       ao_arch_critical(
-               while (!ao_dma_done[miso_dma_index])
-                       ao_sleep(&ao_dma_done[miso_dma_index]);
-               );
-       ao_dma_done_transfer(mosi_dma_index);
-       ao_dma_done_transfer(miso_dma_index);
+       ao_spi_run(id, 3, len);
 }
 
 void
-ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index)
+ao_spi_start_bytes(uint8_t spi_index)
 {
-       uint8_t         *b = block;
-       struct stm_spi  *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 
        stm_spi->cr2 = SPI_CR2_SYNC;
+       validate_spi(stm_spi, 5, 0xffff);
+}
 
-       /* Clear RXNE */
+void
+ao_spi_stop_bytes(uint8_t spi_index)
+{
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+
+       while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
+               ;
+       while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
+               ;
+       /* Clear the OVR flag */
        (void) stm_spi->dr;
+       (void) stm_spi->sr;
+       validate_spi(stm_spi, 6, 0xffff);
+       stm_spi->cr2 = 0;
+}
 
+void
+ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index)
+{
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       const uint8_t   *b = block;
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+
+       stm_spi->cr2 = SPI_CR2_SYNC;
+
+       validate_spi(stm_spi, 7, len);
        while (len--) {
                while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
                stm_spi->dr = *b++;
        }
+       while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
+               ;
+       while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
+               ;
+       /* Clear the OVR flag */
+       (void) stm_spi->dr;
+       (void) stm_spi->sr;
+       validate_spi(stm_spi, 8, len);
 }
 
 void
 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
 {
-       struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
-       uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
-       uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+       uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+       uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 
        spi_dev_null = 0xff;
 
@@ -213,9 +298,6 @@ ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
                            (0 << STM_DMA_CCR_TCIE));
 
-       /* Clear RXNE */
-       (void) stm_spi->dr;
-
        /* Set up the receive DMA to capture data */
        ao_dma_set_transfer(miso_dma_index,
                            &stm_spi->dr,
@@ -231,26 +313,16 @@ ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
                            (1 << STM_DMA_CCR_TCIE));
 
-       stm_spi->cr2 = SPI_CR2_DMA;
-       ao_dma_start(miso_dma_index);
-       ao_dma_start(mosi_dma_index);
-
-       /* Wait until the SPI unit is done */
-       ao_arch_critical(
-               while (!ao_dma_done[miso_dma_index])
-                       ao_sleep(&ao_dma_done[miso_dma_index]);
-               );
-
-       ao_dma_done_transfer(mosi_dma_index);
-       ao_dma_done_transfer(miso_dma_index);
+       ao_spi_run(id, 9, len);
 }
 
 void
 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
 {
-       struct stm_spi *stm_spi = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].stm_spi;
-       uint8_t mosi_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].mosi_dma_index;
-       uint8_t miso_dma_index = ao_spi_stm_info[AO_SPI_INDEX(spi_index)].miso_dma_index;
+       uint8_t         id = AO_SPI_INDEX(spi_index);
+       struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
+       uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
+       uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 
        /* Set up transmit DMA to send data */
        ao_dma_set_transfer(mosi_dma_index,
@@ -267,9 +339,6 @@ ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR) |
                            (0 << STM_DMA_CCR_TCIE));
 
-       /* Clear RXNE */
-       (void) stm_spi->dr;
-
        /* Set up the receive DMA to capture data */
        ao_dma_set_transfer(miso_dma_index,
                            &stm_spi->dr,
@@ -285,18 +354,7 @@ ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
                            (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
                            (1 << STM_DMA_CCR_TCIE));
 
-       stm_spi->cr2 = SPI_CR2_DMA;
-       ao_dma_start(miso_dma_index);
-       ao_dma_start(mosi_dma_index);
-
-       /* Wait until the SPI unit is done */
-       ao_arch_critical(
-               while (!ao_dma_done[miso_dma_index])
-                       ao_sleep(&ao_dma_done[miso_dma_index]);
-               );
-
-       ao_dma_done_transfer(mosi_dma_index);
-       ao_dma_done_transfer(miso_dma_index);
+       ao_spi_run(id, 11, len);
 }
 
 static void
@@ -304,32 +362,24 @@ ao_spi_disable_index(uint8_t spi_index)
 {
        /* Disable current config
         */
-       switch (AO_SPI_INDEX(spi_index)) {
-       case STM_SPI_INDEX(1):
-               switch (spi_index) {
-               case AO_SPI_1_PA5_PA6_PA7:
-                       stm_gpio_set(&stm_gpioa, 5, 1);
-                       stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
-                       stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
-                       stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
-                       break;
-               case AO_SPI_1_PB3_PB4_PB5:
-                       stm_gpio_set(&stm_gpiob, 3, 1);
-                       stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
-                       stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
-                       stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
-                       break;
-               }
+       switch (spi_index) {
+       case AO_SPI_1_PA5_PA6_PA7:
+               stm_gpio_set(&stm_gpioa, 5, 1);
+               stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
+               stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
+               stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
                break;
-       case STM_SPI_INDEX(2):
-               switch (spi_index) {
-               case AO_SPI_2_PB13_PB14_PB15:
-                       stm_gpio_set(&stm_gpiob, 13, 1);
-                       stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
-                       stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
-                       stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
-                       break;
-               }
+       case AO_SPI_1_PB3_PB4_PB5:
+               stm_gpio_set(&stm_gpiob, 3, 1);
+               stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
+               stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
+               stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
+               break;
+       case AO_SPI_2_PB13_PB14_PB15:
+               stm_gpio_set(&stm_gpiob, 13, 1);
+               stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
+               stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
+               stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
                break;
        }
 }
@@ -337,29 +387,21 @@ ao_spi_disable_index(uint8_t spi_index)
 static void
 ao_spi_enable_index(uint8_t spi_index)
 {
-       switch (AO_SPI_INDEX(spi_index)) {
-       case STM_SPI_INDEX(1):
-               switch (spi_index) {
-               case AO_SPI_1_PA5_PA6_PA7:
-                       stm_afr_set(&stm_gpioa, 5, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpioa, 6, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpioa, 7, STM_AFR_AF0);
-                       break;
-               case AO_SPI_1_PB3_PB4_PB5:
-                       stm_afr_set(&stm_gpiob, 3, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpiob, 4, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpiob, 5, STM_AFR_AF0);
-                       break;
-               }
+       switch (spi_index) {
+       case AO_SPI_1_PA5_PA6_PA7:
+               stm_afr_set(&stm_gpioa, 5, STM_AFR_AF0);
+               stm_afr_set(&stm_gpioa, 6, STM_AFR_AF0);
+               stm_afr_set(&stm_gpioa, 7, STM_AFR_AF0);
                break;
-       case STM_SPI_INDEX(2):
-               switch (spi_index) {
-               case AO_SPI_2_PB13_PB14_PB15:
-                       stm_afr_set(&stm_gpiob, 13, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpiob, 14, STM_AFR_AF0);
-                       stm_afr_set(&stm_gpiob, 15, STM_AFR_AF0);
-                       break;
-               }
+       case AO_SPI_1_PB3_PB4_PB5:
+               stm_afr_set(&stm_gpiob, 3, STM_AFR_AF0);
+               stm_afr_set(&stm_gpiob, 4, STM_AFR_AF0);
+               stm_afr_set(&stm_gpiob, 5, STM_AFR_AF0);
+               break;
+       case AO_SPI_2_PB13_PB14_PB15:
+               stm_afr_set(&stm_gpiob, 13, STM_AFR_AF0);
+               stm_afr_set(&stm_gpiob, 14, STM_AFR_AF0);
+               stm_afr_set(&stm_gpiob, 15, STM_AFR_AF0);
                break;
        }
 }
@@ -370,6 +412,20 @@ ao_spi_config(uint8_t spi_index, uint32_t speed)
        uint8_t         id = AO_SPI_INDEX(spi_index);
        struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 
+       if (spi_index != ao_spi_index[id]) {
+
+               /* Disable old config
+                */
+               ao_spi_disable_index(ao_spi_index[id]);
+
+               /* Enable new config
+                */
+               ao_spi_enable_index(spi_index);
+
+               /* Remember current config
+                */
+               ao_spi_index[id] = spi_index;
+       }
        stm_spi->cr2 = SPI_CR2;
        stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) |                   /* Three wire mode */
                        (0 << STM_SPI_CR1_BIDIOE) |
@@ -385,21 +441,6 @@ ao_spi_config(uint8_t spi_index, uint32_t speed)
                        (1 << STM_SPI_CR1_MSTR) |
                        (0 << STM_SPI_CR1_CPOL) |                       /* Format 0 */
                        (0 << STM_SPI_CR1_CPHA));
-
-       if (spi_index != ao_spi_index[id]) {
-
-               /* Disable old config
-                */
-               ao_spi_disable_index(ao_spi_index[id]);
-
-               /* Enable new config
-                */
-               ao_spi_enable_index(spi_index);
-
-               /* Remember current config
-                */
-               ao_spi_index[id] = spi_index;
-       }
 }
 
 uint8_t
@@ -440,10 +481,57 @@ ao_spi_channel_init(uint8_t spi_index)
        ao_spi_disable_index(spi_index);
 
        stm_spi->cr1 = 0;
-       (void) stm_spi->sr;
        stm_spi->cr2 = SPI_CR2_SYNC;
+
+       /* Clear any pending data and error flags */
+       (void) stm_spi->dr;
+       (void) stm_spi->sr;
 }
 
+#if DEBUG
+void
+ao_spi_dump_cmd(void)
+{
+       int s;
+
+       for (s = 0; s < 64; s++) {
+               int i = (spi_task_index + s) & 63;
+               if (spi_tasks[i].which) {
+                       int t;
+                       const char *name = "(none)";
+                       for (t = 0; t < ao_num_tasks; t++)
+                               if (ao_tasks[t]->task_id == spi_tasks[i].task) {
+                                       name = ao_tasks[t]->name;
+                                       break;
+                               }
+                       printf("%2d: %5d task %2d which %2d len %5d %s\n",
+                              s,
+                              spi_tasks[i].tick,
+                              spi_tasks[i].task,
+                              spi_tasks[i].which,
+                              spi_tasks[i].len,
+                              name);
+               }
+       }
+       for (s = 0; s < STM_NUM_SPI; s++) {
+               struct stm_spi *spi = ao_spi_stm_info[s].stm_spi;
+
+               printf("%1d: mutex %2d index %3d miso dma %3d mosi dma %3d",
+                      s, ao_spi_mutex[s], ao_spi_index[s],
+                      ao_spi_stm_info[s].miso_dma_index,
+                      ao_spi_stm_info[s].mosi_dma_index);
+               printf(" cr1 %04x cr2 %02x sr %03x\n",
+                      spi->cr1, spi->cr2, spi->sr);
+       }
+
+}
+
+static const struct ao_cmds ao_spi_cmds[] = {
+       { ao_spi_dump_cmd,      "S\0Dump SPI status" },
+       { 0, NULL }
+};
+#endif
+
 void
 ao_spi_init(void)
 {
@@ -476,4 +564,7 @@ ao_spi_init(void)
        ao_spi_index[1] = AO_SPI_CONFIG_NONE;
        ao_spi_channel_init(STM_SPI_INDEX(2));
 #endif
+#if DEBUG
+       ao_cmd_register(&ao_spi_cmds[0]);
+#endif
 }
index c3d194b..d528e49 100644 (file)
@@ -1345,6 +1345,290 @@ extern struct stm_i2c stm_i2c1, stm_i2c2;
 #define STM_I2C_CCR_CCR                0
 #define  STM_I2C_CCR_MASK      0x7ff
 
+struct stm_tim1 {
+       vuint32_t       cr1;
+       vuint32_t       cr2;
+       vuint32_t       smcr;
+       vuint32_t       dier;
+
+       vuint32_t       sr;
+       vuint32_t       egr;
+       vuint32_t       ccmr1;
+       vuint32_t       ccmr2;
+
+       vuint32_t       ccer;
+       vuint32_t       cnt;
+       vuint32_t       psc;
+       vuint32_t       arr;
+
+       vuint32_t       rcr;
+       vuint32_t       ccr1;
+       vuint32_t       ccr2;
+       vuint32_t       ccr3;
+
+       vuint32_t       ccr4;
+       vuint32_t       bdtr;
+       vuint32_t       dcr;
+       vuint32_t       dmar;
+};
+
+#define STM_TIM1_CR1_CKD       8
+#define  STM_TIM1_CR1_CKD_1            0
+#define  STM_TIM1_CR1_CKD_2            1
+#define  STM_TIM1_CR1_CKD_4            2
+
+#define STM_TIM1_CR1_ARPE      7
+
+#define STM_TIM1_CR1_CMS       5
+#define  STM_TIM1_CR1_CMS_EDGE         0
+#define  STM_TIM1_CR1_CMS_CENTER_1     1
+#define  STM_TIM1_CR1_CMS_CENTER_2     2
+#define  STM_TIM1_CR1_CMS_CENTER_3     3
+
+#define STM_TIM1_CR1_DIR       4
+#define  STM_TIM1_CR1_DIR_UP           0
+#define  STM_TIM1_CR1_DIR_DOWn         1
+#define STM_TIM1_CR1_OPM       3
+#define STM_TIM1_CR1_URS       2
+#define STM_TIM1_CR1_UDIS      1
+#define STM_TIM1_CR1_CEN       0
+
+#define STM_TIM1_CR2_OIS4      14
+#define STM_TIM1_CR2_OIS3N     13
+#define STM_TIM1_CR2_OIS3      12
+#define STM_TIM1_CR2_OIS2N     11
+#define STM_TIM1_CR2_OIS2      10
+#define STM_TIM1_CR2_OIS1N     9
+#define STM_TIM1_CR2_OSI1      8
+#define STM_TIM1_CR2_TI1S      7
+#define STM_TIM1_CR2_MMS       4
+#define  STM_TIM1_CR2_MMS_RESET                        0
+#define  STM_TIM1_CR2_MMS_ENABLE               1
+#define  STM_TIM1_CR2_MMS_UPDATE               2
+#define  STM_TIM1_CR2_MMS_COMPARE_PULSE                3
+#define  STM_TIM1_CR2_MMS_COMPARE_OC1REF       4
+#define  STM_TIM1_CR2_MMS_COMPARE_OC2REF       5
+#define  STM_TIM1_CR2_MMS_COMPARE_OC3REF       6
+#define  STM_TIM1_CR2_MMS_COMPARE_OC4REF       7
+#define STM_TIM1_CR2_CCDS      3
+#define STM_TIM1_CR2_CCUS      2
+#define STM_TIM1_CR2_CCPC      0
+
+#define STM_TIM1_SMCR_ETP      15
+#define STM_TIM1_SMCR_ECE      14
+#define STM_TIM1_SMCR_ETPS     12
+#define  STM_TIM1_SMCR_ETPS_OFF                0
+#define  STM_TIM1_SMCR_ETPS_DIV_2      1
+#define  STM_TIM1_SMCR_ETPS_DIV_4      2
+#define  STM_TIM1_SMCR_ETPS_DIV_8      3
+
+#define STM_TIM1_SMCR_ETF      8
+#define  STM_TIM1_SMCR_ETF_NONE                0
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_2   1
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_4   2
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_8   3
+#define  STM_TIM1_SMCR_ETF_DIV_2_N_6   4
+#define  STM_TIM1_SMCR_ETF_DIV_2_N_8   5
+#define  STM_TIM1_SMCR_ETF_DIV_4_N_6   6
+#define  STM_TIM1_SMCR_ETF_DIV_4_N_8   7
+#define  STM_TIM1_SMCR_ETF_DIV_8_N_6   8
+#define  STM_TIM1_SMCR_ETF_DIV_8_N_8   9
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_5  10
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_6  11
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_8  12
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_5  13
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_6  14
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_8  15
+
+#define STM_TIM1_SMCR_MSM      7
+#define STM_TIM1_SMCR_TS       4
+#define  STM_TIM1_SMCR_TS_ITR0         0
+#define  STM_TIM1_SMCR_TS_ITR1         1
+#define  STM_TIM1_SMCR_TS_ITR2         2
+#define  STM_TIM1_SMCR_TS_ITR3         3
+#define  STM_TIM1_SMCR_TS_TI1F_ED      4
+#define  STM_TIM1_SMCR_TS_TI1FP1       5
+#define  STM_TIM1_SMCR_TS_TI2FP2       6
+#define  STM_TIM1_SMCR_TS_ETRF         7
+
+#define STM_TIM1_SMCR_OCCS     3
+#define STM_TIM1_SMCR_SMS      0
+#define  STM_TIM1_SMCR_SMS_DISABLE     0
+#define  STM_TIM1_SMCR_SMS_ENCODER_1   1
+#define  STM_TIM1_SMCR_SMS_ENCODER_2   2
+#define  STM_TIM1_SMCR_SMS_ENCODER_3   3
+#define  STM_TIM1_SMCR_SMS_RESET       4
+#define  STM_TIM1_SMCR_SMS_GATED       5
+#define  STM_TIM1_SMCR_SMS_TRIGGER     6
+#define  STM_TIM1_SMCR_SMS_EXTERNAL    7
+
+#define STM_TIM1_DIER_TDE      14
+#define STM_TIM1_DIER_COMDE    13
+#define STM_TIM1_DIER_CC4DE    12
+#define STM_TIM1_DIER_CC3DE    11
+#define STM_TIM1_DIER_CC2DE    10
+#define STM_TIM1_DIER_CC1DE    9
+#define STM_TIM1_DIER_UDE      8
+#define STM_TIM1_DIER_BIE      7
+#define STM_TIM1_DIER_TIE      6
+#define STM_TIM1_DIER_COMIE    5
+#define STM_TIM1_DIER_CC4IE    4
+#define STM_TIM1_DIER_CC3IE    3
+#define STM_TIM1_DIER_CC2IE    2
+#define STM_TIM1_DIER_CC1IE    1
+#define STM_TIM1_DIER_UIE      0
+
+#define STM_TIM1_SR_CC4OF      12
+#define STM_TIM1_SR_CC3OF      11
+#define STM_TIM1_SR_CC2OF      10
+#define STM_TIM1_SR_CC1OF      9
+#define STM_TIM1_SR_BIF                7
+#define STM_TIM1_SR_TIF                6
+#define STM_TIM1_SR_COMIF      5
+#define STM_TIM1_SR_CC4IF      4
+#define STM_TIM1_SR_CC3IF      3
+#define STM_TIM1_SR_CC2IF      2
+#define STM_TIM1_SR_CC1IF      1
+#define STM_TIM1_SR_UIF                0
+
+#define STM_TIM1_EGR_BG                7
+#define STM_TIM1_EGR_TG                6
+#define STM_TIM1_EGR_COMG      5
+#define STM_TIM1_EGR_CC4G      4
+#define STM_TIM1_EGR_CC3G      3
+#define STM_TIM1_EGR_CC2G      2
+#define STM_TIM1_EGR_CC1G      1
+#define STM_TIM1_EGR_UG                0
+
+#define STM_TIM1_CCMR1_OC2CE   15
+#define STM_TIM1_CCMR1_OC2M    12
+#define STM_TIM1_CCMR1_OC2PE   11
+#define STM_TIM1_CCMR1_OC2FE   10
+#define STM_TIM1_CCMR1_CC2S    8
+#define STM_TIM1_CCMR1_OC1CE   7
+#define STM_TIM1_CCMR1_OC1M    4
+#define  STM_TIM1_CCMR_OCM_FROZEN              0
+#define  STM_TIM1_CCMR_OCM_1_HIGH_MATCH                1
+#define  STM_TIM1_CCMR_OCM_1_LOW_MATCH         2
+#define  STM_TIM1_CCMR_OCM_TOGGLE              3
+#define  STM_TIM1_CCMR_OCM_FORCE_LOW           4
+#define  STM_TIM1_CCMR_OCM_FORCE_HIGH          5
+#define  STM_TIM1_CCMR_OCM_PWM_MODE_1          6
+#define  STM_TIM1_CCMR_OCM_PWM_MODE_2          7
+
+#define STM_TIM1_CCMR1_OC1PE   3
+#define STM_TIM1_CCMR1_OC1FE   2
+#define STM_TIM1_CCMR1_CC1S    0
+#define  STM_TIM1_CCMR_CCS_OUTPUT      0
+#define  STM_TIM1_CCMR_CCS_INPUT_TI1   1
+#define  STM_TIM1_CCMR_CCS_INPUT_TI2   2
+#define  STM_TIM1_CCMR_CCS_INPUT_TRC   3
+
+#define STM_TIM1_CCMR1_IC2F    12
+#define STM_TIM1_CCMR1_IC2PSC  10
+#define STM_TIM1_CCMR1_CC2S    8
+#define STM_TIM1_CCMR1_IC1F    4
+#define  STM_TIM1_CCMR1_IC1F_NONE      0
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_2 1
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_4 2
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_8 3
+#define  STM_TIM1_CCMR1_IC1F_DIV_2_N_6 4
+#define  STM_TIM1_CCMR1_IC1F_DIV_2_N_8 5
+#define  STM_TIM1_CCMR1_IC1F_DIV_4_N_6 6
+#define  STM_TIM1_CCMR1_IC1F_DIV_4_N_8 7
+#define  STM_TIM1_CCMR1_IC1F_DIV_8_N_6 8
+#define  STM_TIM1_CCMR1_IC1F_DIV_8_N_8 9
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_5        10
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_6        11
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_8        12
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_5        13
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_6        14
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_8        15
+
+#define STM_TIM1_CCMR1_IC1PSC  2
+#define  STM_TIM1_CCMR1_IC1PSC_NONE    0
+#define  STM_TIM1_CCMR1_IC1PSC_2       1
+#define  STM_TIM1_CCMR1_IC1PSC_4       2
+#define  STM_TIM1_CCMR1_IC1PSC_8       3
+
+#define STM_TIM1_CCMR1_CC1S    0
+#define  STM_TIM1_CCMR1_CC1S_OUTPUT    0
+#define  STM_TIM1_CCMR1_CC1S_TI1       1
+#define  STM_TIM1_CCMR1_CC1S_TI2       2
+#define  STM_TIM1_CCMR1_CC1S_TRC       3
+
+#define STM_TIM1_CCMR2_OC4CE   15
+#define STM_TIM1_CCMR2_OC4M    12
+#define STM_TIM1_CCMR2_OC4PE   11
+#define STM_TIM1_CCMR2_OC4FE   10
+#define STM_TIM1_CCMR2_CC4S    8
+#define  STM_TIM1_CCMR2_CCS_OUTPUT     0
+#define  STM_TIM1_CCMR2_CCS_INPUT_TI3  1
+#define  STM_TIM1_CCMR2_CCS_INPUT_TI4  2
+#define  STM_TIM1_CCMR2_CCS_INPUT_TRC  3
+#define STM_TIM1_CCMR2_OC3CE   7
+#define STM_TIM1_CCMR2_OC3M    4
+#define STM_TIM1_CCMR2_OC3PE   3
+#define STM_TIM1_CCMR2_OC3FE   2
+#define STM_TIM1_CCMR2_CC3S    0
+
+#define STM_TIM1_CCMR2_IC4F    12
+#define STM_TIM1_CCMR2_IC2PSC  10
+#define STM_TIM1_CCMR2_CC4S    8
+#define STM_TIM1_CCMR2_IC3F    4
+#define  STM_TIM1_CCMR2_IC1F_NONE      0
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_2 1
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_4 2
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_8 3
+#define  STM_TIM1_CCMR2_IC1F_DIV_2_N_6 4
+#define  STM_TIM1_CCMR2_IC1F_DIV_2_N_8 5
+#define  STM_TIM1_CCMR2_IC1F_DIV_4_N_6 6
+#define  STM_TIM1_CCMR2_IC1F_DIV_4_N_8 7
+#define  STM_TIM1_CCMR2_IC1F_DIV_8_N_6 8
+#define  STM_TIM1_CCMR2_IC1F_DIV_8_N_8 9
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_5        10
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_6        11
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_8        12
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_5        13
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_6        14
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_8        15
+
+#define STM_TIM1_CCER_CC4P     13
+#define STM_TIM1_CCER_CC4E     12
+#define STM_TIM1_CCER_CC3NP    11
+#define STM_TIM1_CCER_CC3NE    10
+#define STM_TIM1_CCER_CC3P     9
+#define STM_TIM1_CCER_CC3E     8
+#define STM_TIM1_CCER_CC2NP    7
+#define STM_TIM1_CCER_CC2NE    6
+#define STM_TIM1_CCER_CC2P     5
+#define STM_TIM1_CCER_CC2E     4
+#define STM_TIM1_CCER_CC1BP    3
+#define STM_TIM1_CCER_CC1NE    2
+#define STM_TIM1_CCER_CC1P     1
+#define STM_TIM1_CCER_CC1E     0
+
+#define STM_TIM1_BDTR_MOE      15
+#define STM_TIM1_BDTR_AOE      14
+#define STM_TIM1_BDTR_BKP      13
+#define STM_TIM1_BDTR_BKE      12
+#define STM_TIM1_BDTR_OSSR     11
+#define STM_TIM1_BDTR_OSSI     10
+#define STM_TIM1_BDTR_LOCK     8
+#define  STM_TIM1_BDTR_LOCK_OFF                0
+#define  STM_TIM1_BDTR_LOCK_LEVEL_1    1
+#define  STM_TIM1_BDTR_LOCK_LEVEL_2    2
+#define  STM_TIM1_BDTR_LOCK_LEVEL_3    3
+
+#define STM_TIM1_BDTR_DTG      0
+
+#define STM_TIM1_DCR_DBL       8
+#define STM_TIM1_DCR_DBA       0
+
+extern struct stm_tim1 stm_tim1;
+
+#define stm_tim1       (*(struct stm_tim1 *)0x40012c00)
+
 struct stm_tim23 {
        vuint32_t       cr1;
        vuint32_t       cr2;
@@ -1519,15 +1803,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
 
 #define STM_TIM23_CCMR2_OC4CE  15
 #define STM_TIM23_CCMR2_OC4M   12
-#define  STM_TIM23_CCMR2_OC4M_FROZEN                   0
-#define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
-#define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH         2
-#define  STM_TIM23_CCMR2_OC4M_TOGGLE                   3
-#define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                        4
-#define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH               5
-#define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1               6
-#define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2               7
-#define  STM_TIM23_CCMR2_OC4M_MASK                     7
+#define  STM_TIM23_CCMR2_OCM_FROZEN                    0
+#define  STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
+#define  STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH          2
+#define  STM_TIM23_CCMR2_OCM_TOGGLE                    3
+#define  STM_TIM23_CCMR2_OCM_FORCE_LOW                 4
+#define  STM_TIM23_CCMR2_OCM_FORCE_HIGH                        5
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_1                        6
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_2                        7
+#define  STM_TIM23_CCMR2_OCM_MASK                      7
 #define STM_TIM23_CCMR2_OC4PE  11
 #define STM_TIM23_CCMR2_OC4FE  10
 #define STM_TIM23_CCMR2_CC4S   8
@@ -1539,15 +1823,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
 
 #define STM_TIM23_CCMR2_OC3CE  7
 #define STM_TIM23_CCMR2_OC3M   4
-#define  STM_TIM23_CCMR2_OC3M_FROZEN                   0
-#define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH                1
-#define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH         2
-#define  STM_TIM23_CCMR2_OC3M_TOGGLE                   3
-#define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                        4
-#define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH               5
+#define  STM_TIM23_CCMR2_OCM_FROZEN                    0
+#define  STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH         1
+#define  STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH          2
+#define  STM_TIM23_CCMR2_OCM_TOGGLE                    3
+#define  STM_TIM23_CCMR2_OCM_FORCE_LOW                 4
+#define  STM_TIM23_CCMR2_OCM_FORCE_HIGH                        5
 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1               6
-#define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2               7
-#define  STM_TIM23_CCMR2_OC3M_MASK                     7
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_2                        7
+#define  STM_TIM23_CCMR2_OCM_MASK                      7
 #define STM_TIM23_CCMR2_OC3PE  11
 #define STM_TIM23_CCMR2_OC3FE  2
 #define STM_TIM23_CCMR2_CC3S   0