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e879d73)
We only need the power interface when placing the chip in the lowest
power state, so don't power up the power interface clock at startup,
instead wait until later.
Signed-off-by: Keith Packard <keithp@keithp.com>
ao_arch_block_interrupts();
ao_arch_block_interrupts();
+ /* Enable power interface clock */
+ stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
+ ao_arch_nop();
stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
ao_arch_nop();
stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
ao_arch_nop();
stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
/* Enable 1 wait state so the CPU can run at 48MHz */
stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
/* Enable 1 wait state so the CPU can run at 48MHz */
stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
- /* Enable power interface clock */
- stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
-
/* HCLK to 48MHz -> AHB prescaler = /1 */
cfgr = stm_rcc.cfgr;
cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
/* HCLK to 48MHz -> AHB prescaler = /1 */
cfgr = stm_rcc.cfgr;
cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);