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altos: Add STM32F0 beep and SPI byte API.
[fw/altos] / src / stmf0 / stm32f0.h
diff --git a/src/stmf0/stm32f0.h b/src/stmf0/stm32f0.h
index c3d194baf4015272858028c3314ff0f4968f57c3..d528e492127657f4bf5de4d6d85e860e8fe8c05e 100644 (file)
--- a/src/stmf0/stm32f0.h
+++ b/src/stmf0/stm32f0.h
@@ -1345,6 +1345,290 @@ extern struct stm_i2c stm_i2c1, stm_i2c2;
 #define STM_I2C_CCR_CCR                0
 #define  STM_I2C_CCR_MASK      0x7ff
 
+struct stm_tim1 {
+       vuint32_t       cr1;
+       vuint32_t       cr2;
+       vuint32_t       smcr;
+       vuint32_t       dier;
+
+       vuint32_t       sr;
+       vuint32_t       egr;
+       vuint32_t       ccmr1;
+       vuint32_t       ccmr2;
+
+       vuint32_t       ccer;
+       vuint32_t       cnt;
+       vuint32_t       psc;
+       vuint32_t       arr;
+
+       vuint32_t       rcr;
+       vuint32_t       ccr1;
+       vuint32_t       ccr2;
+       vuint32_t       ccr3;
+
+       vuint32_t       ccr4;
+       vuint32_t       bdtr;
+       vuint32_t       dcr;
+       vuint32_t       dmar;
+};
+
+#define STM_TIM1_CR1_CKD       8
+#define  STM_TIM1_CR1_CKD_1            0
+#define  STM_TIM1_CR1_CKD_2            1
+#define  STM_TIM1_CR1_CKD_4            2
+
+#define STM_TIM1_CR1_ARPE      7
+
+#define STM_TIM1_CR1_CMS       5
+#define  STM_TIM1_CR1_CMS_EDGE         0
+#define  STM_TIM1_CR1_CMS_CENTER_1     1
+#define  STM_TIM1_CR1_CMS_CENTER_2     2
+#define  STM_TIM1_CR1_CMS_CENTER_3     3
+
+#define STM_TIM1_CR1_DIR       4
+#define  STM_TIM1_CR1_DIR_UP           0
+#define  STM_TIM1_CR1_DIR_DOWn         1
+#define STM_TIM1_CR1_OPM       3
+#define STM_TIM1_CR1_URS       2
+#define STM_TIM1_CR1_UDIS      1
+#define STM_TIM1_CR1_CEN       0
+
+#define STM_TIM1_CR2_OIS4      14
+#define STM_TIM1_CR2_OIS3N     13
+#define STM_TIM1_CR2_OIS3      12
+#define STM_TIM1_CR2_OIS2N     11
+#define STM_TIM1_CR2_OIS2      10
+#define STM_TIM1_CR2_OIS1N     9
+#define STM_TIM1_CR2_OSI1      8
+#define STM_TIM1_CR2_TI1S      7
+#define STM_TIM1_CR2_MMS       4
+#define  STM_TIM1_CR2_MMS_RESET                        0
+#define  STM_TIM1_CR2_MMS_ENABLE               1
+#define  STM_TIM1_CR2_MMS_UPDATE               2
+#define  STM_TIM1_CR2_MMS_COMPARE_PULSE                3
+#define  STM_TIM1_CR2_MMS_COMPARE_OC1REF       4
+#define  STM_TIM1_CR2_MMS_COMPARE_OC2REF       5
+#define  STM_TIM1_CR2_MMS_COMPARE_OC3REF       6
+#define  STM_TIM1_CR2_MMS_COMPARE_OC4REF       7
+#define STM_TIM1_CR2_CCDS      3
+#define STM_TIM1_CR2_CCUS      2
+#define STM_TIM1_CR2_CCPC      0
+
+#define STM_TIM1_SMCR_ETP      15
+#define STM_TIM1_SMCR_ECE      14
+#define STM_TIM1_SMCR_ETPS     12
+#define  STM_TIM1_SMCR_ETPS_OFF                0
+#define  STM_TIM1_SMCR_ETPS_DIV_2      1
+#define  STM_TIM1_SMCR_ETPS_DIV_4      2
+#define  STM_TIM1_SMCR_ETPS_DIV_8      3
+
+#define STM_TIM1_SMCR_ETF      8
+#define  STM_TIM1_SMCR_ETF_NONE                0
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_2   1
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_4   2
+#define  STM_TIM1_SMCR_ETF_DIV_1_N_8   3
+#define  STM_TIM1_SMCR_ETF_DIV_2_N_6   4
+#define  STM_TIM1_SMCR_ETF_DIV_2_N_8   5
+#define  STM_TIM1_SMCR_ETF_DIV_4_N_6   6
+#define  STM_TIM1_SMCR_ETF_DIV_4_N_8   7
+#define  STM_TIM1_SMCR_ETF_DIV_8_N_6   8
+#define  STM_TIM1_SMCR_ETF_DIV_8_N_8   9
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_5  10
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_6  11
+#define  STM_TIM1_SMCR_ETF_DIV_16_N_8  12
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_5  13
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_6  14
+#define  STM_TIM1_SMCR_ETF_DIV_32_N_8  15
+
+#define STM_TIM1_SMCR_MSM      7
+#define STM_TIM1_SMCR_TS       4
+#define  STM_TIM1_SMCR_TS_ITR0         0
+#define  STM_TIM1_SMCR_TS_ITR1         1
+#define  STM_TIM1_SMCR_TS_ITR2         2
+#define  STM_TIM1_SMCR_TS_ITR3         3
+#define  STM_TIM1_SMCR_TS_TI1F_ED      4
+#define  STM_TIM1_SMCR_TS_TI1FP1       5
+#define  STM_TIM1_SMCR_TS_TI2FP2       6
+#define  STM_TIM1_SMCR_TS_ETRF         7
+
+#define STM_TIM1_SMCR_OCCS     3
+#define STM_TIM1_SMCR_SMS      0
+#define  STM_TIM1_SMCR_SMS_DISABLE     0
+#define  STM_TIM1_SMCR_SMS_ENCODER_1   1
+#define  STM_TIM1_SMCR_SMS_ENCODER_2   2
+#define  STM_TIM1_SMCR_SMS_ENCODER_3   3
+#define  STM_TIM1_SMCR_SMS_RESET       4
+#define  STM_TIM1_SMCR_SMS_GATED       5
+#define  STM_TIM1_SMCR_SMS_TRIGGER     6
+#define  STM_TIM1_SMCR_SMS_EXTERNAL    7
+
+#define STM_TIM1_DIER_TDE      14
+#define STM_TIM1_DIER_COMDE    13
+#define STM_TIM1_DIER_CC4DE    12
+#define STM_TIM1_DIER_CC3DE    11
+#define STM_TIM1_DIER_CC2DE    10
+#define STM_TIM1_DIER_CC1DE    9
+#define STM_TIM1_DIER_UDE      8
+#define STM_TIM1_DIER_BIE      7
+#define STM_TIM1_DIER_TIE      6
+#define STM_TIM1_DIER_COMIE    5
+#define STM_TIM1_DIER_CC4IE    4
+#define STM_TIM1_DIER_CC3IE    3
+#define STM_TIM1_DIER_CC2IE    2
+#define STM_TIM1_DIER_CC1IE    1
+#define STM_TIM1_DIER_UIE      0
+
+#define STM_TIM1_SR_CC4OF      12
+#define STM_TIM1_SR_CC3OF      11
+#define STM_TIM1_SR_CC2OF      10
+#define STM_TIM1_SR_CC1OF      9
+#define STM_TIM1_SR_BIF                7
+#define STM_TIM1_SR_TIF                6
+#define STM_TIM1_SR_COMIF      5
+#define STM_TIM1_SR_CC4IF      4
+#define STM_TIM1_SR_CC3IF      3
+#define STM_TIM1_SR_CC2IF      2
+#define STM_TIM1_SR_CC1IF      1
+#define STM_TIM1_SR_UIF                0
+
+#define STM_TIM1_EGR_BG                7
+#define STM_TIM1_EGR_TG                6
+#define STM_TIM1_EGR_COMG      5
+#define STM_TIM1_EGR_CC4G      4
+#define STM_TIM1_EGR_CC3G      3
+#define STM_TIM1_EGR_CC2G      2
+#define STM_TIM1_EGR_CC1G      1
+#define STM_TIM1_EGR_UG                0
+
+#define STM_TIM1_CCMR1_OC2CE   15
+#define STM_TIM1_CCMR1_OC2M    12
+#define STM_TIM1_CCMR1_OC2PE   11
+#define STM_TIM1_CCMR1_OC2FE   10
+#define STM_TIM1_CCMR1_CC2S    8
+#define STM_TIM1_CCMR1_OC1CE   7
+#define STM_TIM1_CCMR1_OC1M    4
+#define  STM_TIM1_CCMR_OCM_FROZEN              0
+#define  STM_TIM1_CCMR_OCM_1_HIGH_MATCH                1
+#define  STM_TIM1_CCMR_OCM_1_LOW_MATCH         2
+#define  STM_TIM1_CCMR_OCM_TOGGLE              3
+#define  STM_TIM1_CCMR_OCM_FORCE_LOW           4
+#define  STM_TIM1_CCMR_OCM_FORCE_HIGH          5
+#define  STM_TIM1_CCMR_OCM_PWM_MODE_1          6
+#define  STM_TIM1_CCMR_OCM_PWM_MODE_2          7
+
+#define STM_TIM1_CCMR1_OC1PE   3
+#define STM_TIM1_CCMR1_OC1FE   2
+#define STM_TIM1_CCMR1_CC1S    0
+#define  STM_TIM1_CCMR_CCS_OUTPUT      0
+#define  STM_TIM1_CCMR_CCS_INPUT_TI1   1
+#define  STM_TIM1_CCMR_CCS_INPUT_TI2   2
+#define  STM_TIM1_CCMR_CCS_INPUT_TRC   3
+
+#define STM_TIM1_CCMR1_IC2F    12
+#define STM_TIM1_CCMR1_IC2PSC  10
+#define STM_TIM1_CCMR1_CC2S    8
+#define STM_TIM1_CCMR1_IC1F    4
+#define  STM_TIM1_CCMR1_IC1F_NONE      0
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_2 1
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_4 2
+#define  STM_TIM1_CCMR1_IC1F_DIV_1_N_8 3
+#define  STM_TIM1_CCMR1_IC1F_DIV_2_N_6 4
+#define  STM_TIM1_CCMR1_IC1F_DIV_2_N_8 5
+#define  STM_TIM1_CCMR1_IC1F_DIV_4_N_6 6
+#define  STM_TIM1_CCMR1_IC1F_DIV_4_N_8 7
+#define  STM_TIM1_CCMR1_IC1F_DIV_8_N_6 8
+#define  STM_TIM1_CCMR1_IC1F_DIV_8_N_8 9
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_5        10
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_6        11
+#define  STM_TIM1_CCMR1_IC1F_DIV_16_N_8        12
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_5        13
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_6        14
+#define  STM_TIM1_CCMR1_IC1F_DIV_32_N_8        15
+
+#define STM_TIM1_CCMR1_IC1PSC  2
+#define  STM_TIM1_CCMR1_IC1PSC_NONE    0
+#define  STM_TIM1_CCMR1_IC1PSC_2       1
+#define  STM_TIM1_CCMR1_IC1PSC_4       2
+#define  STM_TIM1_CCMR1_IC1PSC_8       3
+
+#define STM_TIM1_CCMR1_CC1S    0
+#define  STM_TIM1_CCMR1_CC1S_OUTPUT    0
+#define  STM_TIM1_CCMR1_CC1S_TI1       1
+#define  STM_TIM1_CCMR1_CC1S_TI2       2
+#define  STM_TIM1_CCMR1_CC1S_TRC       3
+
+#define STM_TIM1_CCMR2_OC4CE   15
+#define STM_TIM1_CCMR2_OC4M    12
+#define STM_TIM1_CCMR2_OC4PE   11
+#define STM_TIM1_CCMR2_OC4FE   10
+#define STM_TIM1_CCMR2_CC4S    8
+#define  STM_TIM1_CCMR2_CCS_OUTPUT     0
+#define  STM_TIM1_CCMR2_CCS_INPUT_TI3  1
+#define  STM_TIM1_CCMR2_CCS_INPUT_TI4  2
+#define  STM_TIM1_CCMR2_CCS_INPUT_TRC  3
+#define STM_TIM1_CCMR2_OC3CE   7
+#define STM_TIM1_CCMR2_OC3M    4
+#define STM_TIM1_CCMR2_OC3PE   3
+#define STM_TIM1_CCMR2_OC3FE   2
+#define STM_TIM1_CCMR2_CC3S    0
+
+#define STM_TIM1_CCMR2_IC4F    12
+#define STM_TIM1_CCMR2_IC2PSC  10
+#define STM_TIM1_CCMR2_CC4S    8
+#define STM_TIM1_CCMR2_IC3F    4
+#define  STM_TIM1_CCMR2_IC1F_NONE      0
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_2 1
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_4 2
+#define  STM_TIM1_CCMR2_IC1F_DIV_1_N_8 3
+#define  STM_TIM1_CCMR2_IC1F_DIV_2_N_6 4
+#define  STM_TIM1_CCMR2_IC1F_DIV_2_N_8 5
+#define  STM_TIM1_CCMR2_IC1F_DIV_4_N_6 6
+#define  STM_TIM1_CCMR2_IC1F_DIV_4_N_8 7
+#define  STM_TIM1_CCMR2_IC1F_DIV_8_N_6 8
+#define  STM_TIM1_CCMR2_IC1F_DIV_8_N_8 9
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_5        10
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_6        11
+#define  STM_TIM1_CCMR2_IC1F_DIV_16_N_8        12
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_5        13
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_6        14
+#define  STM_TIM1_CCMR2_IC1F_DIV_32_N_8        15
+
+#define STM_TIM1_CCER_CC4P     13
+#define STM_TIM1_CCER_CC4E     12
+#define STM_TIM1_CCER_CC3NP    11
+#define STM_TIM1_CCER_CC3NE    10
+#define STM_TIM1_CCER_CC3P     9
+#define STM_TIM1_CCER_CC3E     8
+#define STM_TIM1_CCER_CC2NP    7
+#define STM_TIM1_CCER_CC2NE    6
+#define STM_TIM1_CCER_CC2P     5
+#define STM_TIM1_CCER_CC2E     4
+#define STM_TIM1_CCER_CC1BP    3
+#define STM_TIM1_CCER_CC1NE    2
+#define STM_TIM1_CCER_CC1P     1
+#define STM_TIM1_CCER_CC1E     0
+
+#define STM_TIM1_BDTR_MOE      15
+#define STM_TIM1_BDTR_AOE      14
+#define STM_TIM1_BDTR_BKP      13
+#define STM_TIM1_BDTR_BKE      12
+#define STM_TIM1_BDTR_OSSR     11
+#define STM_TIM1_BDTR_OSSI     10
+#define STM_TIM1_BDTR_LOCK     8
+#define  STM_TIM1_BDTR_LOCK_OFF                0
+#define  STM_TIM1_BDTR_LOCK_LEVEL_1    1
+#define  STM_TIM1_BDTR_LOCK_LEVEL_2    2
+#define  STM_TIM1_BDTR_LOCK_LEVEL_3    3
+
+#define STM_TIM1_BDTR_DTG      0
+
+#define STM_TIM1_DCR_DBL       8
+#define STM_TIM1_DCR_DBA       0
+
+extern struct stm_tim1 stm_tim1;
+
+#define stm_tim1       (*(struct stm_tim1 *)0x40012c00)
+
 struct stm_tim23 {
        vuint32_t       cr1;
        vuint32_t       cr2;
@@ -1519,15 +1803,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
 
 #define STM_TIM23_CCMR2_OC4CE  15
 #define STM_TIM23_CCMR2_OC4M   12
-#define  STM_TIM23_CCMR2_OC4M_FROZEN                   0
-#define  STM_TIM23_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
-#define  STM_TIM23_CCMR2_OC4M_SET_LOW_ON_MATCH         2
-#define  STM_TIM23_CCMR2_OC4M_TOGGLE                   3
-#define  STM_TIM23_CCMR2_OC4M_FORCE_LOW                        4
-#define  STM_TIM23_CCMR2_OC4M_FORCE_HIGH               5
-#define  STM_TIM23_CCMR2_OC4M_PWM_MODE_1               6
-#define  STM_TIM23_CCMR2_OC4M_PWM_MODE_2               7
-#define  STM_TIM23_CCMR2_OC4M_MASK                     7
+#define  STM_TIM23_CCMR2_OCM_FROZEN                    0
+#define  STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH 1
+#define  STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH          2
+#define  STM_TIM23_CCMR2_OCM_TOGGLE                    3
+#define  STM_TIM23_CCMR2_OCM_FORCE_LOW                 4
+#define  STM_TIM23_CCMR2_OCM_FORCE_HIGH                        5
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_1                        6
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_2                        7
+#define  STM_TIM23_CCMR2_OCM_MASK                      7
 #define STM_TIM23_CCMR2_OC4PE  11
 #define STM_TIM23_CCMR2_OC4FE  10
 #define STM_TIM23_CCMR2_CC4S   8
@@ -1539,15 +1823,15 @@ extern struct stm_tim23 stm_tim2, stm_tim3;
 
 #define STM_TIM23_CCMR2_OC3CE  7
 #define STM_TIM23_CCMR2_OC3M   4
-#define  STM_TIM23_CCMR2_OC3M_FROZEN                   0
-#define  STM_TIM23_CCMR2_OC3M_SET_HIGH_ON_MATCH                1
-#define  STM_TIM23_CCMR2_OC3M_SET_LOW_ON_MATCH         2
-#define  STM_TIM23_CCMR2_OC3M_TOGGLE                   3
-#define  STM_TIM23_CCMR2_OC3M_FORCE_LOW                        4
-#define  STM_TIM23_CCMR2_OC3M_FORCE_HIGH               5
+#define  STM_TIM23_CCMR2_OCM_FROZEN                    0
+#define  STM_TIM23_CCMR2_OCM_SET_HIGH_ON_MATCH         1
+#define  STM_TIM23_CCMR2_OCM_SET_LOW_ON_MATCH          2
+#define  STM_TIM23_CCMR2_OCM_TOGGLE                    3
+#define  STM_TIM23_CCMR2_OCM_FORCE_LOW                 4
+#define  STM_TIM23_CCMR2_OCM_FORCE_HIGH                        5
 #define  STM_TIM23_CCMR2_OC3M_PWM_MODE_1               6
-#define  STM_TIM23_CCMR2_OC3M_PWM_MODE_2               7
-#define  STM_TIM23_CCMR2_OC3M_MASK                     7
+#define  STM_TIM23_CCMR2_OCM_PWM_MODE_2                        7
+#define  STM_TIM23_CCMR2_OCM_MASK                      7
 #define STM_TIM23_CCMR2_OC3PE  11
 #define STM_TIM23_CCMR2_OC3FE  2
 #define STM_TIM23_CCMR2_CC3S   0
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