#define stm_gpiob (*((struct stm_gpio *) 0x48000400))
#define stm_gpioa (*((struct stm_gpio *) 0x48000000))
-struct stm_usart {
- vuint32_t cr1; /* control register 1 */
- vuint32_t cr2; /* control register 2 */
- vuint32_t cr3; /* control register 3 */
- vuint32_t brr; /* baud rate register */
-
- vuint32_t gtpr; /* guard time and prescaler */
- vuint32_t rtor; /* */
- vuint32_t rqr; /* */
- vuint32_t isr; /* */
-
- vuint32_t icr; /* */
- vuint32_t rdr; /* */
- vuint32_t tdr; /* */
-};
-
-extern struct stm_usart stm_usart1;
-extern struct stm_usart stm_usart2;
-
-#define STM_USART_SR_CTS (9) /* CTS flag */
-#define STM_USART_SR_LBD (8) /* LIN break detection flag */
-#define STM_USART_SR_TXE (7) /* Transmit data register empty */
-#define STM_USART_SR_TC (6) /* Transmission complete */
-#define STM_USART_SR_RXNE (5) /* Read data register not empty */
-#define STM_USART_SR_IDLE (4) /* IDLE line detected */
-#define STM_USART_SR_ORE (3) /* Overrun error */
-#define STM_USART_SR_NF (2) /* Noise detected flag */
-#define STM_USART_SR_FE (1) /* Framing error */
-#define STM_USART_SR_PE (0) /* Parity error */
-
-#define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
-#define STM_USART_CR1_UE (13) /* USART enable */
-#define STM_USART_CR1_M (12) /* Word length */
-#define STM_USART_CR1_WAKE (11) /* Wakeup method */
-#define STM_USART_CR1_PCE (10) /* Parity control enable */
-#define STM_USART_CR1_PS (9) /* Parity selection */
-#define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
-#define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
-#define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
-#define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
-#define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
-#define STM_USART_CR1_TE (3) /* Transmitter enable */
-#define STM_USART_CR1_RE (2) /* Receiver enable */
-#define STM_USART_CR1_RWU (1) /* Receiver wakeup */
-#define STM_USART_CR1_SBK (0) /* Send break */
-
-#define STM_USART_CR2_LINEN (14) /* LIN mode enable */
-#define STM_USART_CR2_STOP (12) /* STOP bits */
-#define STM_USART_CR2_STOP_MASK 3
-#define STM_USART_CR2_STOP_1 0
-#define STM_USART_CR2_STOP_0_5 1
-#define STM_USART_CR2_STOP_2 2
-#define STM_USART_CR2_STOP_1_5 3
-
-#define STM_USART_CR2_CLKEN (11) /* Clock enable */
-#define STM_USART_CR2_CPOL (10) /* Clock polarity */
-#define STM_USART_CR2_CPHA (9) /* Clock phase */
-#define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
-#define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
-#define STM_USART_CR2_LBDL (5) /* lin break detection length */
-#define STM_USART_CR2_ADD (0)
-#define STM_USART_CR2_ADD_MASK 0xf
-
-#define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
-#define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
-#define STM_USART_CR3_CTSE (9) /* CTS enable */
-#define STM_USART_CR3_RTSE (8) /* RTS enable */
-#define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
-#define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
-#define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
-#define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
-#define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
-#define STM_USART_CR3_IRLP (2) /* IrDA low-power */
-#define STM_USART_CR3_IREN (1) /* IrDA mode enable */
-#define STM_USART_CR3_EIE (0) /* Error interrupt enable */
-
-struct stm_tim {
-};
-
-extern struct stm_tim stm_tim9;
-
-struct stm_tim1011 {
- vuint32_t cr1;
- uint32_t unused_4;
- vuint32_t smcr;
- vuint32_t dier;
- vuint32_t sr;
- vuint32_t egr;
- vuint32_t ccmr1;
- uint32_t unused_1c;
- vuint32_t ccer;
- vuint32_t cnt;
- vuint32_t psc;
- vuint32_t arr;
- uint32_t unused_30;
- vuint32_t ccr1;
- uint32_t unused_38;
- uint32_t unused_3c;
- uint32_t unused_40;
- uint32_t unused_44;
- uint32_t unused_48;
- uint32_t unused_4c;
- vuint32_t or;
-};
-
-extern struct stm_tim1011 stm_tim10;
-extern struct stm_tim1011 stm_tim11;
-
-#define STM_TIM1011_CR1_CKD 8
-#define STM_TIM1011_CR1_CKD_1 0
-#define STM_TIM1011_CR1_CKD_2 1
-#define STM_TIM1011_CR1_CKD_4 2
-#define STM_TIM1011_CR1_CKD_MASK 3
-#define STM_TIM1011_CR1_ARPE 7
-#define STM_TIM1011_CR1_URS 2
-#define STM_TIM1011_CR1_UDIS 1
-#define STM_TIM1011_CR1_CEN 0
-
-#define STM_TIM1011_SMCR_ETP 15
-#define STM_TIM1011_SMCR_ECE 14
-#define STM_TIM1011_SMCR_ETPS 12
-#define STM_TIM1011_SMCR_ETPS_OFF 0
-#define STM_TIM1011_SMCR_ETPS_2 1
-#define STM_TIM1011_SMCR_ETPS_4 2
-#define STM_TIM1011_SMCR_ETPS_8 3
-#define STM_TIM1011_SMCR_ETPS_MASK 3
-#define STM_TIM1011_SMCR_ETF 8
-#define STM_TIM1011_SMCR_ETF_NONE 0
-#define STM_TIM1011_SMCR_ETF_CK_INT_2 1
-#define STM_TIM1011_SMCR_ETF_CK_INT_4 2
-#define STM_TIM1011_SMCR_ETF_CK_INT_8 3
-#define STM_TIM1011_SMCR_ETF_DTS_2_6 4
-#define STM_TIM1011_SMCR_ETF_DTS_2_8 5
-#define STM_TIM1011_SMCR_ETF_DTS_4_6 6
-#define STM_TIM1011_SMCR_ETF_DTS_4_8 7
-#define STM_TIM1011_SMCR_ETF_DTS_8_6 8
-#define STM_TIM1011_SMCR_ETF_DTS_8_8 9
-#define STM_TIM1011_SMCR_ETF_DTS_16_5 10
-#define STM_TIM1011_SMCR_ETF_DTS_16_6 11
-#define STM_TIM1011_SMCR_ETF_DTS_16_8 12
-#define STM_TIM1011_SMCR_ETF_DTS_32_5 13
-#define STM_TIM1011_SMCR_ETF_DTS_32_6 14
-#define STM_TIM1011_SMCR_ETF_DTS_32_8 15
-#define STM_TIM1011_SMCR_ETF_MASK 15
-
-#define STM_TIM1011_DIER_CC1E 1
-#define STM_TIM1011_DIER_UIE 0
-
-#define STM_TIM1011_SR_CC1OF 9
-#define STM_TIM1011_SR_CC1IF 1
-#define STM_TIM1011_SR_UIF 0
-
-#define STM_TIM1011_EGR_CC1G 1
-#define STM_TIM1011_EGR_UG 0
-
-#define STM_TIM1011_CCMR1_OC1CE 7
-#define STM_TIM1011_CCMR1_OC1M 4
-#define STM_TIM1011_CCMR1_OC1M_FROZEN 0
-#define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
-#define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
-#define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
-#define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
-#define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
-#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
-#define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
-#define STM_TIM1011_CCMR1_OC1M_MASK 7
-#define STM_TIM1011_CCMR1_OC1PE 3
-#define STM_TIM1011_CCMR1_OC1FE 2
-#define STM_TIM1011_CCMR1_CC1S 0
-#define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
-#define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
-#define STM_TIM1011_CCMR1_CC1S_MASK 3
-
-#define STM_TIM1011_CCMR1_IC1F_NONE 0
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
-#define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
-#define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
-#define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
-#define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
-#define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
-#define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
-#define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
-#define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
-#define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
-#define STM_TIM1011_CCMR1_IC1F_MASK 15
-#define STM_TIM1011_CCMR1_IC1PSC 2
-#define STM_TIM1011_CCMR1_IC1PSC_1 0
-#define STM_TIM1011_CCMR1_IC1PSC_2 1
-#define STM_TIM1011_CCMR1_IC1PSC_4 2
-#define STM_TIM1011_CCMR1_IC1PSC_8 3
-#define STM_TIM1011_CCMR1_IC1PSC_MASK 3
-#define STM_TIM1011_CCMR1_CC1S 0
-
-#define STM_TIM1011_CCER_CC1NP 3
-#define STM_TIM1011_CCER_CC1P 1
-#define STM_TIM1011_CCER_CC1E 0
-
-#define STM_TIM1011_OR_TI1_RMP_RI 3
-#define STM_TIM1011_ETR_RMP 2
-#define STM_TIM1011_TI1_RMP 0
-#define STM_TIM1011_TI1_RMP_GPIO 0
-#define STM_TIM1011_TI1_RMP_LSI 1
-#define STM_TIM1011_TI1_RMP_LSE 2
-#define STM_TIM1011_TI1_RMP_RTC 3
-#define STM_TIM1011_TI1_RMP_MASK 3
-
/* Flash interface */
struct stm_flash {
#define STM_RCC_CFGR_SW_HSI48 3
#define STM_RCC_CFGR_SW_MASK 3
+#define STM_RCC_APB2RSTR_DBGMCURST 22
+#define STM_RCC_APB2RSTR_TIM17RST 18
+#define STM_RCC_APB2RSTR_TIM16RST 17
+#define STM_RCC_APB2RSTR_TIM15RST 16
+#define STM_RCC_APB2RSTR_USART1RST 14
+#define STM_RCC_APB2RSTR_SPI1RST 12
+#define STM_RCC_APB2RSTR_TIM1RST 11
+#define STM_RCC_APB2RSTR_ADCRST 9
+#define STM_RCC_APB2RSTR_USART8RST 7
+#define STM_RCC_APB2RSTR_USART7RST 6
+#define STM_RCC_APB2RSTR_USART6RST 5
+#define STM_RCC_APB2RSTR_SYSCFGRST 1
+
#define STM_RCC_APB1RSTR_CECRST 30
#define STM_RCC_APB1RSTR_DACRST 29
#define STM_RCC_APB1RSTR_PWRRST 28
#define STM_RCC_AHBENR_FLITFEN 4
#define STM_RCC_AHBENR_SRAMEN 2
#define STM_RCC_AHBENR_DMA2EN 1
-#define STM_RCC_AHBENR_DMAEM 0
+#define STM_RCC_AHBENR_DMAEN 0
#define STM_RCC_APB2ENR_DBGMCUEN 22
#define STM_RCC_APB2ENR_TIM17EN 18
#define STM_PWR_CSR_SBF (1)
#define STM_PWR_CSR_WUF (0)
-struct stm_tim67 {
- vuint32_t cr1;
- vuint32_t cr2;
- uint32_t _unused_08;
- vuint32_t dier;
-
- vuint32_t sr;
- vuint32_t egr;
- uint32_t _unused_18;
- uint32_t _unused_1c;
-
- uint32_t _unused_20;
- vuint32_t cnt;
- vuint32_t psc;
- vuint32_t arr;
-};
-
-extern struct stm_tim67 stm_tim6;
-
-#define STM_TIM67_CR1_ARPE (7)
-#define STM_TIM67_CR1_OPM (3)
-#define STM_TIM67_CR1_URS (2)
-#define STM_TIM67_CR1_UDIS (1)
-#define STM_TIM67_CR1_CEN (0)
-
-#define STM_TIM67_CR2_MMS (4)
-#define STM_TIM67_CR2_MMS_RESET 0
-#define STM_TIM67_CR2_MMS_ENABLE 1
-#define STM_TIM67_CR2_MMS_UPDATE 2
-#define STM_TIM67_CR2_MMS_MASK 7
-
-#define STM_TIM67_DIER_UDE (8)
-#define STM_TIM67_DIER_UIE (0)
-
-#define STM_TIM67_SR_UIF (0)
-
-#define STM_TIM67_EGR_UG (0)
-
-struct stm_lcd {
- vuint32_t cr;
- vuint32_t fcr;
- vuint32_t sr;
- vuint32_t clr;
- uint32_t unused_0x10;
- vuint32_t ram[8*2];
-};
-
-extern struct stm_lcd stm_lcd;
-
-#define STM_LCD_CR_MUX_SEG (7)
-
-#define STM_LCD_CR_BIAS (5)
-#define STM_LCD_CR_BIAS_1_4 0
-#define STM_LCD_CR_BIAS_1_2 1
-#define STM_LCD_CR_BIAS_1_3 2
-#define STM_LCD_CR_BIAS_MASK 3
-
-#define STM_LCD_CR_DUTY (2)
-#define STM_LCD_CR_DUTY_STATIC 0
-#define STM_LCD_CR_DUTY_1_2 1
-#define STM_LCD_CR_DUTY_1_3 2
-#define STM_LCD_CR_DUTY_1_4 3
-#define STM_LCD_CR_DUTY_1_8 4
-#define STM_LCD_CR_DUTY_MASK 7
-
-#define STM_LCD_CR_VSEL (1)
-#define STM_LCD_CR_LCDEN (0)
-
-#define STM_LCD_FCR_PS (22)
-#define STM_LCD_FCR_PS_1 0x0
-#define STM_LCD_FCR_PS_2 0x1
-#define STM_LCD_FCR_PS_4 0x2
-#define STM_LCD_FCR_PS_8 0x3
-#define STM_LCD_FCR_PS_16 0x4
-#define STM_LCD_FCR_PS_32 0x5
-#define STM_LCD_FCR_PS_64 0x6
-#define STM_LCD_FCR_PS_128 0x7
-#define STM_LCD_FCR_PS_256 0x8
-#define STM_LCD_FCR_PS_512 0x9
-#define STM_LCD_FCR_PS_1024 0xa
-#define STM_LCD_FCR_PS_2048 0xb
-#define STM_LCD_FCR_PS_4096 0xc
-#define STM_LCD_FCR_PS_8192 0xd
-#define STM_LCD_FCR_PS_16384 0xe
-#define STM_LCD_FCR_PS_32768 0xf
-#define STM_LCD_FCR_PS_MASK 0xf
-
-#define STM_LCD_FCR_DIV (18)
-#define STM_LCD_FCR_DIV_16 0x0
-#define STM_LCD_FCR_DIV_17 0x1
-#define STM_LCD_FCR_DIV_18 0x2
-#define STM_LCD_FCR_DIV_19 0x3
-#define STM_LCD_FCR_DIV_20 0x4
-#define STM_LCD_FCR_DIV_21 0x5
-#define STM_LCD_FCR_DIV_22 0x6
-#define STM_LCD_FCR_DIV_23 0x7
-#define STM_LCD_FCR_DIV_24 0x8
-#define STM_LCD_FCR_DIV_25 0x9
-#define STM_LCD_FCR_DIV_26 0xa
-#define STM_LCD_FCR_DIV_27 0xb
-#define STM_LCD_FCR_DIV_28 0xc
-#define STM_LCD_FCR_DIV_29 0xd
-#define STM_LCD_FCR_DIV_30 0xe
-#define STM_LCD_FCR_DIV_31 0xf
-#define STM_LCD_FCR_DIV_MASK 0xf
-
-#define STM_LCD_FCR_BLINK (16)
-#define STM_LCD_FCR_BLINK_DISABLE 0
-#define STM_LCD_FCR_BLINK_SEG0_COM0 1
-#define STM_LCD_FCR_BLINK_SEG0_COMALL 2
-#define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
-#define STM_LCD_FCR_BLINK_MASK 3
-
-#define STM_LCD_FCR_BLINKF (13)
-#define STM_LCD_FCR_BLINKF_8 0
-#define STM_LCD_FCR_BLINKF_16 1
-#define STM_LCD_FCR_BLINKF_32 2
-#define STM_LCD_FCR_BLINKF_64 3
-#define STM_LCD_FCR_BLINKF_128 4
-#define STM_LCD_FCR_BLINKF_256 5
-#define STM_LCD_FCR_BLINKF_512 6
-#define STM_LCD_FCR_BLINKF_1024 7
-#define STM_LCD_FCR_BLINKF_MASK 7
-
-#define STM_LCD_FCR_CC (10)
-#define STM_LCD_FCR_CC_MASK 7
-
-#define STM_LCD_FCR_DEAD (7)
-#define STM_LCD_FCR_DEAD_MASK 7
-
-#define STM_LCD_FCR_PON (4)
-#define STM_LCD_FCR_PON_MASK 7
-
-#define STM_LCD_FCR_UDDIE (3)
-#define STM_LCD_FCR_SOFIE (1)
-#define STM_LCD_FCR_HD (0)
-
-#define STM_LCD_SR_FCRSF (5)
-#define STM_LCD_SR_RDY (4)
-#define STM_LCD_SR_UDD (3)
-#define STM_LCD_SR_UDR (2)
-#define STM_LCD_SR_SOF (1)
-#define STM_LCD_SR_ENS (0)
-
-#define STM_LCD_CLR_UDDC (3)
-#define STM_LCD_CLR_SOFC (1)
-
/* The SYSTICK starts at 0xe000e010 */
struct stm_systick {
#define STM_SCB_AIRCR_VECTCLRACTIVE 1
#define STM_SCB_AIRCR_VECTRESET 0
-struct stm_mpu {
- vuint32_t typer;
- vuint32_t cr;
- vuint32_t rnr;
- vuint32_t rbar;
-
- vuint32_t rasr;
- vuint32_t rbar_a1;
- vuint32_t rasr_a1;
- vuint32_t rbar_a2;
- vuint32_t rasr_a2;
- vuint32_t rbar_a3;
- vuint32_t rasr_a3;
-};
-
-extern struct stm_mpu stm_mpu;
-
-#define STM_MPU_TYPER_IREGION 16
-#define STM_MPU_TYPER_IREGION_MASK 0xff
-#define STM_MPU_TYPER_DREGION 8
-#define STM_MPU_TYPER_DREGION_MASK 0xff
-#define STM_MPU_TYPER_SEPARATE 0
-
-#define STM_MPU_CR_PRIVDEFENA 2
-#define STM_MPU_CR_HFNMIENA 1
-#define STM_MPU_CR_ENABLE 0
-
-#define STM_MPU_RNR_REGION 0
-#define STM_MPU_RNR_REGION_MASK 0xff
-
-#define STM_MPU_RBAR_ADDR 5
-#define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
-
-#define STM_MPU_RBAR_VALID 4
-#define STM_MPU_RBAR_REGION 0
-#define STM_MPU_RBAR_REGION_MASK 0xf
-
-#define STM_MPU_RASR_XN 28
-#define STM_MPU_RASR_AP 24
-#define STM_MPU_RASR_AP_NONE_NONE 0
-#define STM_MPU_RASR_AP_RW_NONE 1
-#define STM_MPU_RASR_AP_RW_RO 2
-#define STM_MPU_RASR_AP_RW_RW 3
-#define STM_MPU_RASR_AP_RO_NONE 5
-#define STM_MPU_RASR_AP_RO_RO 6
-#define STM_MPU_RASR_AP_MASK 7
-#define STM_MPU_RASR_TEX 19
-#define STM_MPU_RASR_TEX_MASK 7
-#define STM_MPU_RASR_S 18
-#define STM_MPU_RASR_C 17
-#define STM_MPU_RASR_B 16
-#define STM_MPU_RASR_SRD 8
-#define STM_MPU_RASR_SRD_MASK 0xff
-#define STM_MPU_RASR_SIZE 1
-#define STM_MPU_RASR_SIZE_MASK 0x1f
-#define STM_MPU_RASR_ENABLE 0
-
#define isr(name) void stm_ ## name ## _isr(void);
isr(nmi)
vuint32_t reserved;
};
-#define STM_NUM_DMA 7
+#define STM_NUM_DMA 6
struct stm_dma {
vuint32_t isr;
extern struct stm_dma stm_dma;
-/* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
+/* DMA channels go from 1 to 6, instead of 0 to 5 (sigh)
*/
#define STM_DMA_INDEX(channel) ((channel) - 1)
#define STM_DMA_CCR_TCIE (1)
#define STM_DMA_CCR_EN (0)
-#define STM_DMA_CHANNEL_ADC1 1
+/* DMA channel assignments. When a peripheral has multiple channels
+ * (indicated with _<number>), then it can be configured to either
+ * channel using syscfg.cfgr1
+ */
+
+#define STM_DMA_CHANNEL_ADC_1 1
+#define STM_DMA_CHANNEL_ADC_2 2
+
#define STM_DMA_CHANNEL_SPI1_RX 2
#define STM_DMA_CHANNEL_SPI1_TX 3
+
#define STM_DMA_CHANNEL_SPI2_RX 4
#define STM_DMA_CHANNEL_SPI2_TX 5
-#define STM_DMA_CHANNEL_USART3_TX 2
-#define STM_DMA_CHANNEL_USART3_RX 3
-#define STM_DMA_CHANNEL_USART1_TX 4
-#define STM_DMA_CHANNEL_USART1_RX 5
-#define STM_DMA_CHANNEL_USART2_RX 6
-#define STM_DMA_CHANNEL_USART2_TX 7
+
+#define STM_DMA_CHANNEL_USART1_TX_1 2
+#define STM_DMA_CHANNEL_USART1_RX_1 3
+#define STM_DMA_CHANNEL_USART1_TX_2 4
+#define STM_DMA_CHANNEL_USART1_RX_2 5
+
+#define STM_DMA_CHANNEL_USART2_RX 4
+#define STM_DMA_CHANNEL_USART2_TX 5
+
+#define STM_DMA_CHANNEL_I2C1_TX 2
+#define STM_DMA_CHANNEL_I2C1_RX 3
+
#define STM_DMA_CHANNEL_I2C2_TX 4
#define STM_DMA_CHANNEL_I2C2_RX 5
-#define STM_DMA_CHANNEL_I2C1_TX 6
-#define STM_DMA_CHANNEL_I2C1_RX 7
+
+#define STM_DMA_CHANNEL_TIM1_CH1 2
+#define STM_DMA_CHANNEL_TIM1_CH2 3
+#define STM_DMA_CHANNEL_TIM1_CH4 4
+#define STM_DMA_CHANNEL_TIM1_TRIG 4
+#define STM_DMA_CHANNEL_TIM1_COM 4
+#define STM_DMA_CHANNEL_TIM1_CH3 5
+#define STM_DMA_CHANNEL_TIM1_UP 5
+
#define STM_DMA_CHANNEL_TIM2_CH3 1
#define STM_DMA_CHANNEL_TIM2_UP 2
+#define STM_DMA_CHANNEL_TIM2_CH2 3
+#define STM_DMA_CHANNEL_TIM2_CH4 4
#define STM_DMA_CHANNEL_TIM2_CH1 5
-#define STM_DMA_CHANNEL_TIM2_CH2 7
-#define STM_DMA_CHANNEL_TIM2_CH4 7
+
#define STM_DMA_CHANNEL_TIM3_CH3 2
#define STM_DMA_CHANNEL_TIM3_CH4 3
#define STM_DMA_CHANNEL_TIM3_UP 3
-#define STM_DMA_CHANNEL_TIM3_CH1 6
-#define STM_DMA_CHANNEL_TIM3_TRIG 6
-#define STM_DMA_CHANNEL_TIM4_CH1 1
-#define STM_DMA_CHANNEL_TIM4_CH2 4
-#define STM_DMA_CHANNEL_TIM4_CH3 5
-#define STM_DMA_CHANNEL_TIM4_UP 7
-#define STM_DMA_CHANNEL_TIM6_UP_DA 2
-#define STM_DMA_CHANNEL_C_CHANNEL1 2
-#define STM_DMA_CHANNEL_TIM7_UP_DA 3
-#define STM_DMA_CHANNEL_C_CHANNEL2 3
+#define STM_DMA_CHANNEL_TIM3_CH1 4
+#define STM_DMA_CHANNEL_TIM3_TRIG 4
+
+#define STM_DMA_CHANNEL_TIM6_UP_DAC 2
+
+#define STM_DMA_CHANNEL_TIM15_CH1 5
+#define STM_DMA_CHANNEL_TIM15_UP 5
+#define STM_DMA_CHANNEL_TIM15_TRIG 5
+#define STM_DMA_CHANNEL_TIM15_COM 5
+
+#define STM_DMA_CHANNEL_TIM16_CH1_1 3
+#define STM_DMA_CHANNEL_TIM16_UP_1 3
+#define STM_DMA_CHANNEL_TIM16_CH1_2 4
+#define STM_DMA_CHANNEL_TIM16_UP_2 4
+
+#define STM_DMA_CHANNEL_TIM17_CH1_1 1
+#define STM_DMA_CHANNEL_TIM17_UP_1 1
+#define STM_DMA_CHANNEL_TIM17_CH1_2 2
+#define STM_DMA_CHANNEL_TIM17_UP_2 2
/*
* Only spi channel 1 and 2 can use DMA
#define STM_SPI_SR_RXNE 0
struct stm_adc {
- vuint32_t sr;
- vuint32_t cr1;
- vuint32_t cr2;
- vuint32_t smpr1;
- vuint32_t smpr2;
- vuint32_t smpr3;
- vuint32_t jofr1;
- vuint32_t jofr2;
- vuint32_t jofr3;
- vuint32_t jofr4;
- vuint32_t htr;
- vuint32_t ltr;
- vuint32_t sqr1;
- vuint32_t sqr2;
- vuint32_t sqr3;
- vuint32_t sqr4;
- vuint32_t sqr5;
- vuint32_t jsqr;
- vuint32_t jdr1;
- vuint32_t jdr2;
- vuint32_t jdr3;
- vuint32_t jdr4;
+ vuint32_t isr;
+ vuint32_t ier;
+ vuint32_t cr;
+ vuint32_t cfgr1;
+
+ vuint32_t cfgr2;
+ vuint32_t smpr;
+ vuint32_t r_18;
+ vuint32_t r_1c;
+
+ vuint32_t tr;
+ vuint32_t r_24;
+ vuint32_t chselr;
+ vuint32_t r_2c;
+
+ vuint32_t r_30[4];
+
vuint32_t dr;
- uint8_t reserved[0x300 - 0x5c];
- vuint32_t csr;
+
+ uint8_t r_44[0x308 - 0x44];
vuint32_t ccr;
};
extern struct stm_adc stm_adc;
-#define STM_ADC_SR_JCNR 9
-#define STM_ADC_SR_RCNR 8
-#define STM_ADC_SR_ADONS 6
-#define STM_ADC_SR_OVR 5
-#define STM_ADC_SR_STRT 4
-#define STM_ADC_SR_JSTRT 3
-#define STM_ADC_SR_JEOC 2
-#define STM_ADC_SR_EOC 1
-#define STM_ADC_SR_AWD 0
-
-#define STM_ADC_CR1_OVRIE 26
-#define STM_ADC_CR1_RES 24
-#define STM_ADC_CR1_RES_12 0
-#define STM_ADC_CR1_RES_10 1
-#define STM_ADC_CR1_RES_8 2
-#define STM_ADC_CR1_RES_6 3
-#define STM_ADC_CR1_RES_MASK 3
-#define STM_ADC_CR1_AWDEN 23
-#define STM_ADC_CR1_JAWDEN 22
-#define STM_ADC_CR1_PDI 17
-#define STM_ADC_CR1_PDD 16
-#define STM_ADC_CR1_DISCNUM 13
-#define STM_ADC_CR1_DISCNUM_1 0
-#define STM_ADC_CR1_DISCNUM_2 1
-#define STM_ADC_CR1_DISCNUM_3 2
-#define STM_ADC_CR1_DISCNUM_4 3
-#define STM_ADC_CR1_DISCNUM_5 4
-#define STM_ADC_CR1_DISCNUM_6 5
-#define STM_ADC_CR1_DISCNUM_7 6
-#define STM_ADC_CR1_DISCNUM_8 7
-#define STM_ADC_CR1_DISCNUM_MASK 7
-#define STM_ADC_CR1_JDISCEN 12
-#define STM_ADC_CR1_DISCEN 11
-#define STM_ADC_CR1_JAUTO 10
-#define STM_ADC_CR1_AWDSGL 9
-#define STM_ADC_CR1_SCAN 8
-#define STM_ADC_CR1_JEOCIE 7
-#define STM_ADC_CR1_AWDIE 6
-#define STM_ADC_CR1_EOCIE 5
-#define STM_ADC_CR1_AWDCH 0
-#define STM_ADC_CR1_AWDCH_MASK 0x1f
-
-#define STM_ADC_CR2_SWSTART 30
-#define STM_ADC_CR2_EXTEN 28
-#define STM_ADC_CR2_EXTEN_DISABLE 0
-#define STM_ADC_CR2_EXTEN_RISING 1
-#define STM_ADC_CR2_EXTEN_FALLING 2
-#define STM_ADC_CR2_EXTEN_BOTH 3
-#define STM_ADC_CR2_EXTEN_MASK 3
-#define STM_ADC_CR2_EXTSEL 24
-#define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
-#define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
-#define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
-#define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
-#define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
-#define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
-#define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
-#define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
-#define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
-#define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
-#define STM_ADC_CR2_EXTSEL_EXTI_11 15
-#define STM_ADC_CR2_EXTSEL_MASK 15
-#define STM_ADC_CR2_JWSTART 22
-#define STM_ADC_CR2_JEXTEN 20
-#define STM_ADC_CR2_JEXTEN_DISABLE 0
-#define STM_ADC_CR2_JEXTEN_RISING 1
-#define STM_ADC_CR2_JEXTEN_FALLING 2
-#define STM_ADC_CR2_JEXTEN_BOTH 3
-#define STM_ADC_CR2_JEXTEN_MASK 3
-#define STM_ADC_CR2_JEXTSEL 16
-#define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
-#define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
-#define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
-#define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
-#define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
-#define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
-#define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
-#define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
-#define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
-#define STM_ADC_CR2_JEXTSEL_EXTI_15 15
-#define STM_ADC_CR2_JEXTSEL_MASK 15
-#define STM_ADC_CR2_ALIGN 11
-#define STM_ADC_CR2_EOCS 10
-#define STM_ADC_CR2_DDS 9
-#define STM_ADC_CR2_DMA 8
-#define STM_ADC_CR2_DELS 4
-#define STM_ADC_CR2_DELS_NONE 0
-#define STM_ADC_CR2_DELS_UNTIL_READ 1
-#define STM_ADC_CR2_DELS_7 2
-#define STM_ADC_CR2_DELS_15 3
-#define STM_ADC_CR2_DELS_31 4
-#define STM_ADC_CR2_DELS_63 5
-#define STM_ADC_CR2_DELS_127 6
-#define STM_ADC_CR2_DELS_255 7
-#define STM_ADC_CR2_DELS_MASK 7
-#define STM_ADC_CR2_CONT 1
-#define STM_ADC_CR2_ADON 0
-
-#define STM_ADC_CCR_TSVREFE 23
-#define STM_ADC_CCR_ADCPRE 16
-#define STM_ADC_CCR_ADCPRE_HSI_1 0
-#define STM_ADC_CCR_ADCPRE_HSI_2 1
-#define STM_ADC_CCR_ADCPRE_HSI_4 2
-#define STM_ADC_CCR_ADCPRE_MASK 3
+#define STM_ADC_ISR_AWD 7
+#define STM_ADC_ISR_OVR 4
+#define STM_ADC_ISR_EOSEQ 3
+#define STM_ADC_ISR_EOC 2
+#define STM_ADC_ISR_EOSMP 1
+#define STM_ADC_ISR_ADRDY 0
+
+#define STM_ADC_IER_AWDIE 7
+#define STM_ADC_IER_OVRIE 4
+#define STM_ADC_IER_EOSEQIE 3
+#define STM_ADC_IER_EOCIE 2
+#define STM_ADC_IER_EOSMPIE 1
+#define STM_ADC_IER_ADRDYIE 0
+
+#define STM_ADC_CR_ADCAL 31
+#define STM_ADC_CR_ADSTP 4
+#define STM_ADC_CR_ADSTART 2
+#define STM_ADC_CR_ADDIS 1
+#define STM_ADC_CR_ADEN 0
+
+#define STM_ADC_CFGR1_AWDCH 26
+#define STM_ADC_CFGR1_AWDEN 23
+#define STM_ADC_CFGR1_AWDSGL 22
+#define STM_ADC_CFGR1_DISCEN 16
+#define STM_ADC_CFGR1_AUTOOFF 15
+#define STM_ADC_CFGR1_WAIT 14
+#define STM_ADC_CFGR1_CONT 13
+#define STM_ADC_CFGR1_OVRMOD 12
+#define STM_ADC_CFGR1_EXTEN 10
+#define STM_ADC_CFGR1_EXTEN_DISABLE 0
+#define STM_ADC_CFGR1_EXTEN_RISING 1
+#define STM_ADC_CFGR1_EXTEN_FALLING 2
+#define STM_ADC_CFGR1_EXTEN_BOTH 3
+#define STM_ADC_CFGR1_EXTEN_MASK 3
+
+#define STM_ADC_CFGR1_EXTSEL 6
+#define STM_ADC_CFGR1_ALIGN 5
+#define STM_ADC_CFGR1_RES 3
+#define STM_ADC_CFGR1_RES_12 0
+#define STM_ADC_CFGR1_RES_10 1
+#define STM_ADC_CFGR1_RES_8 2
+#define STM_ADC_CFGR1_RES_6 3
+#define STM_ADC_CFGR1_RES_MASK 3
+#define STM_ADC_CFGR1_SCANDIR 2
+#define STM_ADC_CFGR1_SCANDIR_UP 0
+#define STM_ADC_CFGR1_SCANDIR_DOWN 1
+#define STM_ADC_CFGR1_DMACFG 1
+#define STM_ADC_CFGR1_DMACFG_ONESHOT 0
+#define STM_ADC_CFGR1_DMACFG_CIRCULAR 1
+#define STM_ADC_CFGR1_DMAEN 0
+
+#define STM_ADC_CFGR2_CKMODE 30
+#define STM_ADC_CFGR2_CKMODE_ADCCLK 0
+#define STM_ADC_CFGR2_CKMODE_PCLK_2 1
+#define STM_ADC_CFGR2_CKMODE_PCLK_4 2
+
+#define STM_ADC_SMPR_SMP 0
+#define STM_ADC_SMPR_SMP_1_5 0
+#define STM_ADC_SMPR_SMP_7_5 1
+#define STM_ADC_SMPR_SMP_13_5 2
+#define STM_ADC_SMPR_SMP_28_5 3
+#define STM_ADC_SMPR_SMP_41_5 4
+#define STM_ADC_SMPR_SMP_55_5 5
+#define STM_ADC_SMPR_SMP_71_5 6
+#define STM_ADC_SMPR_SMP_239_5 7
+
+#define STM_ADC_TR_HT 16
+#define STM_ADC_TR_LT 0
+
+#define STM_ADC_CCR_VBATEN 24
+#define STM_ADC_CCR_TSEN 23
+#define STM_ADC_CCR_VREFEN 22
struct stm_cal {
uint16_t ts_cal_cold; /* 30°C */
projects / fw / altos / blobdiff