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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32F0_H_
  19 #define _STM32F0_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24 typedef volatile void *         vvoid_t;
  25 typedef volatile uint16_t       vuint16_t;
  26
  27 struct stm_gpio {
  28         vuint32_t       moder;
  29         vuint32_t       otyper;
  30         vuint32_t       ospeedr;
  31         vuint32_t       pupdr;
  32
  33         vuint32_t       idr;
  34         vuint32_t       odr;
  35         vuint32_t       bsrr;
  36         vuint32_t       lckr;
  37
  38         vuint32_t       afrl;
  39         vuint32_t       afrh;
  40         vuint32_t       brr;
  41 };
  42
  43 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  44 #define STM_MODER_MASK                  3
  45 #define STM_MODER_INPUT                 0
  46 #define STM_MODER_OUTPUT                1
  47 #define STM_MODER_ALTERNATE             2
  48 #define STM_MODER_ANALOG                3
  49
  50 static inline void
  51 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  52         gpio->moder = ((gpio->moder &
  53                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  54                        value << STM_MODER_SHIFT(pin));
  55 }
  56
  57 static inline uint32_t
  58 stm_moder_get(struct stm_gpio *gpio, int pin) {
  59         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  60 }
  61
  62 #define STM_OTYPER_SHIFT(pin)           (pin)
  63 #define STM_OTYPER_MASK                 1
  64 #define STM_OTYPER_PUSH_PULL            0
  65 #define STM_OTYPER_OPEN_DRAIN           1
  66
  67 static inline void
  68 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  69         gpio->otyper = ((gpio->otyper &
  70                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  71                         value << STM_OTYPER_SHIFT(pin));
  72 }
  73
  74 static inline uint32_t
  75 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  76         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  77 }
  78
  79 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  80 #define STM_OSPEEDR_MASK                3
  81 #define STM_OSPEEDR_LOW                 0       /* 2MHz */
  82 #define STM_OSPEEDR_MEDIUM              1       /* 10MHz */
  83 #define STM_OSPEEDR_HIGH                3       /* 10-50MHz */
  84
  85 static inline void
  86 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  87         gpio->ospeedr = ((gpio->ospeedr &
  88                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  89                        value << STM_OSPEEDR_SHIFT(pin));
  90 }
  91
  92 static inline uint32_t
  93 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  94         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  95 }
  96
  97 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  98 #define STM_PUPDR_MASK                  3
  99 #define STM_PUPDR_NONE                  0
 100 #define STM_PUPDR_PULL_UP               1
 101 #define STM_PUPDR_PULL_DOWN             2
 102 #define STM_PUPDR_RESERVED              3
 103
 104 static inline void
 105 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 106         gpio->pupdr = ((gpio->pupdr &
 107                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 108                        value << STM_PUPDR_SHIFT(pin));
 109 }
 110
 111 static inline uint32_t
 112 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 113         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 114 }
 115
 116 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 117 #define STM_AFR_MASK                    0xf
 118 #define STM_AFR_NONE                    0
 119 #define STM_AFR_AF0                     0x0
 120 #define STM_AFR_AF1                     0x1
 121 #define STM_AFR_AF2                     0x2
 122 #define STM_AFR_AF3                     0x3
 123 #define STM_AFR_AF4                     0x4
 124 #define STM_AFR_AF5                     0x5
 125 #define STM_AFR_AF6                     0x6
 126 #define STM_AFR_AF7                     0x7
 127
 128 static inline void
 129 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 130         /*
 131          * Set alternate pin mode too
 132          */
 133         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 134         if (pin < 8)
 135                 gpio->afrl = ((gpio->afrl &
 136                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 137                               value << STM_AFR_SHIFT(pin));
 138         else {
 139                 pin -= 8;
 140                 gpio->afrh = ((gpio->afrh &
 141                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 142                               value << STM_AFR_SHIFT(pin));
 143         }
 144 }
 145
 146 static inline uint32_t
 147 stm_afr_get(struct stm_gpio *gpio, int pin) {
 148         if (pin < 8)
 149                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 150         else {
 151                 pin -= 8;
 152                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 153         }
 154 }
 155
 156 static inline void
 157 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 158         /* Use the bit set/reset register to do this atomically */
 159         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 160 }
 161
 162 static inline uint8_t
 163 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 164         return (gpio->idr >> pin) & 1;
 165 }
 166
 167 static inline uint16_t
 168 stm_gpio_get_all(struct stm_gpio *gpio) {
 169         return gpio->idr;
 170 }
 171
 172 /*
 173  * We can't define these in registers.ld or our fancy
 174  * ao_enable_gpio macro will expand into a huge pile of code
 175  * as the compiler won't do correct constant folding and
 176  * dead-code elimination
 177  */
 178
 179 extern struct stm_gpio stm_gpioa;
 180 extern struct stm_gpio stm_gpiob;
 181 extern struct stm_gpio stm_gpioc;
 182 extern struct stm_gpio stm_gpiof;
 183
 184 #define stm_gpiof  (*((struct stm_gpio *) 0x48001400))
 185 #define stm_gpioc  (*((struct stm_gpio *) 0x48000800))
 186 #define stm_gpiob  (*((struct stm_gpio *) 0x48000400))
 187 #define stm_gpioa  (*((struct stm_gpio *) 0x48000000))
 188
 189 /* Flash interface */
 190
 191 struct stm_flash {
 192         vuint32_t       acr;
 193         vuint32_t       keyr;
 194         vuint32_t       optkeyr;
 195         vuint32_t       sr;
 196
 197         vuint32_t       cr;
 198         vuint32_t       ar;
 199         vuint32_t       unused_0x18;
 200         vuint32_t       obr;
 201
 202         vuint32_t       wrpr;
 203 };
 204
 205 extern struct stm_flash stm_flash;
 206
 207 #define STM_FLASH_ACR_PRFTBS    (5)
 208 #define STM_FLASH_ACR_PRFTBE    (4)
 209 #define STM_FLASH_ACR_LATENCY   (0)
 210 #define  STM_FLASH_ACR_LATENCY_0                0
 211 #define  STM_FLASH_ACR_LATENCY_1                1
 212
 213 #define STM_FLASH_PECR_OBL_LAUNCH       18
 214 #define STM_FLASH_PECR_ERRIE            17
 215 #define STM_FLASH_PECR_EOPIE            16
 216 #define STM_FLASH_PECR_FPRG             10
 217 #define STM_FLASH_PECR_ERASE            9
 218 #define STM_FLASH_PECR_FTDW             8
 219 #define STM_FLASH_PECR_DATA             4
 220 #define STM_FLASH_PECR_PROG             3
 221 #define STM_FLASH_PECR_OPTLOCK          2
 222 #define STM_FLASH_PECR_PRGLOCK          1
 223 #define STM_FLASH_PECR_PELOCK           0
 224
 225 #define STM_FLASH_SR_EOP                5
 226 #define STM_FLASH_SR_WRPRTERR           4
 227 #define STM_FLASH_SR_PGERR              2
 228 #define STM_FLASH_SR_BSY                0
 229
 230 #define STM_FLASH_CR_OBL_LAUNCH         13
 231 #define STM_FLASH_CR_EOPIE              12
 232 #define STM_FLASH_CR_ERRIE              10
 233 #define STM_FLASH_CR_OPTWRE             9
 234 #define STM_FLASH_CR_LOCK               7
 235 #define STM_FLASH_CR_STRT               6
 236 #define STM_FLASH_CR_OPTER              5
 237 #define STM_FLASH_CR_OPTPG              4
 238 #define STM_FLASH_CR_MER                2
 239 #define STM_FLASH_CR_PER                1
 240 #define STM_FLASH_CR_PG                 0
 241
 242 #define STM_FLASH_OBR_DATA1             24
 243 #define STM_FLASH_OBR_DATA0             16
 244 #define STM_FLASH_OBR_BOOT_SEL          15
 245 #define STM_FLASH_OBR_RAM_PARITY_CHECK  14
 246 #define STM_FLASH_OBR_VDDA_MONITOR      13
 247 #define STM_FLASH_OBR_NBOOT1            12
 248 #define STM_FLASH_OBR_NBOOT0            11
 249 #define STM_FLASH_OBR_NRST_STDBY        10
 250 #define STM_FLASH_OBR_NRST_STOP         9
 251 #define STM_FLASH_OBR_WDG_SW            8
 252 #define STM_FLASH_OBR_RDPRT             1
 253 #define  STM_FLASH_OBR_RDPRT_LEVEL0             0
 254 #define  STM_FLASH_OBR_RDPRT_LEVEL1             1
 255 #define  STM_FLASH_OBR_RDPRT_LEVEL2             3
 256 #define STM_FLASH_OBR_OPTERR            0
 257
 258 #define STM_FLASH_KEYR_KEY1     0x45670123
 259 #define STM_FLASH_KEYR_KEY2     0xcdef89ab
 260
 261 struct stm_rcc {
 262         vuint32_t       cr;
 263         vuint32_t       cfgr;
 264         vuint32_t       cir;
 265         vuint32_t       apb2rstr;
 266
 267         vuint32_t       apb1rstr;
 268         vuint32_t       ahbenr;
 269         vuint32_t       apb2enr;
 270         vuint32_t       apb1enr;
 271
 272         vuint32_t       bdcr;
 273         vuint32_t       csr;
 274         vuint32_t       ahbrstr;
 275         vuint32_t       cfgr2;
 276
 277         vuint32_t       cfgr3;
 278         vuint32_t       cr2;
 279 };
 280
 281 extern struct stm_rcc stm_rcc;
 282
 283 /* Nominal high speed internal oscillator frequency is 16MHz */
 284 #define STM_HSI_FREQ            16000000
 285
 286 #define STM_RCC_CR_PLLRDY       (25)
 287 #define STM_RCC_CR_PLLON        (24)
 288 #define STM_RCC_CR_CSSON        (19)
 289 #define STM_RCC_CR_HSEBYP       (18)
 290 #define STM_RCC_CR_HSERDY       (17)
 291 #define STM_RCC_CR_HSEON        (16)
 292 #define STM_RCC_CR_HSICAL       (8)
 293 #define STM_RCC_CR_HSITRIM      (3)
 294 #define STM_RCC_CR_HSIRDY       (1)
 295 #define STM_RCC_CR_HSION        (0)
 296
 297 #define STM_RCC_CFGR_PLL_NODIV  (31)
 298 #define  STM_RCC_CFGR_PLL_NODIV_DIV_1   1
 299 #define  STM_RCC_CFGR_PLL_NODIV_DIV_2   0
 300
 301 #define STM_RCC_CFGR_MCOPRE     (28)
 302 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 303 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 304 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 305 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 306 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 307 #define  STM_RCC_CFGR_MCOPRE_DIV_32     5
 308 #define  STM_RCC_CFGR_MCOPRE_DIV_64     6
 309 #define  STM_RCC_CFGR_MCOPRE_DIV_128    7
 310 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 311
 312 #define STM_RCC_CFGR_MCO        (24)
 313 # define STM_RCC_CFGR_MCO_DISABLE       0
 314
 315 #define STM_RCC_CFGR_PLLMUL     (18)
 316 #define  STM_RCC_CFGR_PLLMUL_2          0
 317 #define  STM_RCC_CFGR_PLLMUL_3          1
 318 #define  STM_RCC_CFGR_PLLMUL_4          2
 319 #define  STM_RCC_CFGR_PLLMUL_5          3
 320 #define  STM_RCC_CFGR_PLLMUL_6          4
 321 #define  STM_RCC_CFGR_PLLMUL_7          5
 322 #define  STM_RCC_CFGR_PLLMUL_8          6
 323 #define  STM_RCC_CFGR_PLLMUL_9          7
 324 #define  STM_RCC_CFGR_PLLMUL_10         8
 325 #define  STM_RCC_CFGR_PLLMUL_11         9
 326 #define  STM_RCC_CFGR_PLLMUL_12         10
 327 #define  STM_RCC_CFGR_PLLMUL_13         11
 328 #define  STM_RCC_CFGR_PLLMUL_14         12
 329 #define  STM_RCC_CFGR_PLLMUL_15         13
 330 #define  STM_RCC_CFGR_PLLMUL_16         14
 331 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 332
 333 #define STM_RCC_CFGR_PLLXTPRE   (17)
 334
 335 #define STM_RCC_CFGR_PLLSRC     (15)
 336 # define STM_RCC_CFGR_PLLSRC_HSI_DIV_2  0
 337 # define STM_RCC_CFGR_PLLSRC_HSI        1
 338 # define STM_RCC_CFGR_PLLSRC_HSE        2
 339 # define STM_RCC_CFGR_PLLSRC_HSI48      3
 340
 341 #define STM_RCC_CFGR_ADCPRE     (14)
 342
 343 #define STM_RCC_CFGR_PPRE       (8)
 344 #define  STM_RCC_CFGR_PPRE_DIV_1        0
 345 #define  STM_RCC_CFGR_PPRE_DIV_2        4
 346 #define  STM_RCC_CFGR_PPRE_DIV_4        5
 347 #define  STM_RCC_CFGR_PPRE_DIV_8        6
 348 #define  STM_RCC_CFGR_PPRE_DIV_16       7
 349 #define  STM_RCC_CFGR_PPRE_MASK         7
 350
 351 #define STM_RCC_CFGR_HPRE       (4)
 352 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 353 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 354 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 355 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 356 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 357 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 358 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 359 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 360 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 361 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 362
 363 #define STM_RCC_CFGR_SWS        (2)
 364 #define  STM_RCC_CFGR_SWS_HSI           0
 365 #define  STM_RCC_CFGR_SWS_HSE           1
 366 #define  STM_RCC_CFGR_SWS_PLL           2
 367 #define  STM_RCC_CFGR_SWS_HSI48         3
 368 #define  STM_RCC_CFGR_SWS_MASK          3
 369
 370 #define STM_RCC_CFGR_SW         (0)
 371 #define  STM_RCC_CFGR_SW_HSI            0
 372 #define  STM_RCC_CFGR_SW_HSE            1
 373 #define  STM_RCC_CFGR_SW_PLL            2
 374 #define  STM_RCC_CFGR_SW_HSI48          3
 375 #define  STM_RCC_CFGR_SW_MASK           3
 376
 377 #define STM_RCC_APB2RSTR_DBGMCURST      22
 378 #define STM_RCC_APB2RSTR_TIM17RST       18
 379 #define STM_RCC_APB2RSTR_TIM16RST       17
 380 #define STM_RCC_APB2RSTR_TIM15RST       16
 381 #define STM_RCC_APB2RSTR_USART1RST      14
 382 #define STM_RCC_APB2RSTR_SPI1RST        12
 383 #define STM_RCC_APB2RSTR_TIM1RST        11
 384 #define STM_RCC_APB2RSTR_ADCRST         9
 385 #define STM_RCC_APB2RSTR_USART8RST      7
 386 #define STM_RCC_APB2RSTR_USART7RST      6
 387 #define STM_RCC_APB2RSTR_USART6RST      5
 388 #define STM_RCC_APB2RSTR_SYSCFGRST      1
 389
 390 #define STM_RCC_APB1RSTR_CECRST         30
 391 #define STM_RCC_APB1RSTR_DACRST         29
 392 #define STM_RCC_APB1RSTR_PWRRST         28
 393 #define STM_RCC_APB1RSTR_CRSRST         27
 394 #define STM_RCC_APB1RSTR_CANRST         25
 395 #define STM_RCC_APB1RSTR_USBRST         23
 396 #define STM_RCC_APB1RSTR_I2C2RST        22
 397 #define STM_RCC_APB1RSTR_I1C1RST        21
 398 #define STM_RCC_APB1RSTR_USART5RST      20
 399 #define STM_RCC_APB1RSTR_USART4RST      19
 400 #define STM_RCC_APB1RSTR_USART3RST      18
 401 #define STM_RCC_APB1RSTR_USART2RST      17
 402 #define STM_RCC_APB1RSTR_SPI2RST        14
 403 #define STM_RCC_APB1RSTR_WWDGRST        11
 404 #define STM_RCC_APB1RSTR_TIM14RST       8
 405 #define STM_RCC_APB1RSTR_TIM7RST        5
 406 #define STM_RCC_APB1RSTR_TIM6RST        4
 407 #define STM_RCC_APB1RSTR_TIM3RST        1
 408 #define STM_RCC_APB1RSTR_TIM2RST        0
 409
 410 #define STM_RCC_AHBENR_TSCEN    24
 411 #define STM_RCC_AHBENR_IOPFEN   22
 412 #define STM_RCC_AHBENR_IOPEEN   21
 413 #define STM_RCC_AHBENR_IOPDEN   20
 414 #define STM_RCC_AHBENR_IOPCEN   19
 415 #define STM_RCC_AHBENR_IOPBEN   18
 416 #define STM_RCC_AHBENR_IOPAEN   17
 417 #define STM_RCC_AHBENR_CRCEN    6
 418 #define STM_RCC_AHBENR_FLITFEN  4
 419 #define STM_RCC_AHBENR_SRAMEN   2
 420 #define STM_RCC_AHBENR_DMA2EN   1
 421 #define STM_RCC_AHBENR_DMAEN    0
 422
 423 #define STM_RCC_APB2ENR_DBGMCUEN        22
 424 #define STM_RCC_APB2ENR_TIM17EN         18
 425 #define STM_RCC_APB2ENR_TIM16EN         17
 426 #define STM_RCC_APB2ENR_TIM15EN         16
 427 #define STM_RCC_APB2ENR_USART1EN        14
 428 #define STM_RCC_APB2ENR_SPI1EN          12
 429 #define STM_RCC_APB2ENR_TIM1EN          11
 430 #define STM_RCC_APB2ENR_ADCEN           9
 431 #define STM_RCC_APB2ENR_USART8EN        7
 432 #define STM_RCC_APB2ENR_USART7EN        6
 433 #define STM_RCC_APB2ENR_USART6EN        5
 434 #define STM_RCC_APB2ENR_SYSCFGCOMPEN    0
 435
 436 #define STM_RCC_APB1ENR_CECEN           30
 437 #define STM_RCC_APB1ENR_DACEN           29
 438 #define STM_RCC_APB1ENR_PWREN           28
 439 #define STM_RCC_APB1ENR_CRSEN           27
 440 #define STM_RCC_APB1ENR_CANEN           25
 441 #define STM_RCC_APB1ENR_USBEN           23
 442 #define STM_RCC_APB1ENR_I2C2EN          22
 443 #define STM_RCC_APB1ENR_IC21EN          21
 444 #define STM_RCC_APB1ENR_USART5EN        20
 445 #define STM_RCC_APB1ENR_USART4EN        19
 446 #define STM_RCC_APB1ENR_USART3EN        18
 447 #define STM_RCC_APB1ENR_USART2EN        17
 448 #define STM_RCC_APB1ENR_SPI2EN          14
 449 #define STM_RCC_APB1ENR_WWDGEN          11
 450 #define STM_RCC_APB1ENR_TIM14EN         8
 451 #define STM_RCC_APB1ENR_TIM7EN          5
 452 #define STM_RCC_APB1ENR_TIM6EN          4
 453 #define STM_RCC_APB1ENR_TIM3EN          1
 454 #define STM_RCC_APB1ENR_TIM2EN          0
 455
 456 #define STM_RCC_CSR_LPWRRSTF            (31)
 457 #define STM_RCC_CSR_WWDGRSTF            (30)
 458 #define STM_RCC_CSR_IWDGRSTF            (29)
 459 #define STM_RCC_CSR_SFTRSTF             (28)
 460 #define STM_RCC_CSR_PORRSTF             (27)
 461 #define STM_RCC_CSR_PINRSTF             (26)
 462 #define STM_RCC_CSR_OBLRSTF             (25)
 463 #define STM_RCC_CSR_RMVF                (24)
 464 #define STM_RCC_CSR_V18PWRRSTF          (23)
 465 #define STM_RCC_CSR_LSIRDY              (1)
 466 #define STM_RCC_CSR_LSION               (0)
 467
 468 #define STM_RCC_CR2_HSI48CAL            24
 469 #define STM_RCC_CR2_HSI48RDY            17
 470 #define STM_RCC_CR2_HSI48ON             16
 471 #define STM_RCC_CR2_HSI14CAL            8
 472 #define STM_RCC_CR2_HSI14TRIM           3
 473 #define STM_RCC_CR2_HSI14DIS            2
 474 #define STM_RCC_CR2_HSI14RDY            1
 475 #define STM_RCC_CR2_HSI14ON             0
 476
 477 #define STM_RCC_CFGR3_USART3SW          18
 478 #define STM_RCC_CFGR3_USART2SW          16
 479 #define STM_RCC_CFGR3_ADCSW             8
 480 #define STM_RCC_CFGR3_USBSW             7
 481 #define STM_RCC_CFGR3_CECSW             6
 482 #define STM_RCC_CFGR3_I2C1SW            4
 483 #define STM_RCC_CFGR3_USART1SW          0
 484
 485 struct stm_crs {
 486         vuint32_t       cr;
 487         vuint32_t       cfgr;
 488         vuint32_t       isr;
 489         vuint32_t       icr;
 490 };
 491
 492 extern struct stm_crs stm_crs;
 493
 494 #define STM_CRS_CR_TRIM         8
 495 #define STM_CRS_CR_SWSYNC       7
 496 #define STM_CRS_CR_AUTOTRIMEN   6
 497 #define STM_CRS_CR_CEN          5
 498 #define STM_CRS_CR_ESYNCIE      3
 499 #define STM_CRS_CR_ERRIE        2
 500 #define STM_CRS_CR_SYNCWARNIE   1
 501 #define STM_CRS_CR_SYNCOKIE     0
 502
 503 #define STM_CRS_CFGR_SYNCPOL    31
 504 #define STM_CRS_CFGR_SYNCSRC    28
 505 #define  STM_CRS_CFGR_SYNCSRC_GPIO      0
 506 #define  STM_CRS_CFGR_SYNCSRC_LSE       1
 507 #define  STM_CRS_CFGR_SYNCSRC_USB       2
 508 #define STM_CRS_CFGR_SYNCDIV    24
 509 #define  STM_CRS_CFGR_SYNCDIV_1         0
 510 #define  STM_CRS_CFGR_SYNCDIV_2         1
 511 #define  STM_CRS_CFGR_SYNCDIV_4         2
 512 #define  STM_CRS_CFGR_SYNCDIV_8         3
 513 #define  STM_CRS_CFGR_SYNCDIV_16        4
 514 #define  STM_CRS_CFGR_SYNCDIV_32        5
 515 #define  STM_CRS_CFGR_SYNCDIV_64        6
 516 #define  STM_CRS_CFGR_SYNCDIV_128       7
 517 #define STM_CRS_CFGR_FELIM      16
 518 #define STM_CRS_CFGR_RELOAD     0
 519
 520 #define STM_CRS_ISR_FECAP       16
 521 #define STM_CRS_ISR_FEDIR       15
 522 #define STM_CRS_ISR_TRIMOVF     10
 523 #define STM_CRS_ISR_SYNCMISS    9
 524 #define STM_CRS_ISR_SYNCERR     8
 525 #define STM_CRS_ISR_ESYNCF      3
 526 #define STM_CRS_ISR_ERRF        2
 527 #define STM_CRS_ISR_SYNCWARNF   1
 528 #define STM_CRS_ISR_SYNCOKF     0
 529
 530 #define STM_CRS_ICR_ESYNCC      3
 531 #define STM_CRS_ICR_ERRC        2
 532 #define STM_CRS_ICR_SYNCWARNC   1
 533 #define STM_CRS_ICR_SYNCOKC     0
 534
 535 struct stm_pwr {
 536         vuint32_t       cr;
 537         vuint32_t       csr;
 538 };
 539
 540 extern struct stm_pwr stm_pwr;
 541
 542 #define STM_PWR_CR_DBP          (8)
 543
 544 #define STM_PWR_CR_PLS          (5)
 545 #define  STM_PWR_CR_PLS_2_0     0
 546 #define  STM_PWR_CR_PLS_2_1     1
 547 #define  STM_PWR_CR_PLS_2_2     2
 548 #define  STM_PWR_CR_PLS_2_3     3
 549 #define  STM_PWR_CR_PLS_2_4     4
 550 #define  STM_PWR_CR_PLS_2_5     5
 551 #define  STM_PWR_CR_PLS_2_6     6
 552 #define  STM_PWR_CR_PLS_EXT     7
 553 #define  STM_PWR_CR_PLS_MASK    7
 554
 555 #define STM_PWR_CR_PVDE         (4)
 556 #define STM_PWR_CR_CSBF         (3)
 557 #define STM_PWR_CR_CWUF         (2)
 558 #define STM_PWR_CR_PDDS         (1)
 559 #define STM_PWR_CR_LPSDSR       (0)
 560
 561 #define STM_PWR_CSR_EWUP3       (10)
 562 #define STM_PWR_CSR_EWUP2       (9)
 563 #define STM_PWR_CSR_EWUP1       (8)
 564 #define STM_PWR_CSR_REGLPF      (5)
 565 #define STM_PWR_CSR_VOSF        (4)
 566 #define STM_PWR_CSR_VREFINTRDYF (3)
 567 #define STM_PWR_CSR_PVDO        (2)
 568 #define STM_PWR_CSR_SBF         (1)
 569 #define STM_PWR_CSR_WUF         (0)
 570
 571 /* The SYSTICK starts at 0xe000e010 */
 572
 573 struct stm_systick {
 574         vuint32_t       csr;
 575         vuint32_t       rvr;
 576         vuint32_t       cvr;
 577         vuint32_t       calib;
 578 };
 579
 580 extern struct stm_systick stm_systick;
 581
 582 #define STM_SYSTICK_CSR_ENABLE          0
 583 #define STM_SYSTICK_CSR_TICKINT         1
 584 #define STM_SYSTICK_CSR_CLKSOURCE       2
 585 #define  STM_SYSTICK_CSR_CLKSOURCE_EXTERNAL             0
 586 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               1
 587 #define STM_SYSTICK_CSR_COUNTFLAG       16
 588
 589 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 590
 591 struct stm_nvic {
 592         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 593
 594         uint8_t         _unused020[0x080 - 0x004];
 595
 596         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 597
 598         uint8_t         _unused0a0[0x100 - 0x084];
 599
 600         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 601
 602         uint8_t         _unused120[0x180 - 0x104];
 603
 604         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 605
 606         uint8_t         _unused1a0[0x300 - 0x184];
 607
 608         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 609 };
 610
 611 extern struct stm_nvic stm_nvic;
 612
 613 #define IRQ_MASK(irq)   (1 << (irq))
 614 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 615
 616 static inline void
 617 stm_nvic_set_enable(int irq) {
 618         stm_nvic.iser = IRQ_MASK(irq);
 619 }
 620
 621 static inline void
 622 stm_nvic_clear_enable(int irq) {
 623         stm_nvic.icer = IRQ_MASK(irq);
 624 }
 625
 626 static inline int
 627 stm_nvic_enabled(int irq) {
 628         return IRQ_BOOL(stm_nvic.iser, irq);
 629 }
 630
 631 static inline void
 632 stm_nvic_set_pending(int irq) {
 633         stm_nvic.ispr = IRQ_MASK(irq);
 634 }
 635
 636 static inline void
 637 stm_nvic_clear_pending(int irq) {
 638         stm_nvic.icpr = IRQ_MASK(irq);
 639 }
 640
 641 static inline int
 642 stm_nvic_pending(int irq) {
 643         return IRQ_BOOL(stm_nvic.ispr, irq);
 644 }
 645
 646 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 647 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 648 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 649
 650 static inline void
 651 stm_nvic_set_priority(int irq, uint8_t prio) {
 652         int             n = IRQ_PRIO_REG(irq);
 653         uint32_t        v;
 654
 655         v = stm_nvic.ipr[n];
 656         v &= ~IRQ_PRIO_MASK(irq);
 657         v |= (prio) << IRQ_PRIO_BIT(irq);
 658         stm_nvic.ipr[n] = v;
 659 }
 660
 661 static inline uint8_t
 662 stm_nvic_get_priority(int irq) {
 663         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 664 }
 665
 666 struct stm_scb {
 667         vuint32_t       cpuid;
 668         vuint32_t       icsr;
 669         vuint32_t       vtor;
 670         vuint32_t       aircr;
 671
 672         vuint32_t       scr;
 673         vuint32_t       ccr;
 674         vuint32_t       shpr1;
 675         vuint32_t       shpr2;
 676
 677         vuint32_t       shpr3;
 678         vuint32_t       shcrs;
 679         vuint32_t       cfsr;
 680         vuint32_t       hfsr;
 681
 682         uint32_t        unused_30;
 683         vuint32_t       mmfar;
 684         vuint32_t       bfar;
 685 };
 686
 687 extern struct stm_scb stm_scb;
 688
 689 #define STM_SCB_AIRCR_VECTKEY           16
 690 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 691 #define STM_SCB_AIRCR_PRIGROUP          8
 692 #define STM_SCB_AIRCR_SYSRESETREQ       2
 693 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 694 #define STM_SCB_AIRCR_VECTRESET         0
 695
 696 #define isr(name) void stm_ ## name ## _isr(void);
 697
 698 isr(nmi)
 699 isr(hardfault)
 700 isr(memmanage)
 701 isr(busfault)
 702 isr(usagefault)
 703 isr(svc)
 704 isr(debugmon)
 705 isr(pendsv)
 706 isr(systick)
 707 isr(wwdg)
 708 isr(pvd)
 709 isr(tamper_stamp)
 710 isr(rtc_wkup)
 711 isr(flash)
 712 isr(rcc)
 713 isr(exti0)
 714 isr(exti1)
 715 isr(exti2)
 716 isr(exti3)
 717 isr(exti4)
 718 isr(dma1_channel1)
 719 isr(dma1_channel2)
 720 isr(dma1_channel3)
 721 isr(dma1_channel4)
 722 isr(dma1_channel5)
 723 isr(dma1_channel6)
 724 isr(dma1_channel7)
 725 isr(adc1)
 726 isr(usb_hp)
 727 isr(usb_lp)
 728 isr(dac)
 729 isr(comp)
 730 isr(exti9_5)
 731 isr(lcd)
 732 isr(tim9)
 733 isr(tim10)
 734 isr(tim11)
 735 isr(tim2)
 736 isr(tim3)
 737 isr(tim4)
 738 isr(i2c1_ev)
 739 isr(i2c1_er)
 740 isr(i2c2_ev)
 741 isr(i2c2_er)
 742 isr(spi1)
 743 isr(spi2)
 744 isr(usart1)
 745 isr(usart2)
 746 isr(usart3)
 747 isr(exti15_10)
 748 isr(rtc_alarm)
 749 isr(usb_fs_wkup)
 750 isr(tim6)
 751 isr(tim7)
 752
 753 #undef isr
 754
 755 #define STM_ISR_WWDG_POS                0
 756 #define STM_ISR_PVD_VDDIO2_POS          1
 757 #define STM_ISR_RTC_POS                 2
 758 #define STM_ISR_FLASH_POS               3
 759 #define STM_ISR_RCC_CRS_POS             4
 760 #define STM_ISR_EXTI0_1_POS             5
 761 #define STM_ISR_EXTI2_3_POS             6
 762 #define STM_ISR_EXTI4_15_POS            7
 763 #define STM_ISR_TSC_POS                 8
 764 #define STM_ISR_DMA_CH1_POS             9
 765 #define STM_ISR_DMA_CH2_3_DMA2_CH1_2_POS        10
 766 #define STM_ISR_DMA_CH44_5_6_7_DMA2_CH3_4_5_POS 11
 767 #define STM_ISR_ADC_COMP_POS            12
 768 #define STM_ISR_TIM1_BRK_UP_TRG_COM_POS 13
 769 #define STM_ISR_TIM1_CC_POS             14
 770 #define STM_ISR_TIM2_POS                15
 771 #define STM_ISR_TIM3_POS                16
 772 #define STM_ISR_TIM6_DAC_POS            17
 773 #define STM_ISR_TIM7_POS                18
 774 #define STM_ISR_TIM14_POS               19
 775 #define STM_ISR_TIM15_POS               20
 776 #define STM_ISR_TIM16_POS               21
 777 #define STM_ISR_TIM17_POS               22
 778 #define STM_ISR_I2C1_POS                23
 779 #define STM_ISR_I2C2_POS                24
 780 #define STM_ISR_SPI1_POS                25
 781 #define STM_ISR_SPI2_POS                26
 782 #define STM_ISR_USART1_POS              27
 783 #define STM_ISR_USART2_POS              28
 784 #define STM_ISR_UASART3_4_5_6_7_8_POS   29
 785 #define STM_ISR_CEC_CAN_POS             30
 786 #define STM_ISR_USB_POS                 31
 787
 788 struct stm_syscfg {
 789         vuint32_t       cfgr1;
 790         vuint32_t       exticr[4];
 791         vuint32_t       cfgr2;
 792 };
 793
 794 extern struct stm_syscfg stm_syscfg;
 795
 796 #define STM_SYSCFG_CFGR1_TIM3_DMA_RMP   30
 797 #define STM_SYSCFG_CFGR1_TIM2_DMA_RMP   29
 798 #define STM_SYSCFG_CFGR1_TIM1_DMA_RMP   28
 799 #define STM_SYSCFG_CFGR1_I2C1_DMA_RMP   27
 800 #define STM_SYSCFG_CFGR1_USART3_DMA_RMP 26
 801 #define STM_SYSCFG_CFGR1_USART2_DMA_RMP 25
 802 #define STM_SYSCFG_CFGR1_SPI2_DMA_RMP   24
 803 #define STM_SYSCFG_CFGR1_I2C_PA10_FMP   23
 804 #define STM_SYSCFG_CFGR1_I2C_PA9_FMP    22
 805 #define STM_SYSCFG_CFGR1_I2C2_FMP       21
 806 #define STM_SYSCFG_CFGR1_I2C1_FMP       20
 807 #define STM_SYSCFG_CFGR1_I2C_PB9_FMP    19
 808 #define STM_SYSCFG_CFGR1_I2C_PB8_FMP    18
 809 #define STM_SYSCFG_CFGR1_I2C_PB7_FMP    17
 810 #define STM_SYSCFG_CFGR1_I2C_PB6_FMP    16
 811 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP2 14
 812 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP2 13
 813 #define STM_SYSCFG_CFGR1_TIM17_DMA_RMP  12
 814 #define STM_SYSCFG_CFGR1_TIM16_DMA_RMP  11
 815 #define STM_SYSCFG_CFGR1_USART1_RX_DMA_RMP      10
 816 #define STM_SYSCFG_CFGR1_USART1_TX_DMA_RMP      9
 817 #define STM_SYSCFG_CFGR1_ADC_DMA_RMP            8
 818 #define STM_SYSCFG_CFGR1_IRDA_ENV_SEL   6
 819 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_TIMER16  0
 820 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART1   1
 821 #define  STM_SYSCFG_CFGR1_IRDA_ENV_SEL_USART4   2
 822 #define STM_SYSCFG_CFGR1_PA11_PA12_RMP  4
 823 #define STM_SYSCFG_CFGR1_MEM_MODE       0
 824 #define  STM_SYSCFG_CFGR1_MEM_MODE_MAIN_FLASH   0
 825 #define  STM_SYSCFG_CFGR1_MEM_MODE_SYSTEM_FLASH 1
 826 #define  STM_SYSCFG_CFGR1_MEM_MODE_SRAM         3
 827 #define  STM_SYSCFG_CFGR1_MEM_MODE_MASK         3
 828
 829 #if 0
 830 static inline void
 831 stm_exticr_set(struct stm_gpio *gpio, int pin) {
 832         uint8_t reg = pin >> 2;
 833         uint8_t shift = (pin & 3) << 2;
 834         uint8_t val = 0;
 835
 836         /* Enable SYSCFG */
 837         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 838
 839         if (gpio == &stm_gpioa)
 840                 val = STM_SYSCFG_EXTICR_PA;
 841         else if (gpio == &stm_gpiob)
 842                 val = STM_SYSCFG_EXTICR_PB;
 843         else if (gpio == &stm_gpioc)
 844                 val = STM_SYSCFG_EXTICR_PC;
 845         else if (gpio == &stm_gpiof)
 846                 val = STM_SYSCFG_EXTICR_PF;
 847
 848         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
 849 }
 850 #endif
 851
 852
 853 struct stm_dma_channel {
 854         vuint32_t       ccr;
 855         vuint32_t       cndtr;
 856         vvoid_t         cpar;
 857         vvoid_t         cmar;
 858         vuint32_t       reserved;
 859 };
 860
 861 #define STM_NUM_DMA     6
 862
 863 struct stm_dma {
 864         vuint32_t               isr;
 865         vuint32_t               ifcr;
 866         struct stm_dma_channel  channel[STM_NUM_DMA];
 867 };
 868
 869 extern struct stm_dma stm_dma;
 870
 871 /* DMA channels go from 1 to 6, instead of 0 to 5 (sigh)
 872  */
 873
 874 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 875
 876 #define STM_DMA_ISR(index)              ((index) << 2)
 877 #define STM_DMA_ISR_MASK                        0xf
 878 #define STM_DMA_ISR_TEIF                        3
 879 #define STM_DMA_ISR_HTIF                        2
 880 #define STM_DMA_ISR_TCIF                        1
 881 #define STM_DMA_ISR_GIF                         0
 882
 883 #define STM_DMA_IFCR(index)             ((index) << 2)
 884 #define STM_DMA_IFCR_MASK                       0xf
 885 #define STM_DMA_IFCR_CTEIF                      3
 886 #define STM_DMA_IFCR_CHTIF                      2
 887 #define STM_DMA_IFCR_CTCIF                      1
 888 #define STM_DMA_IFCR_CGIF                       0
 889
 890 #define STM_DMA_CCR_MEM2MEM             (14)
 891
 892 #define STM_DMA_CCR_PL                  (12)
 893 #define  STM_DMA_CCR_PL_LOW                     (0)
 894 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 895 #define  STM_DMA_CCR_PL_HIGH                    (2)
 896 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 897 #define  STM_DMA_CCR_PL_MASK                    (3)
 898
 899 #define STM_DMA_CCR_MSIZE               (10)
 900 #define  STM_DMA_CCR_MSIZE_8                    (0)
 901 #define  STM_DMA_CCR_MSIZE_16                   (1)
 902 #define  STM_DMA_CCR_MSIZE_32                   (2)
 903 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 904
 905 #define STM_DMA_CCR_PSIZE               (8)
 906 #define  STM_DMA_CCR_PSIZE_8                    (0)
 907 #define  STM_DMA_CCR_PSIZE_16                   (1)
 908 #define  STM_DMA_CCR_PSIZE_32                   (2)
 909 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 910
 911 #define STM_DMA_CCR_MINC                (7)
 912 #define STM_DMA_CCR_PINC                (6)
 913 #define STM_DMA_CCR_CIRC                (5)
 914 #define STM_DMA_CCR_DIR                 (4)
 915 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 916 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 917 #define STM_DMA_CCR_TEIE                (3)
 918 #define STM_DMA_CCR_HTIE                (2)
 919 #define STM_DMA_CCR_TCIE                (1)
 920 #define STM_DMA_CCR_EN                  (0)
 921
 922 /* DMA channel assignments. When a peripheral has multiple channels
 923  * (indicated with _<number>), then it can be configured to either
 924  * channel using syscfg.cfgr1
 925  */
 926
 927 #define STM_DMA_CHANNEL_ADC_1           1
 928 #define STM_DMA_CHANNEL_ADC_2           2
 929
 930 #define STM_DMA_CHANNEL_SPI1_RX         2
 931 #define STM_DMA_CHANNEL_SPI1_TX         3
 932
 933 #define STM_DMA_CHANNEL_SPI2_RX         4
 934 #define STM_DMA_CHANNEL_SPI2_TX         5
 935
 936 #define STM_DMA_CHANNEL_USART1_TX_1     2
 937 #define STM_DMA_CHANNEL_USART1_RX_1     3
 938 #define STM_DMA_CHANNEL_USART1_TX_2     4
 939 #define STM_DMA_CHANNEL_USART1_RX_2     5
 940
 941 #define STM_DMA_CHANNEL_USART2_RX       4
 942 #define STM_DMA_CHANNEL_USART2_TX       5
 943
 944 #define STM_DMA_CHANNEL_I2C1_TX         2
 945 #define STM_DMA_CHANNEL_I2C1_RX         3
 946
 947 #define STM_DMA_CHANNEL_I2C2_TX         4
 948 #define STM_DMA_CHANNEL_I2C2_RX         5
 949
 950 #define STM_DMA_CHANNEL_TIM1_CH1        2
 951 #define STM_DMA_CHANNEL_TIM1_CH2        3
 952 #define STM_DMA_CHANNEL_TIM1_CH4        4
 953 #define STM_DMA_CHANNEL_TIM1_TRIG       4
 954 #define STM_DMA_CHANNEL_TIM1_COM        4
 955 #define STM_DMA_CHANNEL_TIM1_CH3        5
 956 #define STM_DMA_CHANNEL_TIM1_UP         5
 957
 958 #define STM_DMA_CHANNEL_TIM2_CH3        1
 959 #define STM_DMA_CHANNEL_TIM2_UP         2
 960 #define STM_DMA_CHANNEL_TIM2_CH2        3
 961 #define STM_DMA_CHANNEL_TIM2_CH4        4
 962 #define STM_DMA_CHANNEL_TIM2_CH1        5
 963
 964 #define STM_DMA_CHANNEL_TIM3_CH3        2
 965 #define STM_DMA_CHANNEL_TIM3_CH4        3
 966 #define STM_DMA_CHANNEL_TIM3_UP         3
 967 #define STM_DMA_CHANNEL_TIM3_CH1        4
 968 #define STM_DMA_CHANNEL_TIM3_TRIG       4
 969
 970 #define STM_DMA_CHANNEL_TIM6_UP_DAC     2
 971
 972 #define STM_DMA_CHANNEL_TIM15_CH1       5
 973 #define STM_DMA_CHANNEL_TIM15_UP        5
 974 #define STM_DMA_CHANNEL_TIM15_TRIG      5
 975 #define STM_DMA_CHANNEL_TIM15_COM       5
 976
 977 #define STM_DMA_CHANNEL_TIM16_CH1_1     3
 978 #define STM_DMA_CHANNEL_TIM16_UP_1      3
 979 #define STM_DMA_CHANNEL_TIM16_CH1_2     4
 980 #define STM_DMA_CHANNEL_TIM16_UP_2      4
 981
 982 #define STM_DMA_CHANNEL_TIM17_CH1_1     1
 983 #define STM_DMA_CHANNEL_TIM17_UP_1      1
 984 #define STM_DMA_CHANNEL_TIM17_CH1_2     2
 985 #define STM_DMA_CHANNEL_TIM17_UP_2      2
 986
 987 /*
 988  * Only spi channel 1 and 2 can use DMA
 989  */
 990 #define STM_NUM_SPI     2
 991
 992 struct stm_spi {
 993         vuint32_t       cr1;
 994         vuint32_t       cr2;
 995         vuint32_t       sr;
 996         vuint32_t       dr;
 997         vuint32_t       crcpr;
 998         vuint32_t       rxcrcr;
 999         vuint32_t       txcrcr;
1000 };
1001
1002 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1003
1004 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1005  */
1006
1007 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1008
1009 #define STM_SPI_CR1_BIDIMODE            15
1010 #define STM_SPI_CR1_BIDIOE              14
1011 #define STM_SPI_CR1_CRCEN               13
1012 #define STM_SPI_CR1_CRCNEXT             12
1013 #define STM_SPI_CR1_DFF                 11
1014 #define STM_SPI_CR1_RXONLY              10
1015 #define STM_SPI_CR1_SSM                 9
1016 #define STM_SPI_CR1_SSI                 8
1017 #define STM_SPI_CR1_LSBFIRST            7
1018 #define STM_SPI_CR1_SPE                 6
1019 #define STM_SPI_CR1_BR                  3
1020 #define  STM_SPI_CR1_BR_PCLK_2                  0
1021 #define  STM_SPI_CR1_BR_PCLK_4                  1
1022 #define  STM_SPI_CR1_BR_PCLK_8                  2
1023 #define  STM_SPI_CR1_BR_PCLK_16                 3
1024 #define  STM_SPI_CR1_BR_PCLK_32                 4
1025 #define  STM_SPI_CR1_BR_PCLK_64                 5
1026 #define  STM_SPI_CR1_BR_PCLK_128                6
1027 #define  STM_SPI_CR1_BR_PCLK_256                7
1028 #define  STM_SPI_CR1_BR_MASK                    7
1029
1030 #define STM_SPI_CR1_MSTR                2
1031 #define STM_SPI_CR1_CPOL                1
1032 #define STM_SPI_CR1_CPHA                0
1033
1034 #define STM_SPI_CR2_TXEIE       7
1035 #define STM_SPI_CR2_RXNEIE      6
1036 #define STM_SPI_CR2_ERRIE       5
1037 #define STM_SPI_CR2_SSOE        2
1038 #define STM_SPI_CR2_TXDMAEN     1
1039 #define STM_SPI_CR2_RXDMAEN     0
1040
1041 #define STM_SPI_SR_BSY          7
1042 #define STM_SPI_SR_OVR          6
1043 #define STM_SPI_SR_MODF         5
1044 #define STM_SPI_SR_CRCERR       4
1045 #define STM_SPI_SR_TXE          1
1046 #define STM_SPI_SR_RXNE         0
1047
1048 struct stm_adc {
1049         vuint32_t       isr;
1050         vuint32_t       ier;
1051         vuint32_t       cr;
1052         vuint32_t       cfgr1;
1053
1054         vuint32_t       cfgr2;
1055         vuint32_t       smpr;
1056         vuint32_t       r_18;
1057         vuint32_t       r_1c;
1058
1059         vuint32_t       tr;
1060         vuint32_t       r_24;
1061         vuint32_t       chselr;
1062         vuint32_t       r_2c;
1063
1064         vuint32_t       r_30[4];
1065
1066         vuint32_t       dr;
1067
1068         uint8_t         r_44[0x308 - 0x44];
1069         vuint32_t       ccr;
1070 };
1071
1072 extern struct stm_adc stm_adc;
1073
1074 #define STM_ADC_ISR_AWD         7
1075 #define STM_ADC_ISR_OVR         4
1076 #define STM_ADC_ISR_EOSEQ       3
1077 #define STM_ADC_ISR_EOC         2
1078 #define STM_ADC_ISR_EOSMP       1
1079 #define STM_ADC_ISR_ADRDY       0
1080
1081 #define STM_ADC_IER_AWDIE       7
1082 #define STM_ADC_IER_OVRIE       4
1083 #define STM_ADC_IER_EOSEQIE     3
1084 #define STM_ADC_IER_EOCIE       2
1085 #define STM_ADC_IER_EOSMPIE     1
1086 #define STM_ADC_IER_ADRDYIE     0
1087
1088 #define STM_ADC_CR_ADCAL        31
1089 #define STM_ADC_CR_ADSTP        4
1090 #define STM_ADC_CR_ADSTART      2
1091 #define STM_ADC_CR_ADDIS        1
1092 #define STM_ADC_CR_ADEN         0
1093
1094 #define STM_ADC_CFGR1_AWDCH     26
1095 #define STM_ADC_CFGR1_AWDEN     23
1096 #define STM_ADC_CFGR1_AWDSGL    22
1097 #define STM_ADC_CFGR1_DISCEN    16
1098 #define STM_ADC_CFGR1_AUTOOFF   15
1099 #define STM_ADC_CFGR1_WAIT      14
1100 #define STM_ADC_CFGR1_CONT      13
1101 #define STM_ADC_CFGR1_OVRMOD    12
1102 #define STM_ADC_CFGR1_EXTEN     10
1103 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1104 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1105 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1106 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1107 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1108
1109 #define STM_ADC_CFGR1_EXTSEL    6
1110 #define STM_ADC_CFGR1_ALIGN     5
1111 #define STM_ADC_CFGR1_RES       3
1112 #define  STM_ADC_CFGR1_RES_12           0
1113 #define  STM_ADC_CFGR1_RES_10           1
1114 #define  STM_ADC_CFGR1_RES_8            2
1115 #define  STM_ADC_CFGR1_RES_6            3
1116 #define  STM_ADC_CFGR1_RES_MASK         3
1117 #define STM_ADC_CFGR1_SCANDIR   2
1118 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1119 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1120 #define STM_ADC_CFGR1_DMACFG    1
1121 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1122 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1123 #define STM_ADC_CFGR1_DMAEN     0
1124
1125 #define STM_ADC_CFGR2_CKMODE    30
1126 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1127 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1128 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1129
1130 #define STM_ADC_SMPR_SMP        0
1131 #define  STM_ADC_SMPR_SMP_1_5           0
1132 #define  STM_ADC_SMPR_SMP_7_5           1
1133 #define  STM_ADC_SMPR_SMP_13_5          2
1134 #define  STM_ADC_SMPR_SMP_28_5          3
1135 #define  STM_ADC_SMPR_SMP_41_5          4
1136 #define  STM_ADC_SMPR_SMP_55_5          5
1137 #define  STM_ADC_SMPR_SMP_71_5          6
1138 #define  STM_ADC_SMPR_SMP_239_5         7
1139
1140 #define STM_ADC_TR_HT           16
1141 #define STM_ADC_TR_LT           0
1142
1143 #define STM_ADC_CCR_VBATEN      24
1144 #define STM_ADC_CCR_TSEN        23
1145 #define STM_ADC_CCR_VREFEN      22
1146
1147 struct stm_cal {
1148         uint16_t        ts_cal_cold;    /* 30°C */
1149         uint16_t        vrefint_cal;
1150         uint16_t        unused_c0;
1151         uint16_t        ts_cal_hot;     /* 110°C */
1152 };
1153
1154 extern struct stm_cal   stm_cal;
1155
1156 #define stm_temp_cal_cold       30
1157 #define stm_temp_cal_hot        110
1158
1159 struct stm_dbgmcu {
1160         uint32_t        idcode;
1161 };
1162
1163 extern struct stm_dbgmcu        stm_dbgmcu;
1164
1165 static inline uint16_t
1166 stm_dev_id(void) {
1167         return stm_dbgmcu.idcode & 0xfff;
1168 }
1169
1170 struct stm_flash_size {
1171         uint16_t        f_size;
1172 };
1173
1174 extern struct stm_flash_size    stm_flash_size_04x;
1175
1176 /* Returns flash size in bytes */
1177 extern uint32_t
1178 stm_flash_size(void);
1179
1180 struct stm_device_id {
1181         uint32_t        u_id0;
1182         uint32_t        u_id1;
1183         uint32_t        u_id2;
1184 };
1185
1186 extern struct stm_device_id     stm_device_id;
1187
1188 #define STM_NUM_I2C     2
1189
1190 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1191
1192 struct stm_i2c {
1193         vuint32_t       cr1;
1194         vuint32_t       cr2;
1195         vuint32_t       oar1;
1196         vuint32_t       oar2;
1197         vuint32_t       dr;
1198         vuint32_t       sr1;
1199         vuint32_t       sr2;
1200         vuint32_t       ccr;
1201         vuint32_t       trise;
1202 };
1203
1204 extern struct stm_i2c stm_i2c1, stm_i2c2;
1205
1206 #define STM_I2C_CR1_SWRST       15
1207 #define STM_I2C_CR1_ALERT       13
1208 #define STM_I2C_CR1_PEC         12
1209 #define STM_I2C_CR1_POS         11
1210 #define STM_I2C_CR1_ACK         10
1211 #define STM_I2C_CR1_STOP        9
1212 #define STM_I2C_CR1_START       8
1213 #define STM_I2C_CR1_NOSTRETCH   7
1214 #define STM_I2C_CR1_ENGC        6
1215 #define STM_I2C_CR1_ENPEC       5
1216 #define STM_I2C_CR1_ENARP       4
1217 #define STM_I2C_CR1_SMBTYPE     3
1218 #define STM_I2C_CR1_SMBUS       1
1219 #define STM_I2C_CR1_PE          0
1220
1221 #define STM_I2C_CR2_LAST        12
1222 #define STM_I2C_CR2_DMAEN       11
1223 #define STM_I2C_CR2_ITBUFEN     10
1224 #define STM_I2C_CR2_ITEVTEN     9
1225 #define STM_I2C_CR2_ITERREN     8
1226 #define STM_I2C_CR2_FREQ        0
1227 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1228 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1229 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1230 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1231 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1232 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1233
1234 #define STM_I2C_SR1_SMBALERT    15
1235 #define STM_I2C_SR1_TIMEOUT     14
1236 #define STM_I2C_SR1_PECERR      12
1237 #define STM_I2C_SR1_OVR         11
1238 #define STM_I2C_SR1_AF          10
1239 #define STM_I2C_SR1_ARLO        9
1240 #define STM_I2C_SR1_BERR        8
1241 #define STM_I2C_SR1_TXE         7
1242 #define STM_I2C_SR1_RXNE        6
1243 #define STM_I2C_SR1_STOPF       4
1244 #define STM_I2C_SR1_ADD10       3
1245 #define STM_I2C_SR1_BTF         2
1246 #define STM_I2C_SR1_ADDR        1
1247 #define STM_I2C_SR1_SB          0
1248
1249 #define STM_I2C_SR2_PEC         8
1250 #define  STM_I2C_SR2_PEC_MASK   0xff00
1251 #define STM_I2C_SR2_DUALF       7
1252 #define STM_I2C_SR2_SMBHOST     6
1253 #define STM_I2C_SR2_SMBDEFAULT  5
1254 #define STM_I2C_SR2_GENCALL     4
1255 #define STM_I2C_SR2_TRA         2
1256 #define STM_I2C_SR2_BUSY        1
1257 #define STM_I2C_SR2_MSL         0
1258
1259 #define STM_I2C_CCR_FS          15
1260 #define STM_I2C_CCR_DUTY        14
1261 #define STM_I2C_CCR_CCR         0
1262 #define  STM_I2C_CCR_MASK       0x7ff
1263
1264 struct stm_tim234 {
1265         vuint32_t       cr1;
1266         vuint32_t       cr2;
1267         vuint32_t       smcr;
1268         vuint32_t       dier;
1269
1270         vuint32_t       sr;
1271         vuint32_t       egr;
1272         vuint32_t       ccmr1;
1273         vuint32_t       ccmr2;
1274
1275         vuint32_t       ccer;
1276         vuint32_t       cnt;
1277         vuint32_t       psc;
1278         vuint32_t       arr;
1279
1280         uint32_t        reserved_30;
1281         vuint32_t       ccr1;
1282         vuint32_t       ccr2;
1283         vuint32_t       ccr3;
1284
1285         vuint32_t       ccr4;
1286         uint32_t        reserved_44;
1287         vuint32_t       dcr;
1288         vuint32_t       dmar;
1289
1290         uint32_t        reserved_50;
1291 };
1292
1293 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1294
1295 #define STM_TIM234_CR1_CKD      8
1296 #define  STM_TIM234_CR1_CKD_1           0
1297 #define  STM_TIM234_CR1_CKD_2           1
1298 #define  STM_TIM234_CR1_CKD_4           2
1299 #define  STM_TIM234_CR1_CKD_MASK        3
1300 #define STM_TIM234_CR1_ARPE     7
1301 #define STM_TIM234_CR1_CMS      5
1302 #define  STM_TIM234_CR1_CMS_EDGE        0
1303 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1304 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1305 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1306 #define  STM_TIM234_CR1_CMS_MASK        3
1307 #define STM_TIM234_CR1_DIR      4
1308 #define  STM_TIM234_CR1_DIR_UP          0
1309 #define  STM_TIM234_CR1_DIR_DOWN        1
1310 #define STM_TIM234_CR1_OPM      3
1311 #define STM_TIM234_CR1_URS      2
1312 #define STM_TIM234_CR1_UDIS     1
1313 #define STM_TIM234_CR1_CEN      0
1314
1315 #define STM_TIM234_CR2_TI1S     7
1316 #define STM_TIM234_CR2_MMS      4
1317 #define  STM_TIM234_CR2_MMS_RESET               0
1318 #define  STM_TIM234_CR2_MMS_ENABLE              1
1319 #define  STM_TIM234_CR2_MMS_UPDATE              2
1320 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1321 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1322 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1323 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1324 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1325 #define  STM_TIM234_CR2_MMS_MASK                7
1326 #define STM_TIM234_CR2_CCDS     3
1327
1328 #define STM_TIM234_SMCR_ETP     15
1329 #define STM_TIM234_SMCR_ECE     14
1330 #define STM_TIM234_SMCR_ETPS    12
1331 #define  STM_TIM234_SMCR_ETPS_OFF               0
1332 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1333 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1334 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1335 #define  STM_TIM234_SMCR_ETPS_MASK              3
1336 #define STM_TIM234_SMCR_ETF     8
1337 #define  STM_TIM234_SMCR_ETF_NONE               0
1338 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1339 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1340 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1341 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1342 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1343 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1344 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1345 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1346 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1347 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1348 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1349 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1350 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1351 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1352 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1353 #define  STM_TIM234_SMCR_ETF_MASK               15
1354 #define STM_TIM234_SMCR_MSM     7
1355 #define STM_TIM234_SMCR_TS      4
1356 #define  STM_TIM234_SMCR_TS_ITR0                0
1357 #define  STM_TIM234_SMCR_TS_ITR1                1
1358 #define  STM_TIM234_SMCR_TS_ITR2                2
1359 #define  STM_TIM234_SMCR_TS_ITR3                3
1360 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1361 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1362 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1363 #define  STM_TIM234_SMCR_TS_ETRF                7
1364 #define  STM_TIM234_SMCR_TS_MASK                7
1365 #define STM_TIM234_SMCR_OCCS    3
1366 #define STM_TIM234_SMCR_SMS     0
1367 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1368 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1369 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1370 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1371 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1372 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1373 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1374 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1375 #define  STM_TIM234_SMCR_SMS_MASK               7
1376
1377 #define STM_TIM234_SR_CC4OF     12
1378 #define STM_TIM234_SR_CC3OF     11
1379 #define STM_TIM234_SR_CC2OF     10
1380 #define STM_TIM234_SR_CC1OF     9
1381 #define STM_TIM234_SR_TIF       6
1382 #define STM_TIM234_SR_CC4IF     4
1383 #define STM_TIM234_SR_CC3IF     3
1384 #define STM_TIM234_SR_CC2IF     2
1385 #define STM_TIM234_SR_CC1IF     1
1386 #define STM_TIM234_SR_UIF       0
1387
1388 #define STM_TIM234_EGR_TG       6
1389 #define STM_TIM234_EGR_CC4G     4
1390 #define STM_TIM234_EGR_CC3G     3
1391 #define STM_TIM234_EGR_CC2G     2
1392 #define STM_TIM234_EGR_CC1G     1
1393 #define STM_TIM234_EGR_UG       0
1394
1395 #define STM_TIM234_CCMR1_OC2CE  15
1396 #define STM_TIM234_CCMR1_OC2M   12
1397 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1398 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1399 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1400 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1401 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1402 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1403 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1404 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1405 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1406 #define STM_TIM234_CCMR1_OC2PE  11
1407 #define STM_TIM234_CCMR1_OC2FE  10
1408 #define STM_TIM234_CCMR1_CC2S   8
1409 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1410 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1411 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1412 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1413 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1414
1415 #define STM_TIM234_CCMR1_OC1CE  7
1416 #define STM_TIM234_CCMR1_OC1M   4
1417 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1418 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1419 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1420 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1421 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1422 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1423 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1424 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1425 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1426 #define STM_TIM234_CCMR1_OC1PE  11
1427 #define STM_TIM234_CCMR1_OC1FE  2
1428 #define STM_TIM234_CCMR1_CC1S   0
1429 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1430 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1431 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1432 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1433 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1434
1435 #define STM_TIM234_CCMR2_OC4CE  15
1436 #define STM_TIM234_CCMR2_OC4M   12
1437 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1438 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1439 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1440 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1441 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1442 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1443 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1444 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1445 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1446 #define STM_TIM234_CCMR2_OC4PE  11
1447 #define STM_TIM234_CCMR2_OC4FE  10
1448 #define STM_TIM234_CCMR2_CC4S   8
1449 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1450 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1451 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1452 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1453 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1454
1455 #define STM_TIM234_CCMR2_OC3CE  7
1456 #define STM_TIM234_CCMR2_OC3M   4
1457 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1458 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1459 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1460 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1461 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1462 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1463 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1464 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1465 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1466 #define STM_TIM234_CCMR2_OC3PE  11
1467 #define STM_TIM234_CCMR2_OC3FE  2
1468 #define STM_TIM234_CCMR2_CC3S   0
1469 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1470 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1471 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1472 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1473 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1474
1475 #define STM_TIM234_CCER_CC4NP   15
1476 #define STM_TIM234_CCER_CC4P    13
1477 #define STM_TIM234_CCER_CC4E    12
1478 #define STM_TIM234_CCER_CC3NP   11
1479 #define STM_TIM234_CCER_CC3P    9
1480 #define STM_TIM234_CCER_CC3E    8
1481 #define STM_TIM234_CCER_CC2NP   7
1482 #define STM_TIM234_CCER_CC2P    5
1483 #define STM_TIM234_CCER_CC2E    4
1484 #define STM_TIM234_CCER_CC1NP   3
1485 #define STM_TIM234_CCER_CC1P    1
1486 #define STM_TIM234_CCER_CC1E    0
1487
1488 struct stm_usb {
1489         struct {
1490                 vuint16_t       r;
1491                 uint16_t        _;
1492         } epr[8];
1493         uint8_t         reserved_20[0x40 - 0x20];
1494         vuint16_t       cntr;
1495         uint16_t        reserved_42;
1496         vuint16_t       istr;
1497         uint16_t        reserved_46;
1498         vuint16_t       fnr;
1499         uint16_t        reserved_4a;
1500         vuint16_t       daddr;
1501         uint16_t        reserved_4e;
1502         vuint16_t       btable;
1503         uint16_t        reserved_52;
1504         vuint16_t       lpmcsr;
1505         uint16_t        reserved_56;
1506         vuint16_t       bcdr;
1507         uint16_t        reserved_5a;
1508 };
1509
1510 extern struct stm_usb stm_usb;
1511
1512 #define STM_USB_EPR_CTR_RX      15
1513 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1514 #define STM_USB_EPR_DTOG_RX     14
1515 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1516 #define STM_USB_EPR_STAT_RX     12
1517 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1518 #define  STM_USB_EPR_STAT_RX_STALL                      1
1519 #define  STM_USB_EPR_STAT_RX_NAK                        2
1520 #define  STM_USB_EPR_STAT_RX_VALID                      3
1521 #define  STM_USB_EPR_STAT_RX_MASK                       3
1522 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1523 #define STM_USB_EPR_SETUP       11
1524 #define STM_USB_EPR_EP_TYPE     9
1525 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1526 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1527 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1528 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1529 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1530 #define STM_USB_EPR_EP_KIND     8
1531 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1532 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1533 #define STM_USB_EPR_CTR_TX      7
1534 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1535 #define STM_USB_EPR_DTOG_TX     6
1536 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1537 #define STM_USB_EPR_STAT_TX     4
1538 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1539 #define  STM_USB_EPR_STAT_TX_STALL                      1
1540 #define  STM_USB_EPR_STAT_TX_NAK                        2
1541 #define  STM_USB_EPR_STAT_TX_VALID                      3
1542 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1543 #define  STM_USB_EPR_STAT_TX_MASK                       3
1544 #define STM_USB_EPR_EA          0
1545 #define  STM_USB_EPR_EA_MASK                            0xf
1546
1547 #define STM_USB_CNTR_CTRM       15
1548 #define STM_USB_CNTR_PMAOVRM    14
1549 #define STM_USB_CNTR_ERRM       13
1550 #define STM_USB_CNTR_WKUPM      12
1551 #define STM_USB_CNTR_SUSPM      11
1552 #define STM_USB_CNTR_RESETM     10
1553 #define STM_USB_CNTR_SOFM       9
1554 #define STM_USB_CNTR_ESOFM      8
1555 #define STM_USB_CNTR_RESUME     4
1556 #define STM_USB_CNTR_FSUSP      3
1557 #define STM_USB_CNTR_LP_MODE    2
1558 #define STM_USB_CNTR_PDWN       1
1559 #define STM_USB_CNTR_FRES       0
1560
1561 #define STM_USB_ISTR_CTR        15
1562 #define STM_USB_ISTR_PMAOVR     14
1563 #define STM_USB_ISTR_ERR        13
1564 #define STM_USB_ISTR_WKUP       12
1565 #define STM_USB_ISTR_SUSP       11
1566 #define STM_USB_ISTR_RESET      10
1567 #define STM_USB_ISTR_SOF        9
1568 #define STM_USB_ISTR_ESOF       8
1569 #define STM_USB_L1REQ           7
1570 #define STM_USB_ISTR_DIR        4
1571 #define STM_USB_ISTR_EP_ID      0
1572 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1573
1574 #define STM_USB_FNR_RXDP        15
1575 #define STM_USB_FNR_RXDM        14
1576 #define STM_USB_FNR_LCK         13
1577 #define STM_USB_FNR_LSOF        11
1578 #define  STM_USB_FNR_LSOF_MASK                  0x3
1579 #define STM_USB_FNR_FN          0
1580 #define  STM_USB_FNR_FN_MASK                    0x7ff
1581
1582 #define STM_USB_DADDR_EF        7
1583 #define STM_USB_DADDR_ADD       0
1584 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1585
1586 #define STM_USB_BCDR_DPPU       15
1587 #define STM_USB_BCDR_PS2DET     7
1588 #define STM_USB_BCDR_SDET       6
1589 #define STM_USB_BCDR_PDET       5
1590 #define STM_USB_BCDR_DCDET      4
1591 #define STM_USB_BCDR_SDEN       3
1592 #define STM_USB_BCDR_PDEN       2
1593 #define STM_USB_BCDR_DCDEN      1
1594 #define STM_USB_BCDR_BCDEN      0
1595
1596 union stm_usb_bdt {
1597         struct {
1598                 vuint16_t       addr_tx;
1599                 vuint16_t       count_tx;
1600                 vuint16_t       addr_rx;
1601                 vuint16_t       count_rx;
1602         } single;
1603         struct {
1604                 vuint16_t       addr;
1605                 vuint16_t       count;
1606         } double_tx[2];
1607         struct {
1608                 vuint16_t       addr;
1609                 vuint16_t       count;
1610         } double_rx[2];
1611 };
1612
1613 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1614 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1615 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1616 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1617 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1618
1619 #define STM_USB_BDT_SIZE        8
1620
1621 extern uint8_t stm_usb_sram[];
1622
1623 struct stm_exti {
1624         vuint32_t       imr;
1625         vuint32_t       emr;
1626         vuint32_t       rtsr;
1627         vuint32_t       ftsr;
1628
1629         vuint32_t       swier;
1630         vuint32_t       pr;
1631 };
1632
1633 extern struct stm_exti stm_exti;
1634
1635 #endif /* _STM32F0_H_ */