2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
85 static union stm_usb_bdt *ao_usb_bdt;
86 /* USB address of end of allocated storage */
88 static uint16_t ao_usb_sram_addr;
91 /* Pointer to ep0 tx/rx buffers in USB memory */
92 static uint16_t *ao_usb_ep0_tx_buffer;
93 static uint16_t *ao_usb_ep0_rx_buffer;
96 /* Pointer to interrupt buffer in USB memory */
97 static uint16_t ao_usb_int_tx_offset;
100 /* Pointer to bulk data tx/rx buffers in USB memory */
102 static uint16_t ao_usb_in_tx_offset[2];
103 static uint16_t *ao_usb_in_tx_buffer[2];
104 static uint8_t ao_usb_in_tx_which;
105 static uint8_t ao_usb_tx_count;
109 static uint16_t ao_usb_out_rx_offset;
110 static uint16_t *ao_usb_out_rx_buffer;
112 /* System ram shadow of USB buffer; writing individual bytes is
113 * too much of a pain (sigh) */
114 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
115 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
119 static uint16_t ao_usb_in2_tx_offset[2];
120 static uint16_t *ao_usb_in2_tx_buffer[2];
121 static uint8_t ao_usb_in_tx2_which;
122 static uint8_t ao_usb_tx2_count;
126 * End point register indices
129 #define AO_USB_CONTROL_EPR 0
130 #define AO_USB_INT_EPR 1
131 #define AO_USB_OUT_EPR 2
132 #define AO_USB_IN_EPR 3
133 #define AO_USB_IN2_EPR 4
135 /* Marks when we don't need to send an IN packet.
136 * This happens only when the last IN packet is not full,
137 * otherwise the host will expect to keep seeing packets.
138 * Send a zero-length packet as required
140 static uint8_t ao_usb_in_flushed;
142 /* Marks when we have delivered an IN packet to the hardware
143 * and it has not been received yet. ao_sleep on this address
144 * to wait for it to be delivered.
146 static uint8_t ao_usb_in_pending;
149 /* Marks when we have delivered an IN packet to the hardware
150 * and it has not been received yet. ao_sleep on this address
151 * to wait for it to be delivered.
153 static uint8_t ao_usb_in2_pending;
154 static uint16_t in2_count;
155 static uint8_t ao_usb_in2_flushed;
158 /* Marks when an OUT packet has been received by the hardware
159 * but not pulled to the shadow buffer.
161 static uint8_t ao_usb_out_avail;
162 uint8_t ao_usb_running;
163 static uint8_t ao_usb_configuration;
165 #define AO_USB_EP0_GOT_SETUP 1
166 #define AO_USB_EP0_GOT_RX_DATA 2
167 #define AO_USB_EP0_GOT_TX_ACK 4
169 static uint8_t ao_usb_ep0_receive;
170 static uint8_t ao_usb_address;
171 static uint8_t ao_usb_address_pending;
173 static inline uint32_t set_toggle(uint32_t current_value,
175 uint32_t desired_value)
177 return (current_value ^ desired_value) & mask;
180 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
182 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
185 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
187 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
190 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
191 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
194 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
195 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
198 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
199 return (epr >> STM_USB_EPR_CTR_RX) & 1;
202 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
203 return (epr >> STM_USB_EPR_CTR_TX) & 1;
206 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
207 return (epr >> STM_USB_EPR_SETUP) & 1;
210 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
211 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
214 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
215 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
219 * Set current device address and mark the
220 * interface as active
223 ao_usb_set_address(uint8_t address)
225 debug("ao_usb_set_address %02x\n", address);
226 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
227 ao_usb_address_pending = 0;
231 * Write these values to preserve register contents under HW changes
234 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
235 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
236 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
237 (1 << STM_USB_EPR_CTR_TX) | \
238 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
239 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
241 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
242 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
243 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
244 (1 << STM_USB_EPR_CTR_TX) | \
245 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
246 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
249 * These bits are purely under sw control, so preserve them in the
250 * register by re-writing what was read
252 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
253 (1 << STM_USB_EPR_EP_KIND) | \
254 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
260 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
261 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
263 #define _tx_dbg0(msg)
264 #define _tx_dbg1(msg,value)
268 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
269 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
271 #define _rx_dbg0(msg)
272 #define _rx_dbg1(msg,value)
276 static void _dbg(int line, char *msg, uint32_t value);
280 * Set the state of the specified endpoint register to a new
281 * value. This is tricky because the bits toggle where the new
282 * value is one, and we need to write invariant values in other
283 * spots of the register. This hardware is strange...
286 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
288 uint16_t epr_write, epr_old;
290 _tx_dbg1("set_stat_tx top", stat_tx);
291 epr_old = epr_write = stm_usb.epr[ep].r;
292 epr_write &= STM_USB_EPR_PRESERVE_MASK;
293 epr_write |= STM_USB_EPR_INVARIANT;
294 epr_write |= set_toggle(epr_old,
295 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
296 stat_tx << STM_USB_EPR_STAT_TX);
297 stm_usb.epr[ep].r = epr_write;
298 _tx_dbg1("set_stat_tx bottom", epr_write);
302 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
304 ao_arch_block_interrupts();
305 _ao_usb_set_stat_tx(ep, stat_tx);
306 ao_arch_release_interrupts();
310 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
311 uint16_t epr_write, epr_old;
313 epr_write = epr_old = stm_usb.epr[ep].r;
314 epr_write &= STM_USB_EPR_PRESERVE_MASK;
315 epr_write |= STM_USB_EPR_INVARIANT;
316 epr_write |= set_toggle(epr_old,
317 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
318 stat_rx << STM_USB_EPR_STAT_RX);
319 stm_usb.epr[ep].r = epr_write;
323 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
324 ao_arch_block_interrupts();
325 _ao_usb_set_stat_rx(ep, stat_rx);
326 ao_arch_release_interrupts();
330 * Set just endpoint 0, for use during startup
334 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
338 ao_arch_block_interrupts();
339 epr = stm_usb.epr[ep].r;
340 epr = ((0 << STM_USB_EPR_CTR_RX) |
341 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
343 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
344 (stat_rx << STM_USB_EPR_STAT_RX)) |
345 (type << STM_USB_EPR_EP_TYPE) |
346 (0 << STM_USB_EPR_EP_KIND) |
347 (0 << STM_USB_EPR_CTR_TX) |
348 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
350 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
351 (stat_tx << STM_USB_EPR_STAT_TX)) |
352 (addr << STM_USB_EPR_EA));
353 stm_usb.epr[ep].r = epr;
354 ao_arch_release_interrupts();
355 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
356 ep, epr, stm_usb.epr[ep].r);
360 ao_usb_alloc_buffers(void)
362 uint16_t sram_addr = 0;
364 ao_usb_bdt = (void *) stm_usb_sram;
365 sram_addr += 8 * STM_USB_BDT_SIZE;
367 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
368 sram_addr += AO_USB_CONTROL_SIZE;
370 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
371 sram_addr += AO_USB_CONTROL_SIZE;
375 sram_addr += (sram_addr & 1);
376 ao_usb_int_tx_offset = sram_addr;
377 sram_addr += AO_USB_INT_SIZE;
381 sram_addr += (sram_addr & 1);
382 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
383 ao_usb_out_rx_offset = sram_addr;
384 sram_addr += AO_USB_OUT_SIZE;
388 sram_addr += (sram_addr & 1);
389 ao_usb_in_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
390 ao_usb_in_tx_offset[0] = sram_addr;
391 sram_addr += AO_USB_IN_SIZE;
392 ao_usb_in_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
393 ao_usb_in_tx_offset[1] = sram_addr;
394 sram_addr += AO_USB_IN_SIZE;
395 ao_usb_in_tx_which = 0;
399 sram_addr += (sram_addr & 1);
400 ao_usb_in2_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
401 ao_usb_in2_tx_offset[0] = sram_addr;
402 sram_addr += AO_USB_IN_SIZE;
404 sram_addr += (sram_addr & 1);
405 ao_usb_in2_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
406 ao_usb_in2_tx_offset[1] = sram_addr;
407 sram_addr += AO_USB_IN_SIZE;
408 ao_usb_in2_tx_which = 0;
412 sram_addr += (sram_addr & 1);
413 ao_usb_sram_addr = sram_addr;
418 ao_usb_init_btable(void)
420 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
422 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
423 ao_usb_bdt[0].single.count_tx = 0;
425 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
426 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
427 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
435 ao_usb_init_btable();
437 /* buffer table is at the start of USB memory */
440 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
441 STM_USB_EPR_EP_TYPE_CONTROL,
442 STM_USB_EPR_STAT_RX_VALID,
443 STM_USB_EPR_STAT_TX_NAK);
445 /* Clear all of the other endpoints */
446 for (e = 1; e < 8; e++) {
448 STM_USB_EPR_EP_TYPE_CONTROL,
449 STM_USB_EPR_STAT_RX_DISABLED,
450 STM_USB_EPR_STAT_TX_DISABLED);
453 ao_usb_set_address(0);
457 /* Reset our internal state
460 ao_usb_ep0_state = AO_USB_EP0_IDLE;
462 ao_usb_ep0_in_data = NULL;
463 ao_usb_ep0_in_len = 0;
465 ao_usb_ep0_out_data = 0;
466 ao_usb_ep0_out_len = 0;
470 ao_usb_set_configuration(void)
472 debug ("ao_usb_set_configuration\n");
475 /* Set up the INT end point */
476 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
477 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
479 ao_usb_init_ep(AO_USB_INT_EPR,
481 STM_USB_EPR_EP_TYPE_INTERRUPT,
482 STM_USB_EPR_STAT_RX_DISABLED,
483 STM_USB_EPR_STAT_TX_NAK);
487 /* Set up the OUT end point */
488 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
489 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
490 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
492 ao_usb_init_ep(AO_USB_OUT_EPR,
494 STM_USB_EPR_EP_TYPE_BULK,
495 STM_USB_EPR_STAT_RX_VALID,
496 STM_USB_EPR_STAT_TX_DISABLED);
500 /* Set up the IN end point */
501 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = 0;
502 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
504 ao_usb_init_ep(AO_USB_IN_EPR,
506 STM_USB_EPR_EP_TYPE_BULK,
507 STM_USB_EPR_STAT_RX_DISABLED,
508 STM_USB_EPR_STAT_TX_NAK);
512 /* Set up the IN2 end point */
513 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = 0;
514 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
516 ao_usb_init_ep(AO_USB_IN2_EPR,
518 STM_USB_EPR_EP_TYPE_BULK,
519 STM_USB_EPR_STAT_RX_DISABLED,
520 STM_USB_EPR_STAT_TX_NAK);
523 ao_usb_in_flushed = 0;
524 ao_usb_in_pending = 0;
525 ao_wakeup(&ao_usb_in_pending);
527 ao_usb_in2_flushed = 0;
528 ao_usb_in2_pending = 0;
529 ao_wakeup(&ao_usb_in2_pending);
532 ao_usb_out_avail = 0;
533 ao_usb_configuration = 0;
535 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
539 ao_wakeup(&ao_usb_running);
544 static uint16_t control_count;
545 static uint16_t int_count;
546 static uint16_t in_count;
547 static uint16_t out_count;
548 static uint16_t reset_count;
551 /* The USB memory must be accessed in 16-bit units
555 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
558 *base++ = src[0] | (src[1] << 8);
567 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
570 uint16_t s = *base++;
581 ao_usb_tx_byte(uint16_t *base, uint8_t tx_count, char byte)
584 base[tx_count >> 1] |= ((uint16_t) byte) << 8;
586 base[tx_count >> 1] = (uint16_t) (uint8_t) byte;
590 /* Send an IN data packet */
592 ao_usb_ep0_flush(void)
596 /* Check to see if the endpoint is still busy */
597 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
598 debug("EP0 not accepting IN data\n");
602 this_len = ao_usb_ep0_in_len;
603 if (this_len > AO_USB_CONTROL_SIZE)
604 this_len = AO_USB_CONTROL_SIZE;
606 if (this_len < AO_USB_CONTROL_SIZE)
607 ao_usb_ep0_state = AO_USB_EP0_IDLE;
609 ao_usb_ep0_in_len -= this_len;
611 debug_data ("Flush EP0 len %d:", this_len);
612 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
614 ao_usb_ep0_in_data += this_len;
616 /* Mark the endpoint as TX valid to send the packet */
617 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
618 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
619 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
622 /* Read data from the ep0 OUT fifo */
624 ao_usb_ep0_fill(void)
626 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
628 if (len > ao_usb_ep0_out_len)
629 len = ao_usb_ep0_out_len;
630 ao_usb_ep0_out_len -= len;
632 /* Pull all of the data out of the packet */
633 debug_data ("Fill EP0 len %d:", len);
634 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
636 ao_usb_ep0_out_data += len;
639 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
643 ao_usb_ep0_in_reset(void)
645 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
646 ao_usb_ep0_in_len = 0;
650 ao_usb_ep0_in_queue_byte(uint8_t a)
652 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
653 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
657 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
659 ao_usb_ep0_in_data = data;
660 ao_usb_ep0_in_len = len;
664 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
666 ao_usb_ep0_out_data = data;
667 ao_usb_ep0_out_len = len;
671 ao_usb_ep0_in_start(uint16_t max)
673 /* Don't send more than asked for */
674 if (ao_usb_ep0_in_len > max)
675 ao_usb_ep0_in_len = max;
679 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
681 #if AO_USB_DEVICE_ID_SERIAL
682 static uint8_t ao_usb_serial[2 + 48];
684 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
686 hex_to_ucs2(uint32_t in, uint8_t *out)
690 for (i = 28; i >= 0; i -= 4) {
691 uint8_t bits = (in >> i) & 0xf;
692 *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
697 /* Encode the device ID (96 bits) in hexidecimal to use as a device
701 ao_usb_serial_init(void)
703 ao_usb_serial[0] = 50; /* length */
704 ao_usb_serial[1] = AO_USB_DESC_STRING;
705 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
706 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
707 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
711 /* Walk through the list of descriptors and find a match
714 ao_usb_get_descriptor(uint16_t value, uint16_t length)
716 const uint8_t *descriptor;
717 uint8_t type = value >> 8;
718 uint8_t index = value;
720 descriptor = ao_usb_descriptors;
721 while (descriptor[0] != 0) {
722 if (descriptor[1] == type && index-- == 0) {
724 if (type == AO_USB_DESC_CONFIGURATION)
728 #if AO_USB_DEVICE_ID_SERIAL
729 /* Slightly hacky - the serial number is string 3 */
730 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
731 descriptor = ao_usb_serial;
732 len = sizeof (ao_usb_serial);
737 ao_usb_ep0_in_set(descriptor, len);
740 descriptor += descriptor[0];
745 ao_usb_ep0_setup(void)
747 /* Pull the setup packet out of the fifo */
748 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
750 if (ao_usb_ep0_out_len != 0) {
751 debug ("invalid setup packet length\n");
755 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
756 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
758 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
760 ao_usb_ep0_in_reset();
762 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
763 case AO_USB_TYPE_STANDARD:
764 debug ("Standard setup packet\n");
765 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
766 case AO_USB_RECIP_DEVICE:
767 debug ("Device setup packet\n");
768 switch(ao_usb_setup.request) {
769 case AO_USB_REQ_GET_STATUS:
770 debug ("get status\n");
771 ao_usb_ep0_in_queue_byte(0);
772 ao_usb_ep0_in_queue_byte(0);
774 case AO_USB_REQ_SET_ADDRESS:
775 debug ("set address %d\n", ao_usb_setup.value);
776 ao_usb_address = ao_usb_setup.value;
777 ao_usb_address_pending = 1;
779 case AO_USB_REQ_GET_DESCRIPTOR:
780 debug ("get descriptor %d\n", ao_usb_setup.value);
781 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
783 case AO_USB_REQ_GET_CONFIGURATION:
784 debug ("get configuration %d\n", ao_usb_configuration);
785 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
787 case AO_USB_REQ_SET_CONFIGURATION:
788 ao_usb_configuration = ao_usb_setup.value;
789 debug ("set configuration %d\n", ao_usb_configuration);
790 ao_usb_set_configuration();
794 case AO_USB_RECIP_INTERFACE:
795 debug ("Interface setup packet\n");
796 switch(ao_usb_setup.request) {
797 case AO_USB_REQ_GET_STATUS:
798 ao_usb_ep0_in_queue_byte(0);
799 ao_usb_ep0_in_queue_byte(0);
801 case AO_USB_REQ_GET_INTERFACE:
802 ao_usb_ep0_in_queue_byte(0);
804 case AO_USB_REQ_SET_INTERFACE:
808 case AO_USB_RECIP_ENDPOINT:
809 debug ("Endpoint setup packet\n");
810 switch(ao_usb_setup.request) {
811 case AO_USB_REQ_GET_STATUS:
812 ao_usb_ep0_in_queue_byte(0);
813 ao_usb_ep0_in_queue_byte(0);
819 case AO_USB_TYPE_CLASS:
820 debug ("Class setup packet\n");
821 switch (ao_usb_setup.request) {
822 case AO_USB_SET_LINE_CODING:
823 debug ("set line coding\n");
824 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
826 case AO_USB_GET_LINE_CODING:
827 debug ("get line coding\n");
828 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
830 case AO_USB_SET_CONTROL_LINE_STATE:
836 /* If we're not waiting to receive data from the host,
837 * queue an IN response
839 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
840 ao_usb_ep0_in_start(ao_usb_setup.length);
844 ao_usb_ep0_handle(uint8_t receive)
846 ao_usb_ep0_receive = 0;
847 if (receive & AO_USB_EP0_GOT_SETUP) {
851 if (receive & AO_USB_EP0_GOT_RX_DATA) {
852 debug ("\tgot rx data\n");
853 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
855 if (ao_usb_ep0_out_len == 0) {
856 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
857 ao_usb_ep0_in_start(0);
861 if (receive & AO_USB_EP0_GOT_TX_ACK) {
862 debug ("\tgot tx ack\n");
864 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
865 ao_flight_force_idle = 1;
867 /* Wait until the IN packet is received from addr 0
868 * before assigning our local address
870 if (ao_usb_address_pending)
871 ao_usb_set_address(ao_usb_address);
872 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
877 #if AO_POWER_MANAGEMENT
881 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
883 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
891 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
899 uint32_t istr = stm_usb.istr;
901 stm_usb.istr = ~istr;
902 if (istr & (1 << STM_USB_ISTR_CTR)) {
903 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
904 uint16_t epr, epr_write;
906 /* Preserve the SW write bits, don't mess with most HW writable bits,
907 * clear the CTR_RX and CTR_TX bits
909 epr = stm_usb.epr[ep].r;
911 epr_write &= STM_USB_EPR_PRESERVE_MASK;
912 epr_write |= STM_USB_EPR_INVARIANT;
913 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
914 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
915 stm_usb.epr[ep].r = epr_write;
922 if (ao_usb_epr_ctr_rx(epr)) {
923 if (ao_usb_epr_setup(epr))
924 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
926 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
928 if (ao_usb_epr_ctr_tx(epr))
929 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
930 ao_usb_ep0_handle(ao_usb_ep0_receive);
936 if (ao_usb_epr_ctr_rx(epr)) {
937 _rx_dbg1("RX ISR", epr);
938 ao_usb_out_avail = 1;
939 _rx_dbg0("out avail set");
940 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
941 _rx_dbg0("stdin awoken");
948 _tx_dbg1("TX ISR", epr);
949 if (ao_usb_epr_ctr_tx(epr)) {
950 ao_usb_in_pending = 0;
951 ao_wakeup(&ao_usb_in_pending);
957 _tx_dbg1("TX2 ISR", epr);
958 if (ao_usb_epr_ctr_tx(epr)) {
959 ao_usb_in2_pending = 0;
960 ao_wakeup(&ao_usb_in2_pending);
968 if (ao_usb_epr_ctr_tx(epr))
969 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
975 if (istr & (1 << STM_USB_ISTR_RESET)) {
982 #if AO_POWER_MANAGEMENT
983 if (istr & (1 << STM_USB_ISTR_SUSP)) {
984 debug ("\tsuspend\n");
987 if (istr & (1 << STM_USB_ISTR_WKUP)) {
988 debug ("\twakeup\n");
995 /* Queue the current IN buffer for transmission */
997 _ao_usb_in_send(void)
999 _tx_dbg0("in_send start");
1000 debug ("send %d\n", ao_usb_tx_count);
1001 while (ao_usb_in_pending)
1002 ao_sleep(&ao_usb_in_pending);
1003 ao_usb_in_pending = 1;
1004 if (ao_usb_tx_count != AO_USB_IN_SIZE)
1005 ao_usb_in_flushed = 1;
1006 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset[ao_usb_in_tx_which];
1007 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
1008 ao_usb_tx_count = 0;
1009 ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
1010 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1011 _tx_dbg0("in_send end");
1014 /* Wait for a free IN buffer. Interrupts are blocked */
1016 _ao_usb_in_wait(void)
1019 /* Check if the current buffer is writable */
1020 if (ao_usb_tx_count < AO_USB_IN_SIZE)
1023 _tx_dbg0("in_wait top");
1024 /* Wait for an IN buffer to be ready */
1025 while (ao_usb_in_pending)
1026 ao_sleep(&ao_usb_in_pending);
1027 _tx_dbg0("in_wait bottom");
1034 if (!ao_usb_running)
1037 /* Anytime we've sent a character since
1038 * the last time we flushed, we'll need
1039 * to send a packet -- the only other time
1040 * we would send a packet is when that
1041 * packet was full, in which case we now
1042 * want to send an empty packet
1044 ao_arch_block_interrupts();
1045 while (!ao_usb_in_flushed) {
1046 _tx_dbg0("flush top");
1048 _tx_dbg0("flush end");
1050 ao_arch_release_interrupts();
1054 ao_usb_putchar(char c)
1056 if (!ao_usb_running)
1059 ao_arch_block_interrupts();
1062 ao_usb_in_flushed = 0;
1063 ao_usb_tx_count = ao_usb_tx_byte(ao_usb_in_tx_buffer[ao_usb_in_tx_which], ao_usb_tx_count, c);
1065 /* Send the packet when full */
1066 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1067 _tx_dbg0("putchar full");
1069 _tx_dbg0("putchar flushed");
1071 ao_arch_release_interrupts();
1076 /* Queue the current IN buffer for transmission */
1078 _ao_usb_in2_send(void)
1080 _tx_dbg0("in2_send start");
1081 debug ("send2 %d\n", ao_usb_tx_count);
1082 while (ao_usb_in2_pending)
1083 ao_sleep(&ao_usb_in2_pending);
1084 ao_usb_in2_pending = 1;
1085 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1086 ao_usb_in2_flushed = 1;
1087 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset[ao_usb_in2_tx_which];
1088 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx2_count;
1089 ao_usb_tx2_count = 0;
1090 ao_usb_in2_tx_which = 1 - ao_usb_in2_tx_which;
1091 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1092 _tx_dbg0("in2_send end");
1095 /* Wait for a free IN buffer. Interrupts are blocked */
1097 _ao_usb_in2_wait(void)
1100 /* Check if the current buffer is writable */
1101 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1104 _tx_dbg0("in2_wait top");
1105 /* Wait for an IN buffer to be ready */
1106 while (ao_usb_in2_pending)
1107 ao_sleep(&ao_usb_in2_pending);
1108 _tx_dbg0("in_wait bottom");
1115 if (!ao_usb_running)
1118 /* Anytime we've sent a character since
1119 * the last time we flushed, we'll need
1120 * to send a packet -- the only other time
1121 * we would send a packet is when that
1122 * packet was full, in which case we now
1123 * want to send an empty packet
1125 ao_arch_block_interrupts();
1126 while (!ao_usb_in2_flushed) {
1127 _tx_dbg0("flush2 top");
1129 _tx_dbg0("flush2 end");
1131 ao_arch_release_interrupts();
1135 ao_usb_putchar2(char c)
1137 if (!ao_usb_running)
1140 ao_arch_block_interrupts();
1143 ao_usb_in2_flushed = 0;
1144 ao_usb_tx2_count = ao_usb_tx_byte(ao_usb_in2_tx_buffer[ao_usb_in2_tx_which], ao_usb_tx2_count, c);
1146 /* Send the packet when full */
1147 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1148 _tx_dbg0("putchar2 full");
1150 _tx_dbg0("putchar2 flushed");
1152 ao_arch_release_interrupts();
1158 _ao_usb_out_recv(void)
1160 _rx_dbg0("out_recv top");
1161 ao_usb_out_avail = 0;
1163 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
1165 _rx_dbg1("out_recv count", ao_usb_rx_count);
1166 debug ("recv %d\n", ao_usb_rx_count);
1167 debug_data("Fill OUT len %d:", ao_usb_rx_count);
1168 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
1172 /* ACK the packet */
1173 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1177 _ao_usb_pollchar(void)
1181 if (!ao_usb_running)
1182 return AO_READ_AGAIN;
1185 if (ao_usb_rx_pos != ao_usb_rx_count)
1188 _rx_dbg0("poll check");
1189 /* Check to see if a packet has arrived */
1190 if (!ao_usb_out_avail) {
1191 _rx_dbg0("poll none");
1192 return AO_READ_AGAIN;
1197 /* Pull a character out of the fifo */
1198 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
1203 ao_usb_getchar(void)
1207 ao_arch_block_interrupts();
1208 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1209 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1210 ao_arch_release_interrupts();
1221 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
1222 ao_usb_sram_addr += AO_USB_IN_SIZE;
1227 ao_usb_write(uint16_t *buffer, uint16_t len)
1229 ao_arch_block_interrupts();
1231 /* Wait for everything to be ready at the same time */
1233 /* Make sure USB is connected */
1234 if (!ao_usb_running) {
1235 ao_sleep(&ao_usb_running);
1239 /* Flush any pending regular I/O */
1240 if (ao_usb_tx_count) {
1245 /* Wait for an idle IN buffer */
1246 if (ao_usb_in_pending) {
1247 ao_sleep(&ao_usb_in_pending);
1253 ao_usb_in_pending = 1;
1254 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1255 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1256 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1257 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1258 ao_arch_release_interrupts();
1263 ao_usb_write2(uint16_t *buffer, uint16_t len)
1265 ao_arch_block_interrupts();
1267 /* Wait for everything to be ready at the same time */
1269 /* Make sure USB is connected */
1270 if (!ao_usb_running) {
1271 ao_sleep(&ao_usb_running);
1275 /* Flush any pending regular I/O */
1276 if (ao_usb_tx2_count) {
1281 /* Wait for an idle IN buffer */
1282 if (ao_usb_in2_pending) {
1283 ao_sleep(&ao_usb_in2_pending);
1289 ao_usb_in2_pending = 1;
1290 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1291 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1292 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
1293 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1294 ao_arch_release_interrupts();
1300 ao_usb_disable(void)
1302 ao_arch_block_interrupts();
1303 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1306 /* Disable USB pull-up */
1307 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1309 /* Switch off the device */
1310 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1312 /* Disable the interface */
1313 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1314 ao_arch_release_interrupts();
1322 /* Select HSI48 as USB clock source */
1323 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1325 /* Enable USB device */
1326 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1328 /* Clear reset condition */
1329 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1331 /* Disable USB pull-up */
1332 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1334 /* Do not touch the GPIOA configuration; USB takes priority
1335 * over GPIO on pins A11 and A12, but if you select alternate
1336 * input 10 (the documented correct selection), then USB is
1337 * pulled low and doesn't work at all
1340 ao_arch_block_interrupts();
1342 /* Route interrupts */
1343 stm_nvic_set_enable(STM_ISR_USB_POS);
1344 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1346 ao_usb_configuration = 0;
1348 /* Set up buffer descriptors */
1349 ao_usb_init_btable();
1351 /* Reset the USB controller */
1352 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1354 /* Clear the reset bit */
1357 /* Clear any spurious interrupts */
1362 debug ("ao_usb_enable\n");
1364 /* Enable interrupts */
1365 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1366 (0 << STM_USB_CNTR_PMAOVRM) |
1367 (0 << STM_USB_CNTR_ERRM) |
1368 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1369 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1370 (1 << STM_USB_CNTR_RESETM) |
1371 (0 << STM_USB_CNTR_SOFM) |
1372 (0 << STM_USB_CNTR_ESOFM) |
1373 (0 << STM_USB_CNTR_RESUME) |
1374 (0 << STM_USB_CNTR_FSUSP) |
1375 (0 << STM_USB_CNTR_LP_MODE) |
1376 (0 << STM_USB_CNTR_PDWN) |
1377 (0 << STM_USB_CNTR_FRES));
1379 ao_arch_release_interrupts();
1381 for (t = 0; t < 1000; t++)
1384 /* Enable USB pull-up */
1385 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1389 struct ao_task ao_usb_echo_task;
1397 c = ao_usb_getchar();
1408 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1409 control_count, out_count, in_count, int_count, reset_count);
1412 __code struct ao_cmds ao_usb_cmds[] = {
1413 { ao_usb_irq, "I\0Show USB interrupt counts" },
1421 /* Turn on syscfg */
1422 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1424 /* Set PA11/PA12 remapping bit */
1425 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1427 #ifndef AO_USB_START_DISABLED
1431 #if AO_USB_DEVICE_ID_SERIAL
1432 ao_usb_serial_init();
1435 debug ("ao_usb_init\n");
1436 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1438 ao_usb_alloc_buffers();
1441 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1444 ao_cmd_register(&ao_usb_cmds[0]);
1448 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1453 #if TX_DBG || RX_DBG
1463 uint32_t in_pending;
1465 uint32_t in_flushed;
1475 #define NUM_USB_DBG 128
1477 static struct ao_usb_dbg dbg[128];
1480 static void _dbg(int line, char *msg, uint32_t value)
1483 dbg[dbg_i].line = line;
1484 dbg[dbg_i].msg = msg;
1485 dbg[dbg_i].value = value;
1486 asm("mrs %0,primask" : "=&r" (primask));
1487 dbg[dbg_i].primask = primask;
1489 dbg[dbg_i].in_count = in_count;
1490 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1491 dbg[dbg_i].in_pending = ao_usb_in_pending;
1492 dbg[dbg_i].tx_count = ao_usb_tx_count;
1493 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1496 dbg[dbg_i].rx_count = ao_usb_rx_count;
1497 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1498 dbg[dbg_i].out_avail = ao_usb_out_avail;
1499 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1501 if (++dbg_i == NUM_USB_DBG)