2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include <ao_fake_flight.h>
29 volatile AO_TICK_TYPE ao_tick_count;
38 volatile __data uint8_t ao_data_interval = 1;
39 volatile __data uint8_t ao_data_count;
42 void stm_systick_isr(void)
44 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
47 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
48 ao_task_check_alarm((uint16_t) ao_tick_count);
51 if (++ao_data_count == ao_data_interval) {
54 if (ao_fake_flight_active)
55 ao_fake_flight_poll();
59 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
60 ao_wakeup((void *) &ao_data_count);
72 ao_timer_set_adc_interval(uint8_t interval)
75 ao_data_interval = interval;
81 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
86 stm_systick.rvr = SYSTICK_RELOAD;
88 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
89 (1 << STM_SYSTICK_CSR_TICKINT) |
90 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
96 ao_clock_enable_crs(void)
98 /* Enable crs interface clock */
99 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_CRSEN);
101 /* Disable error counter */
102 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
103 (32 << STM_CRS_CR_TRIM) |
104 (0 << STM_CRS_CR_SWSYNC) |
105 (0 << STM_CRS_CR_AUTOTRIMEN) |
106 (0 << STM_CRS_CR_CEN) |
107 (0 << STM_CRS_CR_ESYNCIE) |
108 (0 << STM_CRS_CR_ERRIE) |
109 (0 << STM_CRS_CR_SYNCWARNIE) |
110 (0 << STM_CRS_CR_SYNCOKIE));
112 /* Configure for USB source */
113 stm_crs.cfgr = ((stm_crs.cfgr & ((1 << 30) | (1 << 27))) |
114 (0 << STM_CRS_CFGR_SYNCPOL) |
115 (STM_CRS_CFGR_SYNCSRC_USB << STM_CRS_CFGR_SYNCSRC) |
116 (STM_CRS_CFGR_SYNCDIV_1 << STM_CRS_CFGR_SYNCDIV) |
117 (0x22 << STM_CRS_CFGR_FELIM) |
118 (((48000000 / 1000) - 1) << STM_CRS_CFGR_RELOAD));
120 /* Enable error counter, set auto trim */
121 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
122 (32 << STM_CRS_CR_TRIM) |
123 (0 << STM_CRS_CR_SWSYNC) |
124 (1 << STM_CRS_CR_AUTOTRIMEN) |
125 (1 << STM_CRS_CR_CEN) |
126 (0 << STM_CRS_CR_ESYNCIE) |
127 (0 << STM_CRS_CR_ERRIE) |
128 (0 << STM_CRS_CR_SYNCWARNIE) |
129 (0 << STM_CRS_CR_SYNCOKIE));
135 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
136 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
139 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
140 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
142 /* wait for system to switch to HSI */
143 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
144 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
147 /* reset the clock config, leaving us running on the HSI */
148 stm_rcc.cfgr &= (uint32_t)0x0000000f;
150 /* reset PLLON, CSSON, HSEBYP, HSEON */
151 stm_rcc.cr &= 0x0000ffff;
155 ao_clock_normal_start(void)
158 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSE
159 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSE
160 #define STM_PLLSRC AO_HSE
161 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 1
164 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
166 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
168 /* Enable HSE clock */
169 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
170 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
174 #error No code for PLL initialization yet
181 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI48
182 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI48
184 /* Turn HSI48 clock on */
185 stm_rcc.cr2 |= (1 << STM_RCC_CR2_HSI48ON);
187 /* Wait for clock to stabilize */
188 while ((stm_rcc.cr2 & (1 << STM_RCC_CR2_HSI48RDY)) == 0)
191 ao_clock_enable_crs();
194 #ifndef STM_RCC_CFGR_SWS_TARGET_CLOCK
195 #define STM_HSI 16000000
196 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI
197 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI
198 #define STM_PLLSRC STM_HSI
199 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 0
204 ao_clock_normal_switch(void)
209 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
210 cfgr |= (STM_RCC_CFGR_SW_TARGET_CLOCK << STM_RCC_CFGR_SW);
213 uint32_t c, part, mask, val;
216 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
217 val = (STM_RCC_CFGR_SWS_TARGET_CLOCK << STM_RCC_CFGR_SWS);
222 #if !AO_HSI && !AO_NEED_HSI
223 /* Turn off the HSI clock */
224 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
233 /* Switch to HSI while messing about */
236 /* Disable all interrupts */
239 /* Start high speed clock */
240 ao_clock_normal_start();
242 /* Set flash latency to tolerate 48MHz SYSCLK -> 1 wait state */
244 /* Enable prefetch */
245 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFTBE);
247 /* Enable 1 wait state so the CPU can run at 48MHz */
248 stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
250 /* Enable power interface clock */
251 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
253 /* HCLK to 48MHz -> AHB prescaler = /1 */
255 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
256 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
258 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
259 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
262 /* APB Prescaler = AO_APB_PRESCALER */
264 cfgr &= ~(STM_RCC_CFGR_PPRE_MASK << STM_RCC_CFGR_PPRE);
265 cfgr |= (AO_RCC_CFGR_PPRE_DIV << STM_RCC_CFGR_PPRE);
268 /* Switch to the desired system clock */
269 ao_clock_normal_switch();
271 /* Clear reset flags */
272 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
275 /* Output SYSCLK on PA8 for measurments */
277 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
279 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
280 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
281 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
283 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
284 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
288 #if AO_POWER_MANAGEMENT
290 ao_clock_suspend(void)
296 ao_clock_resume(void)
298 ao_clock_normal_start();
299 ao_clock_normal_switch();