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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19
  20 struct ao_dma_config {
  21         void            (*isr)(int index);
  22 };
  23
  24 uint8_t ao_dma_done[STM_NUM_DMA];
  25
  26 static struct ao_dma_config ao_dma_config[STM_NUM_DMA];
  27 static uint8_t ao_dma_allocated[STM_NUM_DMA];
  28 static uint8_t ao_dma_mutex[STM_NUM_DMA];
  29 static uint8_t ao_dma_active;
  30
  31 #define ch_mask(id)     (STM_DMA_ISR_MASK << STM_DMA_ISR(id))
  32
  33 static void
  34 ao_dma_isr(uint8_t low_index, uint8_t high_index, uint32_t mask) {
  35         /* Get channel interrupt bits */
  36         uint32_t        isr = stm_dma.isr & mask;
  37         uint8_t         index;
  38
  39         /* Ack them */
  40         stm_dma.ifcr = isr;
  41         for (index = low_index; index <= high_index; index++) {
  42                 if (isr & ch_mask(index)) {
  43                         if (ao_dma_config[index].isr)
  44                                 (*ao_dma_config[index].isr)(index);
  45                         else {
  46                                 ao_dma_done[index] = 1;
  47                                 ao_wakeup(&ao_dma_done[index]);
  48                         }
  49                 }
  50         }
  51 }
  52
  53 void stm_dma_ch1_isr(void) {
  54         ao_dma_isr(STM_DMA_INDEX(1),
  55                    STM_DMA_INDEX(1),
  56                    ch_mask(STM_DMA_INDEX(1)));
  57 }
  58
  59 void stm_dma_ch2_3_isr(void) {
  60         ao_dma_isr(STM_DMA_INDEX(2),
  61                    STM_DMA_INDEX(3),
  62                    ch_mask(STM_DMA_INDEX(2)) |
  63                    ch_mask(STM_DMA_INDEX(3)));
  64 }
  65
  66 void stm_dma1_ch4_5_6_isr(void) {
  67         ao_dma_isr(STM_DMA_INDEX(4), STM_DMA_INDEX(6),
  68                    ch_mask(STM_DMA_INDEX(4)) |
  69                    ch_mask(STM_DMA_INDEX(5)) |
  70                    ch_mask(STM_DMA_INDEX(6)));
  71 }
  72
  73 void
  74 ao_dma_set_transfer(uint8_t             index,
  75                     volatile void       *peripheral,
  76                     void                *memory,
  77                     uint16_t            count,
  78                     uint32_t            ccr)
  79 {
  80         if (ao_dma_allocated[index]) {
  81                 if (ao_dma_mutex[index])
  82                         ao_panic(AO_PANIC_DMA);
  83                 ao_dma_mutex[index] = 1;
  84         } else
  85                 ao_mutex_get(&ao_dma_mutex[index]);
  86         ao_arch_critical(
  87                 if (ao_dma_active++ == 0)
  88                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMAEN);
  89                 );
  90         ao_dma_config[index].isr = NULL;
  91         ao_dma_done[index] = 0;
  92         stm_dma.channel[index].cndtr = count;
  93         stm_dma.channel[index].cpar = peripheral;
  94         stm_dma.channel[index].cmar = memory;
  95         stm_dma.channel[index].ccr = ccr;
  96 }
  97
  98 void
  99 ao_dma_set_isr(uint8_t index, void (*isr)(int))
 100 {
 101         ao_dma_config[index].isr = isr;
 102 }
 103
 104 void
 105 ao_dma_start(uint8_t index)
 106 {
 107         stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
 108 }
 109
 110 void
 111 ao_dma_done_transfer(uint8_t index)
 112 {
 113         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
 114         ao_arch_critical(
 115                 if (--ao_dma_active == 0)
 116                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMAEN);
 117                 );
 118         if (ao_dma_allocated[index])
 119                 ao_dma_mutex[index] = 0;
 120         else
 121                 ao_mutex_put(&ao_dma_mutex[index]);
 122 }
 123
 124 void
 125 ao_dma_abort(uint8_t index)
 126 {
 127         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
 128         ao_wakeup(&ao_dma_done[index]);
 129 }
 130
 131 void
 132 ao_dma_alloc(uint8_t index)
 133 {
 134         if (ao_dma_allocated[index])
 135                 ao_panic(AO_PANIC_DMA);
 136         ao_dma_allocated[index] = 1;
 137 }
 138
 139 #define STM_NUM_DMA_ISR 3
 140
 141 void
 142 ao_dma_init(void)
 143 {
 144         int     isr_id;
 145         int     index;
 146
 147         for (isr_id = 0; isr_id < STM_NUM_DMA_ISR; isr_id++) {
 148                 stm_nvic_set_enable(STM_ISR_DMA_CH1_POS + isr_id);
 149                 stm_nvic_set_priority(STM_ISR_DMA_CH1_POS + isr_id, 4);
 150         }
 151         for (index = 0; index < STM_NUM_DMA; index++) {
 152                 ao_dma_allocated[index] = 0;
 153                 ao_dma_mutex[index] = 0;
 154         }
 155 }