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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19
  20 #ifndef BEEPER_CHANNEL
  21 #error BEEPER_CHANNEL undefined
  22 #endif
  23
  24 #ifndef BEEPER_TIMER
  25 #define BEEPER_TIMER    1
  26 #endif
  27
  28 #if BEEPER_TIMER == 1
  29 #define timer stm_tim1
  30 #define STM_RCC_TIMER STM_RCC_APB2ENR_TIM1EN
  31 #define stm_rcc_enr stm_rcc.apb2enr
  32 #endif
  33
  34 #if BEEPER_TIMER == 2
  35 #define timer stm_tim2
  36 #define STM_RCC_TIMER STM_RCC_APB1ENR_TIM2EN
  37 #define stm_rcc_enr stm_rcc.apb1enr
  38 #endif
  39
  40 #if BEEPER_TIMER == 3
  41 #define timer stm_tim3
  42 #define STM_RCC_TIMER STM_RCC_APB1ENR_TIM3EN
  43 #define stm_rcc_enr stm_rcc.apb1enr
  44 #endif
  45
  46 #ifndef timer
  47 #error BEEPER_TIMER invalid
  48 #endif
  49
  50 static inline void
  51 disable(void)
  52 {
  53         timer.cr1 = 0;
  54 #if BEEPER_TIMER == 1
  55         timer.bdtr = 0;
  56 #endif
  57         stm_rcc_enr &= ~(1 << STM_RCC_TIMER);
  58 }
  59
  60 void
  61 ao_beep(uint8_t beep)
  62 {
  63         if (beep == 0) {
  64                 disable();
  65         } else {
  66                 stm_rcc_enr |= (1 << STM_RCC_TIMER);
  67
  68 #if BEEPER_TIMER == 1
  69                 /* Master output enable */
  70                 stm_tim1.bdtr = (1 << STM_TIM1_BDTR_MOE);
  71
  72                 stm_tim1.cr2 = ((0 << STM_TIM1_CR2_TI1S) |
  73                                 (STM_TIM1_CR2_MMS_RESET << STM_TIM1_CR2_MMS) |
  74                                 (0 << STM_TIM1_CR2_CCDS));
  75
  76                 /* Set prescaler to match cc1111 clocks
  77                  */
  78                 stm_tim1.psc = AO_TIM_CLK / 750000;
  79
  80                 /* 1. Select the counter clock (internal, external, prescaler).
  81                  *
  82                  * Setting SMCR to zero means use the internal clock
  83                  */
  84
  85                 stm_tim1.smcr = 0;
  86
  87                 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
  88                 stm_tim1.arr = beep;
  89                 stm_tim1.ccr1 = beep;
  90
  91                 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
  92                  * DMA request is to be generated.
  93                  */
  94                 /* don't want this */
  95
  96                 /* 4. Select the output mode. For example, you must write
  97                  *  OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
  98                  *  pin when CNT matches CCRx, CCRx preload is not used, OCx
  99                  *  is enabled and active high.
 100                  */
 101
 102 #if BEEPER_CHANNEL == 1
 103                 stm_tim1.ccmr1 = ((0 << STM_TIM1_CCMR1_OC2CE) |
 104                                   (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR1_OC2M) |
 105                                   (0 << STM_TIM1_CCMR1_OC2PE) |
 106                                   (0 << STM_TIM1_CCMR1_OC2FE) |
 107                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC2S) |
 108
 109                                   (0 << STM_TIM1_CCMR1_OC1CE) |
 110                                   (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR1_OC1M) |
 111                                   (0 << STM_TIM1_CCMR1_OC1PE) |
 112                                   (0 << STM_TIM1_CCMR1_OC1FE) |
 113                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC1S));
 114
 115                 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
 116                                  (0 << STM_TIM1_CCER_CC4E) |
 117                                  (0 << STM_TIM1_CCER_CC3NP) |
 118                                  (0 << STM_TIM1_CCER_CC3NE) |
 119                                  (0 << STM_TIM1_CCER_CC3P) |
 120                                  (0 << STM_TIM1_CCER_CC3E) |
 121                                  (0 << STM_TIM1_CCER_CC2NP) |
 122                                  (0 << STM_TIM1_CCER_CC2NE) |
 123                                  (0 << STM_TIM1_CCER_CC2P) |
 124                                  (0 << STM_TIM1_CCER_CC2E) |
 125                                  (0 << STM_TIM1_CCER_CC1NE) |
 126                                  (0 << STM_TIM1_CCER_CC1P) |
 127                                  (1 << STM_TIM1_CCER_CC1E));
 128 #endif
 129 #if BEEPER_CHANNEL == 2
 130                 stm_tim1.ccmr1 = ((0 << STM_TIM1_CCMR1_OC2CE) |
 131                                   (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR1_OC2M) |
 132                                   (0 << STM_TIM1_CCMR1_OC2PE) |
 133                                   (0 << STM_TIM1_CCMR1_OC2FE) |
 134                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC2S) |
 135
 136                                   (0 << STM_TIM1_CCMR1_OC1CE) |
 137                                   (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR1_OC1M) |
 138                                   (0 << STM_TIM1_CCMR1_OC1PE) |
 139                                   (0 << STM_TIM1_CCMR1_OC1FE) |
 140                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC1S));
 141
 142                 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
 143                                  (0 << STM_TIM1_CCER_CC4E) |
 144                                  (0 << STM_TIM1_CCER_CC3NP) |
 145                                  (0 << STM_TIM1_CCER_CC3NE) |
 146                                  (0 << STM_TIM1_CCER_CC3P) |
 147                                  (0 << STM_TIM1_CCER_CC3E) |
 148                                  (0 << STM_TIM1_CCER_CC2NP) |
 149                                  (0 << STM_TIM1_CCER_CC2NE) |
 150                                  (0 << STM_TIM1_CCER_CC2P) |
 151                                  (1 << STM_TIM1_CCER_CC2E) |
 152                                  (0 << STM_TIM1_CCER_CC1NE) |
 153                                  (0 << STM_TIM1_CCER_CC1P) |
 154                                  (0 << STM_TIM1_CCER_CC1E));
 155 #endif
 156 #if BEEPER_CHANNEL == 3
 157                 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
 158                                   (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR2_OC4M) |
 159                                   (0 << STM_TIM1_CCMR2_OC4PE) |
 160                                   (0 << STM_TIM1_CCMR2_OC4FE) |
 161                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC4S) |
 162
 163                                   (0 << STM_TIM1_CCMR2_OC3CE) |
 164                                   (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR2_OC3M) |
 165                                   (0 << STM_TIM1_CCMR2_OC3PE) |
 166                                   (0 << STM_TIM1_CCMR2_OC3FE) |
 167                                   (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC3S));
 168
 169                 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
 170                                  (0 << STM_TIM1_CCER_CC4E) |
 171                                  (0 << STM_TIM1_CCER_CC3NP) |
 172                                  (0 << STM_TIM1_CCER_CC3NE) |
 173                                  (0 << STM_TIM1_CCER_CC3P) |
 174                                  (1 << STM_TIM1_CCER_CC3E) |
 175                                  (0 << STM_TIM1_CCER_CC2NP) |
 176                                  (0 << STM_TIM1_CCER_CC2NE) |
 177                                  (0 << STM_TIM1_CCER_CC2P) |
 178                                  (0 << STM_TIM1_CCER_CC2E) |
 179                                  (0 << STM_TIM1_CCER_CC1NE) |
 180                                  (0 << STM_TIM1_CCER_CC1P) |
 181                                  (0 << STM_TIM1_CCER_CC1E));
 182 #endif
 183 #if BEEPER_CHANNEL == 4
 184                 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
 185                                   (STM_TIM1_CCMR2_OC4M_TOGGLE << STM_TIM1_CCMR2_OC4M) |
 186                                   (0 << STM_TIM1_CCMR2_OC4PE) |
 187                                   (0 << STM_TIM1_CCMR2_OC4FE) |
 188                                   (STM_TIM1_CCMR2_CC4S_OUTPUT << STM_TIM1_CCMR2_CC4S) |
 189
 190                                   (0 << STM_TIM1_CCMR2_OC3CE) |
 191                                   (STM_TIM1_CCMR2_OC3M_FROZEN << STM_TIM1_CCMR2_OC3M) |
 192                                   (0 << STM_TIM1_CCMR2_OC3PE) |
 193                                   (0 << STM_TIM1_CCMR2_OC3FE) |
 194                                   (STM_TIM1_CCMR2_CC3S_OUTPUT << STM_TIM1_CCMR2_CC3S));
 195
 196                 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4NP) |
 197                                  (0 << STM_TIM1_CCER_CC4P) |
 198                                  (1 << STM_TIM1_CCER_CC4E) |
 199                                  (0 << STM_TIM1_CCER_CC3NP) |
 200                                  (0 << STM_TIM1_CCER_CC3P) |
 201                                  (0 << STM_TIM1_CCER_CC3E) |
 202                                  (0 << STM_TIM1_CCER_CC2NP) |
 203                                  (0 << STM_TIM1_CCER_CC2P) |
 204                                  (0 << STM_TIM1_CCER_CC2E) |
 205                                  (0 << STM_TIM1_CCER_CC1NP) |
 206                                  (0 << STM_TIM1_CCER_CC1P) |
 207                                  (0 << STM_TIM1_CCER_CC1E));
 208 #endif
 209                 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
 210
 211                 stm_tim1.cr1 = ((STM_TIM1_CR1_CKD_1 << STM_TIM1_CR1_CKD) |
 212                                 (0 << STM_TIM1_CR1_ARPE) |
 213                                 (STM_TIM1_CR1_CMS_EDGE << STM_TIM1_CR1_CMS) |
 214                                 (0 << STM_TIM1_CR1_DIR) |
 215                                 (0 << STM_TIM1_CR1_OPM) |
 216                                 (0 << STM_TIM1_CR1_URS) |
 217                                 (0 << STM_TIM1_CR1_UDIS) |
 218                                 (1 << STM_TIM1_CR1_CEN));
 219
 220                 /* Update the values */
 221                 stm_tim1.egr = (1 << STM_TIM1_EGR_UG);
 222 #endif
 223 #if BEEPER_TIMER == 2 || BEEPER_TIMER == 3
 224
 225                 timer.cr2 = ((0 << STM_TIM23_CR2_TI1S) |
 226                              (STM_TIM23_CR2_MMS_RESET << STM_TIM23_CR2_MMS) |
 227                              (0 << STM_TIM23_CR2_CCDS));
 228
 229                 /* Set prescaler to match cc1111 clocks
 230                  */
 231                 timer.psc = AO_TIM_CLK / 750000;
 232
 233                 /* 1. Select the counter clock (internal, external, prescaler).
 234                  *
 235                  * Setting SMCR to zero means use the internal clock
 236                  */
 237
 238                 timer.smcr = 0;
 239
 240                 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
 241                 timer.arr = beep;
 242                 timer.ccr1 = beep;
 243
 244                 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
 245                  * DMA request is to be generated.
 246                  */
 247                 /* don't want this */
 248
 249                 /* 4. Select the output mode. For example, you must write
 250                  *  OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
 251                  *  pin when CNT matches CCRx, CCRx preload is not used, OCx
 252                  *  is enabled and active high.
 253                  */
 254
 255 #if BEEPER_CHANNEL == 1
 256                 timer.ccmr1 = ((0 << STM_TIM23_CCMR1_OC2CE) |
 257                                (STM_TIM23_CCMR1_OC2M_FROZEN << STM_TIM23_CCMR1_OC2M) |
 258                                (0 << STM_TIM23_CCMR1_OC2PE) |
 259                                (0 << STM_TIM23_CCMR1_OC2FE) |
 260                                (STM_TIM23_CCMR1_CC2S_OUTPUT << STM_TIM23_CCMR1_CC2S) |
 261
 262                                (0 << STM_TIM23_CCMR1_OC1CE) |
 263                                (STM_TIM23_CCMR1_OC1M_TOGGLE << STM_TIM23_CCMR1_OC1M) |
 264                                (0 << STM_TIM23_CCMR1_OC1PE) |
 265                                (0 << STM_TIM23_CCMR1_OC1FE) |
 266                                (STM_TIM23_CCMR1_CC1S_OUTPUT << STM_TIM23_CCMR1_CC1S));
 267
 268                 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
 269                               (0 << STM_TIM23_CCER_CC4E) |
 270                               (0 << STM_TIM23_CCER_CC3NP) |
 271                               (0 << STM_TIM23_CCER_CC3P) |
 272                               (0 << STM_TIM23_CCER_CC3E) |
 273                               (0 << STM_TIM23_CCER_CC2NP) |
 274                               (0 << STM_TIM23_CCER_CC2P) |
 275                               (0 << STM_TIM23_CCER_CC2E) |
 276                               (0 << STM_TIM23_CCER_CC1P) |
 277                               (1 << STM_TIM23_CCER_CC1E));
 278 #endif
 279 #if BEEPER_CHANNEL == 2
 280                 timer.ccmr1 = ((0 << STM_TIM23_CCMR1_OC2CE) |
 281                                (STM_TIM23_CCMR1_OC2M_TOGGLE << STM_TIM23_CCMR1_OC2M) |
 282                                (0 << STM_TIM23_CCMR1_OC2PE) |
 283                                (0 << STM_TIM23_CCMR1_OC2FE) |
 284                                (STM_TIM23_CCMR1_CC2S_OUTPUT << STM_TIM23_CCMR1_CC2S) |
 285
 286                                (0 << STM_TIM23_CCMR1_OC1CE) |
 287                                (STM_TIM23_CCMR1_OC1M_FROZEN << STM_TIM23_CCMR1_OC1M) |
 288                                (0 << STM_TIM23_CCMR1_OC1PE) |
 289                                (0 << STM_TIM23_CCMR1_OC1FE) |
 290                                (STM_TIM23_CCMR1_CC1S_OUTPUT << STM_TIM23_CCMR1_CC1S));
 291
 292                 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
 293                               (0 << STM_TIM23_CCER_CC4E) |
 294                               (0 << STM_TIM23_CCER_CC3NP) |
 295                               (0 << STM_TIM23_CCER_CC3P) |
 296                               (0 << STM_TIM23_CCER_CC3E) |
 297                               (0 << STM_TIM23_CCER_CC2NP) |
 298                               (0 << STM_TIM23_CCER_CC2P) |
 299                               (1 << STM_TIM23_CCER_CC2E) |
 300                               (0 << STM_TIM23_CCER_CC1P) |
 301                               (0 << STM_TIM23_CCER_CC1E));
 302 #endif
 303 #if BEEPER_CHANNEL == 3
 304                 timer.ccmr2 = ((0 << STM_TIM23_CCMR2_OC4CE) |
 305                                (STM_TIM23_CCMR2_OC4M_FROZEN << STM_TIM23_CCMR2_OC4M) |
 306                                (0 << STM_TIM23_CCMR2_OC4PE) |
 307                                (0 << STM_TIM23_CCMR2_OC4FE) |
 308                                (STM_TIM23_CCMR2_CC4S_OUTPUT << STM_TIM23_CCMR2_CC4S) |
 309
 310                                (0 << STM_TIM23_CCMR2_OC3CE) |
 311                                (STM_TIM23_CCMR2_OC3M_TOGGLE << STM_TIM23_CCMR2_OC3M) |
 312                                (0 << STM_TIM23_CCMR2_OC3PE) |
 313                                (0 << STM_TIM23_CCMR2_OC3FE) |
 314                                (STM_TIM23_CCMR2_CC3S_OUTPUT << STM_TIM23_CCMR2_CC3S));
 315
 316                 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
 317                               (0 << STM_TIM23_CCER_CC4E) |
 318                               (0 << STM_TIM23_CCER_CC3NP) |
 319                               (0 << STM_TIM23_CCER_CC3P) |
 320                               (1 << STM_TIM23_CCER_CC3E) |
 321                               (0 << STM_TIM23_CCER_CC2NP) |
 322                               (0 << STM_TIM23_CCER_CC2P) |
 323                               (0 << STM_TIM23_CCER_CC2E) |
 324                               (0 << STM_TIM23_CCER_CC1P) |
 325                               (0 << STM_TIM23_CCER_CC1E));
 326 #endif
 327 #if BEEPER_CHANNEL == 4
 328                 timer.ccmr2 = ((0 << STM_TIM23_CCMR2_OC4CE) |
 329                                (STM_TIM23_CCMR2_OC4M_TOGGLE << STM_TIM23_CCMR2_OC4M) |
 330                                (0 << STM_TIM23_CCMR2_OC4PE) |
 331                                (0 << STM_TIM23_CCMR2_OC4FE) |
 332                                (STM_TIM23_CCMR2_CC4S_OUTPUT << STM_TIM23_CCMR2_CC4S) |
 333
 334                                (0 << STM_TIM23_CCMR2_OC3CE) |
 335                                (STM_TIM23_CCMR2_OC3M_FROZEN << STM_TIM23_CCMR2_OC3M) |
 336                                (0 << STM_TIM23_CCMR2_OC3PE) |
 337                                (0 << STM_TIM23_CCMR2_OC3FE) |
 338                                (STM_TIM23_CCMR2_CC3S_OUTPUT << STM_TIM23_CCMR2_CC3S));
 339
 340                 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
 341                               (1 << STM_TIM23_CCER_CC4E) |
 342                               (0 << STM_TIM23_CCER_CC3NP) |
 343                               (0 << STM_TIM23_CCER_CC3P) |
 344                               (0 << STM_TIM23_CCER_CC3E) |
 345                               (0 << STM_TIM23_CCER_CC2NP) |
 346                               (0 << STM_TIM23_CCER_CC2P) |
 347                               (0 << STM_TIM23_CCER_CC2E) |
 348                               (0 << STM_TIM23_CCER_CC1P) |
 349                               (0 << STM_TIM23_CCER_CC1E));
 350 #endif
 351                 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
 352
 353                 timer.cr1 = ((STM_TIM23_CR1_CKD_1 << STM_TIM23_CR1_CKD) |
 354                              (0 << STM_TIM23_CR1_ARPE) |
 355                              (STM_TIM23_CR1_CMS_EDGE << STM_TIM23_CR1_CMS) |
 356                              (0 << STM_TIM23_CR1_DIR) |
 357                              (0 << STM_TIM23_CR1_OPM) |
 358                              (0 << STM_TIM23_CR1_URS) |
 359                              (0 << STM_TIM23_CR1_UDIS) |
 360                              (1 << STM_TIM23_CR1_CEN));
 361
 362                 /* Update the values */
 363                 timer.egr = (1 << STM_TIM23_EGR_UG);
 364 #endif
 365         }
 366 }
 367
 368 void
 369 ao_beep_for(uint8_t beep, uint16_t ticks) __reentrant
 370 {
 371         ao_beep(beep);
 372         ao_delay(ticks);
 373         ao_beep(0);
 374 }
 375
 376 void
 377 ao_beep_init(void)
 378 {
 379         ao_enable_port(BEEPER_PORT);
 380         stm_afr_set(BEEPER_PORT, BEEPER_PIN, STM_AFR_AF2);
 381
 382         /* Leave the timer off until requested */
 383         stm_rcc_enr &= ~(1 << STM_RCC_TIMER);
 384 }