2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
27 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
29 #define AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
30 #define AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
31 #define AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
32 #define AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
33 #define AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
34 #define AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
35 #define AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
36 #define AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
38 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_24MHz
40 /* Companion bus wants something no faster than 200kHz */
42 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_187500Hz
44 #define AO_SPI_CONFIG_1 0x00
45 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
46 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
48 #define AO_SPI_CONFIG_2 0x04
49 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
50 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
52 #define AO_SPI_CONFIG_3 0x08
53 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
55 #define AO_SPI_CONFIG_NONE 0x0c
57 #define AO_SPI_INDEX_MASK 0x01
58 #define AO_SPI_CONFIG_MASK 0x0c
60 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
61 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
62 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
64 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
65 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
67 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
68 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
71 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
74 ao_spi_get(uint8_t spi_index, uint32_t speed);
77 ao_spi_put(uint8_t spi_index);
80 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
83 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
86 ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
89 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
92 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
94 extern uint16_t ao_spi_speed[STM_NUM_SPI];
99 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
100 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
102 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
103 ao_spi_get(bus, speed); \
104 ao_spi_set_cs(reg,mask); \
107 static inline uint8_t
108 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
110 if (!ao_spi_try_get(bus, speed, task_id))
112 ao_spi_set_cs(reg, mask);
116 #define ao_spi_put_mask(reg,mask,bus) do { \
117 ao_spi_clr_cs(reg,mask); \
121 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
122 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
124 extern struct ao_power ao_power_gpioa;
125 extern struct ao_power ao_power_gpiob;
126 extern struct ao_power ao_power_gpioc;
127 extern struct ao_power ao_power_gpiof;
129 static inline void ao_enable_port(struct stm_gpio *port)
131 if ((port) == &stm_gpioa) {
132 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
133 ao_power_register(&ao_power_gpioa);
134 } else if ((port) == &stm_gpiob) {
135 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
136 ao_power_register(&ao_power_gpiob);
137 } else if ((port) == &stm_gpioc) {
138 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
139 ao_power_register(&ao_power_gpioc);
140 } else if ((port) == &stm_gpiof) {
141 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
142 ao_power_register(&ao_power_gpiof);
146 static inline void ao_disable_port(struct stm_gpio *port)
148 if ((port) == &stm_gpioa) {
149 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN);
150 ao_power_unregister(&ao_power_gpioa);
151 } else if ((port) == &stm_gpiob) {
152 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN);
153 ao_power_unregister(&ao_power_gpiob);
154 } else if ((port) == &stm_gpioc) {
155 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN);
156 ao_power_unregister(&ao_power_gpioc);
157 } else if ((port) == &stm_gpiof) {
158 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN);
159 ao_power_unregister(&ao_power_gpiof);
163 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
165 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
167 #define ao_enable_output(port,bit,pin,v) do { \
168 ao_enable_port(port); \
169 ao_gpio_set(port, bit, pin, v); \
170 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
173 #define ao_gpio_set_mode(port,bit,mode) do { \
174 if (mode == AO_EXTI_MODE_PULL_UP) \
175 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
176 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
177 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
179 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
182 #define ao_enable_input(port,bit,mode) do { \
183 ao_enable_port(port); \
184 stm_moder_set(port, bit, STM_MODER_INPUT); \
185 ao_gpio_set_mode(port, bit, mode); \
188 #define ao_enable_cs(port,bit) do { \
189 ao_enable_output(port, bit, pin, 1); \
192 #define ao_spi_init_cs(port, mask) do { \
193 ao_enable_port(port); \
194 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
195 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
196 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
197 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
198 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
199 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
200 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
201 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
202 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
203 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
204 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
205 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
206 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
207 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
208 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
209 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
215 extern uint8_t ao_dma_done[STM_NUM_DMA];
218 ao_dma_set_transfer(uint8_t index,
219 volatile void *peripheral,
225 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
228 ao_dma_start(uint8_t index);
231 ao_dma_done_transfer(uint8_t index);
234 ao_dma_abort(uint8_t index);
237 ao_dma_alloc(uint8_t index);
245 ao_i2c_get(uint8_t i2c_index);
248 ao_i2c_start(uint8_t i2c_index, uint16_t address);
251 ao_i2c_put(uint8_t i2c_index);
254 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
257 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
262 /* ao_serial_stm.c */
263 struct ao_stm_usart {
264 struct ao_fifo rx_fifo;
265 struct ao_fifo tx_fifo;
266 struct stm_usart *reg;
271 extern struct ao_stm_usart ao_stm_usart1;
275 extern struct ao_stm_usart ao_stm_usart2;
279 extern struct ao_stm_usart ao_stm_usart3;
282 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
284 typedef uint32_t ao_arch_irq_t;
286 static inline uint32_t
287 ao_arch_irqsave(void) {
289 asm("mrs %0,primask" : "=&r" (primask));
290 ao_arch_block_interrupts();
295 ao_arch_irqrestore(uint32_t primask) {
296 asm("msr primask,%0" : : "r" (primask));
300 ao_arch_memory_barrier() {
301 asm volatile("" ::: "memory");
306 ao_arch_init_stack(struct ao_task *task, void *start)
308 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
309 uint32_t a = (uint32_t) start;
312 /* Return address (goes into LR) */
315 /* Clear register values r0-r7 */
323 /* PRIMASK with interrupts enabled */
329 static inline void ao_arch_save_regs(void) {
330 /* Save general registers */
331 asm("push {r0-r7,lr}\n");
338 asm("mrs r0,primask");
342 static inline void ao_arch_save_stack(void) {
344 asm("mov %0,sp" : "=&r" (sp) );
345 ao_cur_task->sp = (sp);
346 if ((uint8_t *) sp < &ao_cur_task->stack[0])
347 ao_panic (AO_PANIC_STACK);
350 static inline void ao_arch_restore_stack(void) {
352 sp = (uint32_t) ao_cur_task->sp;
355 asm("mov sp, %0" : : "r" (sp) );
357 /* Restore PRIMASK */
359 asm("msr primask,r0");
363 asm("msr apsr_nczvq,r0");
365 /* Restore general registers */
366 asm("pop {r0-r7,pc}\n");
369 #ifndef HAS_SAMPLE_PROFILE
370 #define HAS_SAMPLE_PROFILE 0
373 #if !HAS_SAMPLE_PROFILE
374 #define HAS_ARCH_START_SCHEDULER 1
376 static inline void ao_arch_start_scheduler(void) {
380 asm("mrs %0,msp" : "=&r" (sp));
381 asm("msr psp,%0" : : "r" (sp));
382 asm("mrs %0,control" : "=&r" (control));
384 asm("msr control,%0" : : "r" (control));
389 #define ao_arch_isr_stack()
393 #define ao_arch_wait_interrupt() do { \
395 ao_arch_release_interrupts(); \
396 asm(".global ao_idle_loc\nao_idle_loc:"); \
397 ao_arch_block_interrupts(); \
400 #define ao_arch_critical(b) do { \
401 uint32_t __mask = ao_arch_irqsave(); \
402 do { b } while (0); \
403 ao_arch_irqrestore(__mask); \
413 ao_usb_write(uint16_t *buffer, uint16_t len);
416 ao_usb_write2(uint16_t *buffer, uint16_t len);
417 #endif /* AO_USB_DIRECTIO */
419 #endif /* _AO_ARCH_FUNCS_H_ */