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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_adc_fast.h>
  20
  21 uint16_t ao_adc_ring[AO_ADC_RING_SIZE];
  22
  23 uint16_t ao_adc_ring_head, ao_adc_ring_tail;
  24 uint8_t ao_adc_running;
  25
  26 /*
  27  * Callback from DMA ISR
  28  *
  29  * Mark time in ring, shut down DMA engine
  30  */
  31 static void ao_adc_dma_done(int index)
  32 {
  33         (void) index;
  34         ao_adc_ring_head += AO_ADC_RING_CHUNK;
  35         if (ao_adc_ring_head == AO_ADC_RING_SIZE)
  36                 ao_adc_ring_head = 0;
  37         ao_adc_running = 0;
  38         ao_wakeup(&ao_adc_ring_head);
  39         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  40 }
  41
  42 void
  43 _ao_adc_start(void)
  44 {
  45         uint16_t        *buf;
  46
  47         if (ao_adc_running)
  48                 return;
  49         if (_ao_adc_space() < AO_ADC_RING_CHUNK)
  50                 return;
  51         ao_adc_running = 1;
  52         buf = ao_adc_ring + ao_adc_ring_head;
  53         stm_adc.isr = 0;
  54         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  55                             &stm_adc.dr,
  56                             buf,
  57                             AO_ADC_RING_CHUNK,
  58                             (0 << STM_DMA_CCR_MEM2MEM) |
  59                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  60                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  61                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  62                             (1 << STM_DMA_CCR_MINC) |
  63                             (0 << STM_DMA_CCR_PINC) |
  64                             (0 << STM_DMA_CCR_CIRC) |
  65                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  66         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
  67         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  68
  69         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  70 }
  71
  72 void
  73 ao_adc_init(void)
  74 {
  75         uint32_t        chselr;
  76         int             i;
  77
  78         /* Reset ADC */
  79         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
  80         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
  81
  82         /* Turn on ADC pins */
  83         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
  84
  85 #ifdef AO_ADC_PIN0_PORT
  86         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
  87 #endif
  88 #ifdef AO_ADC_PIN1_PORT
  89         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
  90 #endif
  91 #ifdef AO_ADC_PIN2_PORT
  92         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
  93 #endif
  94 #ifdef AO_ADC_PIN3_PORT
  95         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
  96 #endif
  97 #ifdef AO_ADC_PIN4_PORT
  98         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
  99 #endif
 100 #ifdef AO_ADC_PIN5_PORT
 101         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 102 #endif
 103 #ifdef AO_ADC_PIN6_PORT
 104         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 105 #endif
 106 #ifdef AO_ADC_PIN7_PORT
 107         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 108 #endif
 109 #ifdef AO_ADC_PIN24_PORT
 110         #error "Too many ADC ports"
 111 #endif
 112
 113         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 114
 115         chselr = 0;
 116 #if AO_NUM_ADC > 0
 117         chselr |= (1 << AO_ADC_PIN0_CH);
 118 #endif
 119 #if AO_NUM_ADC > 1
 120         chselr |= (1 << AO_ADC_PIN1_CH);
 121 #endif
 122 #if AO_NUM_ADC > 2
 123         chselr |= (1 << AO_ADC_PIN2_CH);
 124 #endif
 125 #if AO_NUM_ADC > 3
 126         chselr |= (1 << AO_ADC_PIN3_CH);
 127 #endif
 128 #if AO_NUM_ADC > 4
 129         chselr |= (1 << AO_ADC_PIN4_CH);
 130 #endif
 131 #if AO_NUM_ADC > 5
 132         chselr |= (1 << AO_ADC_PIN5_CH);
 133 #endif
 134 #if AO_NUM_ADC > 6
 135         chselr |= (1 << AO_ADC_PIN6_CH);
 136 #endif
 137 #if AO_NUM_ADC > 7
 138         chselr |= (1 << AO_ADC_PIN7_CH);
 139 #endif
 140 #if AO_NUM_ADC > 8
 141 #error Need more ADC defines
 142 #endif
 143         stm_adc.chselr = chselr;
 144
 145         /* Set the clock */
 146         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 147
 148         /* Shortest sample time */
 149         stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
 150
 151         /* Calibrate */
 152         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 153         for (i = 0; i < 0xf000; i++) {
 154                 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
 155                         break;
 156         }
 157
 158         /* Enable */
 159         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 160         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 161                 ;
 162
 163         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
 164                          (0 << STM_ADC_CFGR1_AWDEN) |
 165                          (0 << STM_ADC_CFGR1_AWDSGL) |
 166                          (0 << STM_ADC_CFGR1_DISCEN) |
 167                          (0 << STM_ADC_CFGR1_AUTOOFF) |
 168                          (1 << STM_ADC_CFGR1_WAIT) |
 169                          (1 << STM_ADC_CFGR1_CONT) |
 170                          (0 << STM_ADC_CFGR1_OVRMOD) |
 171                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
 172                          (0 << STM_ADC_CFGR1_ALIGN) |
 173                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
 174                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
 175                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
 176                          (1 << STM_ADC_CFGR1_DMAEN));
 177         stm_adc.ccr = 0;
 178
 179         /* Clear any stale status bits */
 180         stm_adc.isr = 0;
 181
 182         /* Turn on syscfg */
 183         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 184
 185         /* Set ADC to use DMA channel 1 (option 1) */
 186         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 187
 188         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 189         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
 190 }