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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_adc_fast.h>
  20
  21 static uint8_t                  ao_adc_done;
  22
  23 /*
  24  * Callback from DMA ISR
  25  *
  26  * Mark time in ring, shut down DMA engine
  27  */
  28 static void ao_adc_dma_done(int index)
  29 {
  30         (void) index;
  31         ao_adc_done = 1;
  32         ao_wakeup(&ao_adc_done);
  33 }
  34
  35 /*
  36  * Start the ADC sequence using the DMA engine
  37  */
  38 void
  39 ao_adc_read(uint16_t *dest, int len)
  40 {
  41         ao_adc_done = 0;
  42         stm_adc.isr = 0;
  43         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  44                             &stm_adc.dr,
  45                             dest,
  46                             len,
  47                             (0 << STM_DMA_CCR_MEM2MEM) |
  48                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  49                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  50                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  51                             (1 << STM_DMA_CCR_MINC) |
  52                             (0 << STM_DMA_CCR_PINC) |
  53                             (0 << STM_DMA_CCR_CIRC) |
  54                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  55         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
  56         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  57
  58         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  59         ao_arch_block_interrupts();
  60         while (!ao_adc_done)
  61                 ao_sleep(&ao_adc_done);
  62         ao_arch_release_interrupts();
  63
  64         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  65
  66         stm_adc.cr |= (1 << STM_ADC_CR_ADSTP);
  67         while ((stm_adc.cr & (1 << STM_ADC_CR_ADSTP)) != 0)
  68                 ;
  69 }
  70
  71 void
  72 ao_adc_init(void)
  73 {
  74         uint32_t        chselr;
  75         int             i;
  76
  77         /* Reset ADC */
  78         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
  79         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
  80
  81         /* Turn on ADC pins */
  82         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
  83
  84 #ifdef AO_ADC_PIN0_PORT
  85         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
  86 #endif
  87 #ifdef AO_ADC_PIN1_PORT
  88         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
  89 #endif
  90 #ifdef AO_ADC_PIN2_PORT
  91         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
  92 #endif
  93 #ifdef AO_ADC_PIN3_PORT
  94         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
  95 #endif
  96 #ifdef AO_ADC_PIN4_PORT
  97         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
  98 #endif
  99 #ifdef AO_ADC_PIN5_PORT
 100         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 101 #endif
 102 #ifdef AO_ADC_PIN6_PORT
 103         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 104 #endif
 105 #ifdef AO_ADC_PIN7_PORT
 106         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 107 #endif
 108 #ifdef AO_ADC_PIN24_PORT
 109         #error "Too many ADC ports"
 110 #endif
 111
 112         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 113
 114         chselr = 0;
 115 #if AO_NUM_ADC > 0
 116         chselr |= (1 << AO_ADC_PIN0_CH);
 117 #endif
 118 #if AO_NUM_ADC > 1
 119         chselr |= (1 << AO_ADC_PIN1_CH);
 120 #endif
 121 #if AO_NUM_ADC > 2
 122         chselr |= (1 << AO_ADC_PIN2_CH);
 123 #endif
 124 #if AO_NUM_ADC > 3
 125         chselr |= (1 << AO_ADC_PIN3_CH);
 126 #endif
 127 #if AO_NUM_ADC > 4
 128         chselr |= (1 << AO_ADC_PIN4_CH);
 129 #endif
 130 #if AO_NUM_ADC > 5
 131         chselr |= (1 << AO_ADC_PIN5_CH);
 132 #endif
 133 #if AO_NUM_ADC > 6
 134         chselr |= (1 << AO_ADC_PIN6_CH);
 135 #endif
 136 #if AO_NUM_ADC > 7
 137         chselr |= (1 << AO_ADC_PIN7_CH);
 138 #endif
 139 #if AO_NUM_ADC > 8
 140 #error Need more ADC defines
 141 #endif
 142         stm_adc.chselr = chselr;
 143
 144         /* Set the clock */
 145         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 146
 147         /* Shortest sample time */
 148         stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
 149
 150         /* Calibrate */
 151         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 152         for (i = 0; i < 0xf000; i++) {
 153                 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
 154                         break;
 155         }
 156
 157         /* Enable */
 158         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 159         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 160                 ;
 161
 162         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
 163                          (0 << STM_ADC_CFGR1_AWDEN) |
 164                          (0 << STM_ADC_CFGR1_AWDSGL) |
 165                          (0 << STM_ADC_CFGR1_DISCEN) |
 166                          (0 << STM_ADC_CFGR1_AUTOOFF) |
 167                          (1 << STM_ADC_CFGR1_WAIT) |
 168                          (1 << STM_ADC_CFGR1_CONT) |
 169                          (0 << STM_ADC_CFGR1_OVRMOD) |
 170                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
 171                          (0 << STM_ADC_CFGR1_ALIGN) |
 172                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
 173                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
 174                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
 175                          (1 << STM_ADC_CFGR1_DMAEN));
 176         stm_adc.ccr = 0;
 177
 178         /* Clear any stale status bits */
 179         stm_adc.isr = 0;
 180
 181         /* Turn on syscfg */
 182         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 183
 184         /* Set ADC to use DMA channel 1 (option 1) */
 185         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 186
 187         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 188 }