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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_adc_fast.h>
  20
  21 uint16_t ao_adc_ring[AO_ADC_RING_SIZE] __attribute__((aligned(4)));
  22
  23 /* Maximum number of samples fetched per _ao_adc_start call */
  24 #define AO_ADC_RING_CHUNK       (AO_ADC_RING_SIZE >> 1)
  25
  26 uint16_t ao_adc_ring_head, ao_adc_ring_remain;
  27 uint16_t ao_adc_running;
  28
  29 /*
  30  * Callback from DMA ISR
  31  *
  32  * Wakeup any waiting processes, mark the DMA as done, start the ADC
  33  * if there's still lots of space in the ring
  34  */
  35 static void ao_adc_dma_done(int index)
  36 {
  37         (void) index;
  38         ao_adc_ring_head += ao_adc_running;
  39         ao_adc_ring_remain += ao_adc_running;
  40         if (ao_adc_ring_head == AO_ADC_RING_SIZE)
  41                 ao_adc_ring_head = 0;
  42         ao_adc_running = 0;
  43         ao_wakeup(&ao_adc_ring_head);
  44         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  45         _ao_adc_start();
  46 }
  47
  48 void
  49 _ao_adc_start(void)
  50 {
  51         uint16_t        *buf;
  52         uint16_t        count;
  53
  54         if (ao_adc_running)
  55                 return;
  56         count = _ao_adc_space();
  57         if (count == 0)
  58                 return;
  59         if (count > AO_ADC_RING_CHUNK)
  60                 count = AO_ADC_RING_CHUNK;
  61         ao_adc_running = count;
  62         buf = ao_adc_ring + ao_adc_ring_head;
  63         stm_adc.isr = 0;
  64         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  65                             &stm_adc.dr,
  66                             buf,
  67                             count,
  68                             (0 << STM_DMA_CCR_MEM2MEM) |
  69                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  70                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  71                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  72                             (1 << STM_DMA_CCR_MINC) |
  73                             (0 << STM_DMA_CCR_PINC) |
  74                             (0 << STM_DMA_CCR_CIRC) |
  75                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
  76                             (1 << STM_DMA_CCR_TCIE));
  77
  78         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
  79         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  80
  81         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  82 }
  83
  84 void
  85 ao_adc_init(void)
  86 {
  87         uint32_t        chselr;
  88
  89         /* Reset ADC */
  90         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
  91         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
  92
  93         /* Turn on ADC pins */
  94         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
  95
  96 #ifdef AO_ADC_PIN0_PORT
  97         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
  98 #endif
  99 #ifdef AO_ADC_PIN1_PORT
 100         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 101 #endif
 102 #ifdef AO_ADC_PIN2_PORT
 103         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 104 #endif
 105 #ifdef AO_ADC_PIN3_PORT
 106         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 107 #endif
 108 #ifdef AO_ADC_PIN4_PORT
 109         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 110 #endif
 111 #ifdef AO_ADC_PIN5_PORT
 112         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 113 #endif
 114 #ifdef AO_ADC_PIN6_PORT
 115         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 116 #endif
 117 #ifdef AO_ADC_PIN7_PORT
 118         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 119 #endif
 120 #ifdef AO_ADC_PIN24_PORT
 121         #error "Too many ADC ports"
 122 #endif
 123
 124         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 125
 126         chselr = 0;
 127 #if AO_NUM_ADC > 0
 128         chselr |= (1 << AO_ADC_PIN0_CH);
 129 #endif
 130 #if AO_NUM_ADC > 1
 131         chselr |= (1 << AO_ADC_PIN1_CH);
 132 #endif
 133 #if AO_NUM_ADC > 2
 134         chselr |= (1 << AO_ADC_PIN2_CH);
 135 #endif
 136 #if AO_NUM_ADC > 3
 137         chselr |= (1 << AO_ADC_PIN3_CH);
 138 #endif
 139 #if AO_NUM_ADC > 4
 140         chselr |= (1 << AO_ADC_PIN4_CH);
 141 #endif
 142 #if AO_NUM_ADC > 5
 143         chselr |= (1 << AO_ADC_PIN5_CH);
 144 #endif
 145 #if AO_NUM_ADC > 6
 146         chselr |= (1 << AO_ADC_PIN6_CH);
 147 #endif
 148 #if AO_NUM_ADC > 7
 149         chselr |= (1 << AO_ADC_PIN7_CH);
 150 #endif
 151 #if AO_NUM_ADC > 8
 152 #error Need more ADC defines
 153 #endif
 154
 155         /* Set the clock */
 156         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 157
 158         /* Shortest sample time */
 159         stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
 160
 161         /* Turn off enable and start */
 162         stm_adc.cr &= ~((1 << STM_ADC_CR_ADEN) | (1 << STM_ADC_CR_ADSTART));
 163
 164         /* Calibrate */
 165         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 166         while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0)
 167                 ;
 168
 169         /* Enable */
 170         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 171         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 172                 ;
 173
 174         stm_adc.chselr = chselr;
 175
 176         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
 177                          (0 << STM_ADC_CFGR1_AWDEN) |
 178                          (0 << STM_ADC_CFGR1_AWDSGL) |
 179                          (0 << STM_ADC_CFGR1_DISCEN) |
 180                          (0 << STM_ADC_CFGR1_AUTOOFF) |
 181                          (0 << STM_ADC_CFGR1_WAIT) |
 182                          (1 << STM_ADC_CFGR1_CONT) |
 183                          (1 << STM_ADC_CFGR1_OVRMOD) |
 184                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
 185                          (0 << STM_ADC_CFGR1_ALIGN) |
 186                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
 187                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
 188                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
 189                          (1 << STM_ADC_CFGR1_DMAEN));
 190         stm_adc.ccr = 0;
 191
 192         /* Clear any stale status bits */
 193         stm_adc.isr = 0;
 194
 195         /* Turn on syscfg */
 196         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 197
 198         /* Set ADC to use DMA channel 1 (option 1) */
 199         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 200
 201         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 202 }