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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32L0_H_
  20 #define _STM32L0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26
  27 struct stm_gpio {
  28         vuint32_t       moder;
  29         vuint32_t       otyper;
  30         vuint32_t       ospeedr;
  31         vuint32_t       pupdr;
  32
  33         vuint32_t       idr;
  34         vuint32_t       odr;
  35         vuint32_t       bsrr;
  36         vuint32_t       lckr;
  37
  38         vuint32_t       afrl;
  39         vuint32_t       afrh;
  40         vuint32_t       brr;
  41 };
  42
  43 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  44 #define STM_MODER_MASK                  3
  45 #define STM_MODER_INPUT                 0
  46 #define STM_MODER_OUTPUT                1
  47 #define STM_MODER_ALTERNATE             2
  48 #define STM_MODER_ANALOG                3
  49
  50 static inline void
  51 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  52         gpio->moder = ((gpio->moder &
  53                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  54                        value << STM_MODER_SHIFT(pin));
  55 }
  56
  57 static inline uint32_t
  58 stm_spread_mask(uint16_t mask) {
  59         uint32_t m = mask;
  60
  61         /* 0000000000000000mmmmmmmmmmmmmmmm */
  62         m = (m & 0xff) | ((m & 0xff00) << 8);
  63         /* 00000000mmmmmmmm00000000mmmmmmmm */
  64         m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4);
  65         /* 0000mmmm0000mmmm0000mmmm0000mmmm */
  66         m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2);
  67         /* 00mm00mm00mm00mm00mm00mm00mm00mm */
  68         m = (m & 0x11111111) | ((m & 0x22222222) << 2);
  69         /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */
  70         return m;
  71 }
  72
  73 static inline void
  74 stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
  75         uint32_t        bits32 = stm_spread_mask(mask);
  76         uint32_t        mask32 = 3 * bits32;
  77         uint32_t        value32 = (value & 3) * bits32;
  78
  79         gpio->moder = ((gpio->moder & ~mask32) | value32);
  80 }
  81
  82 static inline uint32_t
  83 stm_moder_get(struct stm_gpio *gpio, int pin) {
  84         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  85 }
  86
  87 #define STM_OTYPER_SHIFT(pin)           (pin)
  88 #define STM_OTYPER_MASK                 1
  89 #define STM_OTYPER_PUSH_PULL            0
  90 #define STM_OTYPER_OPEN_DRAIN           1
  91
  92 static inline void
  93 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  94         gpio->otyper = ((gpio->otyper &
  95                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  96                         value << STM_OTYPER_SHIFT(pin));
  97 }
  98
  99 static inline uint32_t
 100 stm_otyper_get(struct stm_gpio *gpio, int pin) {
 101         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
 102 }
 103
 104 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
 105 #define STM_OSPEEDR_MASK                3
 106 #define STM_OSPEEDR_LOW                 0
 107 #define STM_OSPEEDR_MEDIUM              1
 108 #define STM_OSPEEDR_HIGH                2
 109 #define STM_OSPEEDR_VERY_HIGH           3
 110
 111 static inline void
 112 stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 113         gpio->ospeedr = ((gpio->ospeedr &
 114                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
 115                        value << STM_OSPEEDR_SHIFT(pin));
 116 }
 117
 118 static inline void
 119 stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 120         uint32_t        bits32 = stm_spread_mask(mask);
 121         uint32_t        mask32 = 3 * bits32;
 122         uint32_t        value32 = (value & 3) * bits32;
 123
 124         gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32);
 125 }
 126
 127 static inline uint32_t
 128 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
 129         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
 130 }
 131
 132 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 133 #define STM_PUPDR_MASK                  3
 134 #define STM_PUPDR_NONE                  0
 135 #define STM_PUPDR_PULL_UP               1
 136 #define STM_PUPDR_PULL_DOWN             2
 137 #define STM_PUPDR_RESERVED              3
 138
 139 static inline void
 140 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 141         gpio->pupdr = ((gpio->pupdr &
 142                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 143                        value << STM_PUPDR_SHIFT(pin));
 144 }
 145
 146 static inline void
 147 stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 148         uint32_t        bits32 = stm_spread_mask(mask);
 149         uint32_t        mask32 = 3 * bits32;
 150         uint32_t        value32 = (value & 3) * bits32;
 151
 152         gpio->pupdr = (gpio->pupdr & ~mask32) | value32;
 153 }
 154
 155 static inline uint32_t
 156 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 157         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 158 }
 159
 160 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 161 #define STM_AFR_MASK                    0xf
 162 #define STM_AFR_NONE                    0
 163 #define STM_AFR_AF0                     0x0
 164 #define STM_AFR_AF1                     0x1
 165 #define STM_AFR_AF2                     0x2
 166 #define STM_AFR_AF3                     0x3
 167 #define STM_AFR_AF4                     0x4
 168 #define STM_AFR_AF5                     0x5
 169 #define STM_AFR_AF6                     0x6
 170 #define STM_AFR_AF7                     0x7
 171 #define STM_AFR_AF8                     0x8
 172 #define STM_AFR_AF9                     0x9
 173 #define STM_AFR_AF10                    0xa
 174 #define STM_AFR_AF11                    0xb
 175 #define STM_AFR_AF12                    0xc
 176 #define STM_AFR_AF13                    0xd
 177 #define STM_AFR_AF14                    0xe
 178 #define STM_AFR_AF15                    0xf
 179
 180 static inline void
 181 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 182         /*
 183          * Set alternate pin mode too
 184          */
 185         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 186         if (pin < 8)
 187                 gpio->afrl = ((gpio->afrl &
 188                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 189                               value << STM_AFR_SHIFT(pin));
 190         else {
 191                 pin -= 8;
 192                 gpio->afrh = ((gpio->afrh &
 193                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 194                               value << STM_AFR_SHIFT(pin));
 195         }
 196 }
 197
 198 static inline uint32_t
 199 stm_afr_get(struct stm_gpio *gpio, int pin) {
 200         if (pin < 8)
 201                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 202         else {
 203                 pin -= 8;
 204                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 205         }
 206 }
 207
 208 static inline void
 209 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 210         /* Use the bit set/reset register to do this atomically */
 211         gpio->bsrr = value ? (1 << pin) : (1 << (pin + 16));
 212 }
 213
 214 static inline void
 215 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
 216         /* Use the bit set/reset register to do this atomically */
 217         gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
 218 }
 219
 220 static inline void
 221 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 222         gpio->bsrr = bits;
 223 }
 224
 225 static inline void
 226 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 227         gpio->bsrr = ((uint32_t) bits) << 16;
 228 }
 229
 230 static inline uint8_t
 231 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 232         return (gpio->idr >> pin) & 1;
 233 }
 234
 235 static inline uint16_t
 236 stm_gpio_get_all(struct stm_gpio *gpio) {
 237         return gpio->idr;
 238 }
 239
 240 /*
 241  * We can't define these in registers.ld or our fancy
 242  * ao_enable_gpio macro will expand into a huge pile of code
 243  * as the compiler won't do correct constant folding and
 244  * dead-code elimination
 245  */
 246
 247 extern struct stm_gpio stm_gpioa;
 248 extern struct stm_gpio stm_gpiob;
 249 extern struct stm_gpio stm_gpioc;
 250 extern struct stm_gpio stm_gpiod;
 251 extern struct stm_gpio stm_gpioe;
 252 extern struct stm_gpio stm_gpioh;
 253
 254 #define stm_gpiob  (*((struct stm_gpio *) 0x50000400))
 255 #define stm_gpioa  (*((struct stm_gpio *) 0x50000000))
 256
 257 struct stm_usart {
 258         vuint32_t       cr1;    /* control register 1 */
 259         vuint32_t       cr2;    /* control register 2 */
 260         vuint32_t       cr3;    /* control register 3 */
 261         vuint32_t       brr;    /* baud rate register */
 262
 263         vuint32_t       gtpr;   /* guard time and prescaler */
 264         vuint32_t       rtor;   /* receiver timeout register */
 265         vuint32_t       rqr;    /* request register */
 266         vuint32_t       isr;    /* interrupt and status register */
 267
 268         vuint32_t       icr;    /* interrupt flag clear register */
 269         vuint32_t       rdr;    /* receive data register */
 270         vuint32_t       tdr;    /* transmit data register */
 271 };
 272
 273 #define STM_USART_CR1_M1        28
 274 #define STM_USART_CR1_EOBIE     27
 275 #define STM_USART_CR1_RTOIE     26
 276 #define STM_USART_CR1_DEAT      21
 277 #define STM_USART_CR1_DEDT      16
 278 #define STM_USART_CR1_OVER8     15
 279 #define STM_USART_CR1_CMIE      14
 280 #define STM_USART_CR1_MME       13
 281 #define STM_USART_CR1_M0        12
 282 #define STM_USART_CR1_WAKE      11
 283 #define STM_USART_CR1_PCE       10
 284 #define STM_USART_CR1_PS        9
 285 #define STM_USART_CR1_PEIE      8
 286 #define STM_USART_CR1_TXEIE     7
 287 #define STM_USART_CR1_TCIE      6
 288 #define STM_USART_CR1_RXNEIE    5
 289 #define STM_USART_CR1_IDLEIE    4
 290 #define STM_USART_CR1_TE        3
 291 #define STM_USART_CR1_RE        2
 292 #define STM_USART_CR1_UESM      1
 293 #define STM_USART_CR1_UE        0
 294
 295 #define STM_USART_CR2_ADD       24
 296 #define STM_USART_CR2_RTOEN     23
 297 #define STM_USART_CR2_ABRMOD    21
 298 #define STM_USART_CR2_ABREN     20
 299 #define STM_USART_CR2_MSBFIRST  19
 300 #define STM_USART_CR2_DATAINV   18
 301 #define STM_USART_CR2_TXINV     17
 302 #define STM_USART_CR2_RXINV     16
 303 #define STM_USART_CR2_SWAP      15
 304 #define STM_USART_CR2_LINEN     14
 305 #define STM_USART_CR2_STOP      12
 306 #define STM_USART_CR2_CLKEN     11
 307 #define STM_USART_CR2_CPOL      10
 308 #define STM_USART_CR2_CHPA      9
 309 #define STM_USART_CR2_LBCL      8
 310 #define STM_USART_CR2_LBDIE     6
 311 #define STM_USART_CR2_LBDL      5
 312 #define STM_USART_CR2_ADDM7     4
 313
 314 #define STM_USART_CR3_WUFIE     22
 315 #define STM_USART_CR3_WUS       20
 316 #define STM_USART_CR3_SCARCNT   17
 317 #define STM_USART_CR3_DEP       15
 318 #define STM_USART_CR3_DEM       14
 319 #define STM_USART_CR3_DDRE      13
 320 #define STM_USART_CR3_OVRDIS    12
 321 #define STM_USART_CR3_ONEBIT    11
 322 #define STM_USART_CR3_CTIIE     10
 323 #define STM_USART_CR3_CTSE      9
 324 #define STM_USART_CR3_RTSE      8
 325 #define STM_USART_CR3_DMAT      7
 326 #define STM_USART_CR3_DMAR      6
 327 #define STM_USART_CR3_SCEN      5
 328 #define STM_USART_CR3_NACK      4
 329 #define STM_USART_CR3_HDSEL     3
 330 #define STM_USART_CR3_IRLP      2
 331 #define STM_USART_CR3_IREN      1
 332 #define STM_USART_CR3_EIE       0
 333
 334 #define STM_USART_GTPR_GT       8
 335 #define STM_USART_GTPR_PSC      0
 336
 337 #define STM_USART_RQR_TXFRQ     4
 338 #define STM_USART_RQR_RXFRQ     3
 339 #define STM_USART_RQR_MMRQ      2
 340 #define STM_USART_RQR_SBKRQ     1
 341 #define STM_USART_RQR_ABRRQ     0
 342
 343 #define STM_USART_ISR_REACK     22
 344 #define STM_USART_ISR_TEACK     21
 345 #define STM_USART_ISR_WUF       20
 346 #define STM_USART_ISR_RWU       19
 347 #define STM_USART_ISR_SBKF      18
 348 #define STM_USART_ISR_CMF       17
 349 #define STM_USART_ISR_BUSY      16
 350 #define STM_USART_ISR_ABRF      15
 351 #define STM_USART_ISR_ABRE      14
 352 #define STM_USART_ISR_EOBF      12
 353 #define STM_USART_ISR_RTOF      11
 354 #define STM_USART_ISR_CTS       10
 355 #define STM_USART_ISR_CTSIF     9
 356 #define STM_USART_ISR_LBDF      8
 357 #define STM_USART_ISR_TXE       7
 358 #define STM_USART_ISR_TC        6
 359 #define STM_USART_ISR_RXNE      5
 360 #define STM_USART_ISR_IDLE      4
 361 #define STM_USART_ISR_ORE       3
 362 #define STM_USART_ISR_NF        2
 363 #define STM_USART_ISR_FE        1
 364 #define STM_USART_ISR_PE        0
 365
 366 #define STM_USART_ICR_WUCF      20
 367 #define STM_USART_ICR_CMCF      17
 368 #define STM_USART_ICR_EOBCF     12
 369 #define STM_USART_ICR_RTOCF     11
 370 #define STM_USART_ICR_CTSCF     9
 371 #define STM_USART_ICR_LBDCF     8
 372 #define STM_USART_ICR_TCCF      6
 373 #define STM_USART_ICR_IDLECF    4
 374 #define STM_USART_ICR_ORECF     3
 375 #define STM_USART_ICR_NCF       2
 376 #define STM_USART_ICR_FECF      1
 377 #define STM_USART_ICR_PECF      0
 378
 379 extern struct stm_usart stm_usart1;
 380 extern struct stm_usart stm_usart2;
 381 #define stm_usart1 (*((struct stm_usart *) 0x40013800))
 382 #define stm_usart2 (*((struct stm_usart *) 0x40004400))
 383
 384 struct stm_tim {
 385 };
 386
 387 extern struct stm_tim stm_tim9;
 388
 389 struct stm_tim1011 {
 390         vuint32_t       cr1;
 391         uint32_t        unused_4;
 392         vuint32_t       smcr;
 393         vuint32_t       dier;
 394         vuint32_t       sr;
 395         vuint32_t       egr;
 396         vuint32_t       ccmr1;
 397         uint32_t        unused_1c;
 398         vuint32_t       ccer;
 399         vuint32_t       cnt;
 400         vuint32_t       psc;
 401         vuint32_t       arr;
 402         uint32_t        unused_30;
 403         vuint32_t       ccr1;
 404         uint32_t        unused_38;
 405         uint32_t        unused_3c;
 406         uint32_t        unused_40;
 407         uint32_t        unused_44;
 408         uint32_t        unused_48;
 409         uint32_t        unused_4c;
 410         vuint32_t       or;
 411 };
 412
 413 extern struct stm_tim1011 stm_tim10;
 414 extern struct stm_tim1011 stm_tim11;
 415
 416 #define STM_TIM1011_CR1_CKD     8
 417 #define  STM_TIM1011_CR1_CKD_1          0
 418 #define  STM_TIM1011_CR1_CKD_2          1
 419 #define  STM_TIM1011_CR1_CKD_4          2
 420 #define  STM_TIM1011_CR1_CKD_MASK       3
 421 #define STM_TIM1011_CR1_ARPE    7
 422 #define STM_TIM1011_CR1_URS     2
 423 #define STM_TIM1011_CR1_UDIS    1
 424 #define STM_TIM1011_CR1_CEN     0
 425
 426 #define STM_TIM1011_SMCR_ETP    15
 427 #define STM_TIM1011_SMCR_ECE    14
 428 #define STM_TIM1011_SMCR_ETPS   12
 429 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 430 #define  STM_TIM1011_SMCR_ETPS_2        1
 431 #define  STM_TIM1011_SMCR_ETPS_4        2
 432 #define  STM_TIM1011_SMCR_ETPS_8        3
 433 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 434 #define STM_TIM1011_SMCR_ETF    8
 435 #define  STM_TIM1011_SMCR_ETF_NONE              0
 436 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 437 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 438 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 439 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 440 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 441 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 442 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 443 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 444 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 445 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 446 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 447 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 448 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 449 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 450 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 451 #define  STM_TIM1011_SMCR_ETF_MASK              15
 452
 453 #define STM_TIM1011_DIER_CC1E   1
 454 #define STM_TIM1011_DIER_UIE    0
 455
 456 #define STM_TIM1011_SR_CC1OF    9
 457 #define STM_TIM1011_SR_CC1IF    1
 458 #define STM_TIM1011_SR_UIF      0
 459
 460 #define STM_TIM1011_EGR_CC1G    1
 461 #define STM_TIM1011_EGR_UG      0
 462
 463 #define STM_TIM1011_CCMR1_OC1CE 7
 464 #define STM_TIM1011_CCMR1_OC1M  4
 465 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 466 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 467 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 468 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 469 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 470 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 471 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 472 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 473 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 474 #define STM_TIM1011_CCMR1_OC1PE 3
 475 #define STM_TIM1011_CCMR1_OC1FE 2
 476 #define STM_TIM1011_CCMR1_CC1S  0
 477 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 478 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 479 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 480 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 481 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 482
 483 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 484 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 485 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 486 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 487 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 488 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 489 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 490 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 491 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 492 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 493 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 494 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 495 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 496 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 497 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 498 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 499 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 500 #define STM_TIM1011_CCMR1_IC1PSC        2
 501 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 502 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 503 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 504 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 505 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 506 #define STM_TIM1011_CCMR1_CC1S          0
 507
 508 #define STM_TIM1011_CCER_CC1NP          3
 509 #define STM_TIM1011_CCER_CC1P           1
 510 #define STM_TIM1011_CCER_CC1E           0
 511
 512 #define STM_TIM1011_OR_TI1_RMP_RI       3
 513 #define STM_TIM1011_ETR_RMP             2
 514 #define STM_TIM1011_TI1_RMP             0
 515 #define  STM_TIM1011_TI1_RMP_GPIO               0
 516 #define  STM_TIM1011_TI1_RMP_LSI                1
 517 #define  STM_TIM1011_TI1_RMP_LSE                2
 518 #define  STM_TIM1011_TI1_RMP_RTC                3
 519 #define  STM_TIM1011_TI1_RMP_MASK               3
 520
 521 /* Flash interface */
 522
 523 struct stm_flash {
 524         vuint32_t       acr;
 525         vuint32_t       pecr;
 526         vuint32_t       pdkeyr;
 527         vuint32_t       pekeyr;
 528
 529         vuint32_t       prgkeyr;
 530         vuint32_t       optkeyr;
 531         vuint32_t       sr;
 532         vuint32_t       obr;
 533
 534         vuint32_t       wrpr;
 535 };
 536
 537 extern struct stm_flash stm_flash;
 538
 539 #define STM_FLASH_ACR_RUN_PD    (4)
 540 #define STM_FLASH_ACR_SLEEP_PD  (3)
 541 #define STM_FLASH_ACR_ACC64     (2)
 542 #define STM_FLASH_ACR_PRFEN     (1)
 543 #define STM_FLASH_ACR_LATENCY   (0)
 544
 545 #define STM_FLASH_PECR_OBL_LAUNCH       18
 546 #define STM_FLASH_PECR_ERRIE            17
 547 #define STM_FLASH_PECR_EOPIE            16
 548 #define STM_FLASH_PECR_FPRG             10
 549 #define STM_FLASH_PECR_ERASE            9
 550 #define STM_FLASH_PECR_FTDW             8
 551 #define STM_FLASH_PECR_DATA             4
 552 #define STM_FLASH_PECR_PROG             3
 553 #define STM_FLASH_PECR_OPTLOCK          2
 554 #define STM_FLASH_PECR_PRGLOCK          1
 555 #define STM_FLASH_PECR_PELOCK           0
 556
 557 #define STM_FLASH_SR_OPTVERR            11
 558 #define STM_FLASH_SR_SIZERR             10
 559 #define STM_FLASH_SR_PGAERR             9
 560 #define STM_FLASH_SR_WRPERR             8
 561 #define STM_FLASH_SR_READY              3
 562 #define STM_FLASH_SR_ENDHV              2
 563 #define STM_FLASH_SR_EOP                1
 564 #define STM_FLASH_SR_BSY                0
 565
 566 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 567 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 568
 569 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
 570 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
 571
 572 struct stm_rcc {
 573         vuint32_t       cr;
 574         vuint32_t       icscr;
 575         uint32_t        unused08;
 576         vuint32_t       cfgr;
 577
 578         vuint32_t       cier;
 579         vuint32_t       cifr;
 580         vuint32_t       cicr;
 581         vuint32_t       iopstr;
 582
 583         vuint32_t       ahbrstr;
 584         vuint32_t       apb2rstr;
 585         vuint32_t       apb1rstr;
 586         vuint32_t       iopenr;
 587
 588         vuint32_t       ahbenr;
 589         vuint32_t       apb2enr;
 590         vuint32_t       apb1enr;
 591         vuint32_t       iopsmen;
 592
 593         vuint32_t       ahbsmenr;
 594         vuint32_t       apb2smenr;
 595         vuint32_t       apb1smenr;
 596         vuint32_t       ccipr;
 597
 598         vuint32_t       csr;
 599 };
 600
 601 extern struct stm_rcc stm_rcc;
 602
 603 /* Nominal high speed internal oscillator frequency is 16MHz */
 604 #define STM_HSI_FREQ            16000000
 605 #define STM_MSI_FREQ             2097000
 606
 607 #define STM_RCC_CR_RTCPRE       (29)
 608 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 609 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 610 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 611 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 612 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 613
 614 #define STM_RCC_CR_CSSON        (28)
 615 #define STM_RCC_CR_PLLRDY       (25)
 616 #define STM_RCC_CR_PLLON        (24)
 617 #define STM_RCC_CR_HSEBYP       (18)
 618 #define STM_RCC_CR_HSERDY       (17)
 619 #define STM_RCC_CR_HSEON        (16)
 620 #define STM_RCC_CR_MSIRDY       (9)
 621 #define STM_RCC_CR_MSION        (8)
 622 #define STM_RCC_CR_HSIRDY       (1)
 623 #define STM_RCC_CR_HSION        (0)
 624
 625 #define STM_RCC_CFGR_MCOPRE     (28)
 626 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 627 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 628 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 629 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 630 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 631 #define  STM_RCC_CFGR_MCOPRE_MASK       7
 632
 633 #define STM_RCC_CFGR_MCOSEL     (24)
 634 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 635 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 636 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 637 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 638 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 639 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 640 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 641 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 642 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 643
 644 #define STM_RCC_CFGR_PLLDIV     (22)
 645 #define  STM_RCC_CFGR_PLLDIV_2          1
 646 #define  STM_RCC_CFGR_PLLDIV_3          2
 647 #define  STM_RCC_CFGR_PLLDIV_4          3
 648 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 649
 650 #define STM_RCC_CFGR_PLLMUL     (18)
 651 #define  STM_RCC_CFGR_PLLMUL_3          0
 652 #define  STM_RCC_CFGR_PLLMUL_4          1
 653 #define  STM_RCC_CFGR_PLLMUL_6          2
 654 #define  STM_RCC_CFGR_PLLMUL_8          3
 655 #define  STM_RCC_CFGR_PLLMUL_12         4
 656 #define  STM_RCC_CFGR_PLLMUL_16         5
 657 #define  STM_RCC_CFGR_PLLMUL_24         6
 658 #define  STM_RCC_CFGR_PLLMUL_32         7
 659 #define  STM_RCC_CFGR_PLLMUL_48         8
 660 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 661
 662 #define STM_RCC_CFGR_PLLSRC     (16)
 663
 664 #define STM_RCC_CFGR_PPRE2      (11)
 665 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 666 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 667 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 668 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 669 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 670 #define  STM_RCC_CFGR_PPRE2_MASK        7
 671
 672 #define STM_RCC_CFGR_PPRE1      (8)
 673 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 674 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 675 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 676 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 677 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 678 #define  STM_RCC_CFGR_PPRE1_MASK        7
 679
 680 #define STM_RCC_CFGR_HPRE       (4)
 681 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 682 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 683 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 684 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 685 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 686 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 687 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 688 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 689 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 690 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 691
 692 #define STM_RCC_CFGR_SWS        (2)
 693 #define  STM_RCC_CFGR_SWS_MSI           0
 694 #define  STM_RCC_CFGR_SWS_HSI           1
 695 #define  STM_RCC_CFGR_SWS_HSE           2
 696 #define  STM_RCC_CFGR_SWS_PLL           3
 697 #define  STM_RCC_CFGR_SWS_MASK          3
 698
 699 #define STM_RCC_CFGR_SW         (0)
 700 #define  STM_RCC_CFGR_SW_MSI            0
 701 #define  STM_RCC_CFGR_SW_HSI            1
 702 #define  STM_RCC_CFGR_SW_HSE            2
 703 #define  STM_RCC_CFGR_SW_PLL            3
 704 #define  STM_RCC_CFGR_SW_MASK           3
 705
 706 #define STM_RCC_IOPENR_IOPAEN           0
 707 #define STM_RCC_IOPENR_IOPBEN           1
 708 #define STM_RCC_IOPENR_IOPCEN           2
 709 #define STM_RCC_IOPENR_IOPDEN           3
 710 #define STM_RCC_IOPENR_IOPEEN           4
 711 #define STM_RCC_IOPENR_IOPHEN           7
 712
 713 #define STM_RCC_AHBENR_DMA1EN           0
 714 #define STM_RCC_AHBENR_MIFEN            8
 715 #define STM_RCC_AHBENR_CRCEN            12
 716 #define STM_RCC_AHBENR_CRYPEN           24
 717
 718 #define STM_RCC_APB2ENR_DBGEN           (22)
 719 #define STM_RCC_APB2ENR_USART1EN        (14)
 720 #define STM_RCC_APB2ENR_SPI1EN          (12)
 721 #define STM_RCC_APB2ENR_ADC1EN          (9)
 722 #define STM_RCC_APB2ENR_FWEN            (7)
 723 #define STM_RCC_APB2ENR_TIM22EN         (5)
 724 #define STM_RCC_APB2ENR_TIM21EN         (2)
 725 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 726
 727 #define STM_RCC_APB1ENR_LPTIM1EN        31
 728 #define STM_RCC_APB1ENR_I2C3EN          30
 729 #define STM_RCC_APB1ENR_PWREN           28
 730 #define STM_RCC_APB1ENR_I2C2EN          22
 731 #define STM_RCC_APB1ENR_I2C1EN          21
 732 #define STM_RCC_APB1ENR_USART5EN        20
 733 #define STM_RCC_APB1ENR_USART4EN        19
 734 #define STM_RCC_APB1ENR_LPUART1EN       18
 735 #define STM_RCC_APB1ENR_USART2EN        17
 736 #define STM_RCC_APB1ENR_SPI2EN          14
 737 #define STM_RCC_APB1ENR_WWDGEN          11
 738 #define STM_RCC_APB1ENR_TIM7EN          5
 739 #define STM_RCC_APB1ENR_TIM6EN          4
 740 #define STM_RCC_APB1ENR_TIM3EN          1
 741 #define STM_RCC_APB1ENR_TIM2EN          0
 742
 743 #define STM_RCC_CSR_LPWRRSTF            (31)
 744 #define STM_RCC_CSR_WWDGRSTF            (30)
 745 #define STM_RCC_CSR_IWDGRSTF            (29)
 746 #define STM_RCC_CSR_SFTRSTF             (28)
 747 #define STM_RCC_CSR_PORRSTF             (27)
 748 #define STM_RCC_CSR_PINRSTF             (26)
 749 #define STM_RCC_CSR_OBLRSTF             (25)
 750 #define STM_RCC_CSR_RMVF                (24)
 751 #define STM_RCC_CSR_RTFRST              (23)
 752 #define STM_RCC_CSR_RTCEN               (22)
 753 #define STM_RCC_CSR_RTCSEL              (16)
 754
 755 #define  STM_RCC_CSR_RTCSEL_NONE                0
 756 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 757 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 758 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 759 #define  STM_RCC_CSR_RTCSEL_MASK                3
 760
 761 #define STM_RCC_CSR_LSEBYP              (10)
 762 #define STM_RCC_CSR_LSERDY              (9)
 763 #define STM_RCC_CSR_LSEON               (8)
 764 #define STM_RCC_CSR_LSIRDY              (1)
 765 #define STM_RCC_CSR_LSION               (0)
 766
 767 struct stm_pwr {
 768         vuint32_t       cr;
 769         vuint32_t       csr;
 770 };
 771
 772 extern struct stm_pwr stm_pwr;
 773
 774 #define STM_PWR_CR_LPRUN        (14)
 775
 776 #define STM_PWR_CR_VOS          (11)
 777 #define  STM_PWR_CR_VOS_1_8             1
 778 #define  STM_PWR_CR_VOS_1_5             2
 779 #define  STM_PWR_CR_VOS_1_2             3
 780 #define  STM_PWR_CR_VOS_MASK            3
 781
 782 #define STM_PWR_CR_FWU          (10)
 783 #define STM_PWR_CR_ULP          (9)
 784 #define STM_PWR_CR_DBP          (8)
 785
 786 #define STM_PWR_CR_PLS          (5)
 787 #define  STM_PWR_CR_PLS_1_9     0
 788 #define  STM_PWR_CR_PLS_2_1     1
 789 #define  STM_PWR_CR_PLS_2_3     2
 790 #define  STM_PWR_CR_PLS_2_5     3
 791 #define  STM_PWR_CR_PLS_2_7     4
 792 #define  STM_PWR_CR_PLS_2_9     5
 793 #define  STM_PWR_CR_PLS_3_1     6
 794 #define  STM_PWR_CR_PLS_EXT     7
 795 #define  STM_PWR_CR_PLS_MASK    7
 796
 797 #define STM_PWR_CR_PVDE         (4)
 798 #define STM_PWR_CR_CSBF         (3)
 799 #define STM_PWR_CR_CWUF         (2)
 800 #define STM_PWR_CR_PDDS         (1)
 801 #define STM_PWR_CR_LPSDSR       (0)
 802
 803 #define STM_PWR_CSR_EWUP3       (10)
 804 #define STM_PWR_CSR_EWUP2       (9)
 805 #define STM_PWR_CSR_EWUP1       (8)
 806 #define STM_PWR_CSR_REGLPF      (5)
 807 #define STM_PWR_CSR_VOSF        (4)
 808 #define STM_PWR_CSR_VREFINTRDYF (3)
 809 #define STM_PWR_CSR_PVDO        (2)
 810 #define STM_PWR_CSR_SBF         (1)
 811 #define STM_PWR_CSR_WUF         (0)
 812
 813 struct stm_tim67 {
 814         vuint32_t       cr1;
 815         vuint32_t       cr2;
 816         uint32_t        _unused_08;
 817         vuint32_t       dier;
 818
 819         vuint32_t       sr;
 820         vuint32_t       egr;
 821         uint32_t        _unused_18;
 822         uint32_t        _unused_1c;
 823
 824         uint32_t        _unused_20;
 825         vuint32_t       cnt;
 826         vuint32_t       psc;
 827         vuint32_t       arr;
 828 };
 829
 830 extern struct stm_tim67 stm_tim6;
 831
 832 #define STM_TIM67_CR1_ARPE      (7)
 833 #define STM_TIM67_CR1_OPM       (3)
 834 #define STM_TIM67_CR1_URS       (2)
 835 #define STM_TIM67_CR1_UDIS      (1)
 836 #define STM_TIM67_CR1_CEN       (0)
 837
 838 #define STM_TIM67_CR2_MMS       (4)
 839 #define  STM_TIM67_CR2_MMS_RESET        0
 840 #define  STM_TIM67_CR2_MMS_ENABLE       1
 841 #define  STM_TIM67_CR2_MMS_UPDATE       2
 842 #define  STM_TIM67_CR2_MMS_MASK         7
 843
 844 #define STM_TIM67_DIER_UDE      (8)
 845 #define STM_TIM67_DIER_UIE      (0)
 846
 847 #define STM_TIM67_SR_UIF        (0)
 848
 849 #define STM_TIM67_EGR_UG        (0)
 850
 851 struct stm_lcd {
 852         vuint32_t       cr;
 853         vuint32_t       fcr;
 854         vuint32_t       sr;
 855         vuint32_t       clr;
 856         uint32_t        unused_0x10;
 857         vuint32_t       ram[8*2];
 858 };
 859
 860 extern struct stm_lcd stm_lcd;
 861
 862 #define STM_LCD_CR_MUX_SEG              (7)
 863
 864 #define STM_LCD_CR_BIAS                 (5)
 865 #define  STM_LCD_CR_BIAS_1_4            0
 866 #define  STM_LCD_CR_BIAS_1_2            1
 867 #define  STM_LCD_CR_BIAS_1_3            2
 868 #define  STM_LCD_CR_BIAS_MASK           3
 869
 870 #define STM_LCD_CR_DUTY                 (2)
 871 #define  STM_LCD_CR_DUTY_STATIC         0
 872 #define  STM_LCD_CR_DUTY_1_2            1
 873 #define  STM_LCD_CR_DUTY_1_3            2
 874 #define  STM_LCD_CR_DUTY_1_4            3
 875 #define  STM_LCD_CR_DUTY_1_8            4
 876 #define  STM_LCD_CR_DUTY_MASK           7
 877
 878 #define STM_LCD_CR_VSEL                 (1)
 879 #define STM_LCD_CR_LCDEN                (0)
 880
 881 #define STM_LCD_FCR_PS                  (22)
 882 #define  STM_LCD_FCR_PS_1               0x0
 883 #define  STM_LCD_FCR_PS_2               0x1
 884 #define  STM_LCD_FCR_PS_4               0x2
 885 #define  STM_LCD_FCR_PS_8               0x3
 886 #define  STM_LCD_FCR_PS_16              0x4
 887 #define  STM_LCD_FCR_PS_32              0x5
 888 #define  STM_LCD_FCR_PS_64              0x6
 889 #define  STM_LCD_FCR_PS_128             0x7
 890 #define  STM_LCD_FCR_PS_256             0x8
 891 #define  STM_LCD_FCR_PS_512             0x9
 892 #define  STM_LCD_FCR_PS_1024            0xa
 893 #define  STM_LCD_FCR_PS_2048            0xb
 894 #define  STM_LCD_FCR_PS_4096            0xc
 895 #define  STM_LCD_FCR_PS_8192            0xd
 896 #define  STM_LCD_FCR_PS_16384           0xe
 897 #define  STM_LCD_FCR_PS_32768           0xf
 898 #define  STM_LCD_FCR_PS_MASK            0xf
 899
 900 #define STM_LCD_FCR_DIV                 (18)
 901 #define STM_LCD_FCR_DIV_16              0x0
 902 #define STM_LCD_FCR_DIV_17              0x1
 903 #define STM_LCD_FCR_DIV_18              0x2
 904 #define STM_LCD_FCR_DIV_19              0x3
 905 #define STM_LCD_FCR_DIV_20              0x4
 906 #define STM_LCD_FCR_DIV_21              0x5
 907 #define STM_LCD_FCR_DIV_22              0x6
 908 #define STM_LCD_FCR_DIV_23              0x7
 909 #define STM_LCD_FCR_DIV_24              0x8
 910 #define STM_LCD_FCR_DIV_25              0x9
 911 #define STM_LCD_FCR_DIV_26              0xa
 912 #define STM_LCD_FCR_DIV_27              0xb
 913 #define STM_LCD_FCR_DIV_28              0xc
 914 #define STM_LCD_FCR_DIV_29              0xd
 915 #define STM_LCD_FCR_DIV_30              0xe
 916 #define STM_LCD_FCR_DIV_31              0xf
 917 #define STM_LCD_FCR_DIV_MASK            0xf
 918
 919 #define STM_LCD_FCR_BLINK               (16)
 920 #define  STM_LCD_FCR_BLINK_DISABLE              0
 921 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 922 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 923 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 924 #define  STM_LCD_FCR_BLINK_MASK                 3
 925
 926 #define STM_LCD_FCR_BLINKF              (13)
 927 #define  STM_LCD_FCR_BLINKF_8                   0
 928 #define  STM_LCD_FCR_BLINKF_16                  1
 929 #define  STM_LCD_FCR_BLINKF_32                  2
 930 #define  STM_LCD_FCR_BLINKF_64                  3
 931 #define  STM_LCD_FCR_BLINKF_128                 4
 932 #define  STM_LCD_FCR_BLINKF_256                 5
 933 #define  STM_LCD_FCR_BLINKF_512                 6
 934 #define  STM_LCD_FCR_BLINKF_1024                7
 935 #define  STM_LCD_FCR_BLINKF_MASK                7
 936
 937 #define STM_LCD_FCR_CC                  (10)
 938 #define  STM_LCD_FCR_CC_MASK                    7
 939
 940 #define STM_LCD_FCR_DEAD                (7)
 941 #define  STM_LCD_FCR_DEAD_MASK                  7
 942
 943 #define STM_LCD_FCR_PON                 (4)
 944 #define  STM_LCD_FCR_PON_MASK                   7
 945
 946 #define STM_LCD_FCR_UDDIE               (3)
 947 #define STM_LCD_FCR_SOFIE               (1)
 948 #define STM_LCD_FCR_HD                  (0)
 949
 950 #define STM_LCD_SR_FCRSF                (5)
 951 #define STM_LCD_SR_RDY                  (4)
 952 #define STM_LCD_SR_UDD                  (3)
 953 #define STM_LCD_SR_UDR                  (2)
 954 #define STM_LCD_SR_SOF                  (1)
 955 #define STM_LCD_SR_ENS                  (0)
 956
 957 #define STM_LCD_CLR_UDDC                (3)
 958 #define STM_LCD_CLR_SOFC                (1)
 959
 960 /* The SYSTICK starts at 0xe000e010 */
 961
 962 struct stm_systick {
 963         vuint32_t       csr;
 964         vuint32_t       rvr;
 965         vuint32_t       cvr;
 966         vuint32_t       calib;
 967 };
 968
 969 extern struct stm_systick stm_systick;
 970
 971 #define STM_SYSTICK_CSR_ENABLE          0
 972 #define STM_SYSTICK_CSR_TICKINT         1
 973 #define STM_SYSTICK_CSR_CLKSOURCE       2
 974 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 975 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 976 #define STM_SYSTICK_CSR_COUNTFLAG       16
 977
 978 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 979
 980 struct stm_nvic {
 981         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 982
 983         uint8_t         _unused020[0x080 - 0x004];
 984
 985         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 986
 987         uint8_t         _unused0a0[0x100 - 0x084];
 988
 989         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 990
 991         uint8_t         _unused120[0x180 - 0x104];
 992
 993         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 994
 995         uint8_t         _unused1a0[0x300 - 0x184];
 996
 997         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 998 };
 999
1000 extern struct stm_nvic stm_nvic;
1001
1002 #define IRQ_MASK(irq)   (1 << (irq))
1003 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
1004
1005 static inline void
1006 stm_nvic_set_enable(int irq) {
1007         stm_nvic.iser = IRQ_MASK(irq);
1008 }
1009
1010 static inline void
1011 stm_nvic_clear_enable(int irq) {
1012         stm_nvic.icer = IRQ_MASK(irq);
1013 }
1014
1015 static inline int
1016 stm_nvic_enabled(int irq) {
1017         return IRQ_BOOL(stm_nvic.iser, irq);
1018 }
1019
1020 static inline void
1021 stm_nvic_set_pending(int irq) {
1022         stm_nvic.ispr = IRQ_MASK(irq);
1023 }
1024
1025 static inline void
1026 stm_nvic_clear_pending(int irq) {
1027         stm_nvic.icpr = IRQ_MASK(irq);
1028 }
1029
1030 static inline int
1031 stm_nvic_pending(int irq) {
1032         return IRQ_BOOL(stm_nvic.ispr, irq);
1033 }
1034
1035 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
1036 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
1037 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
1038
1039 static inline void
1040 stm_nvic_set_priority(int irq, uint8_t prio) {
1041         int             n = IRQ_PRIO_REG(irq);
1042         uint32_t        v;
1043
1044         v = stm_nvic.ipr[n];
1045         v &= ~IRQ_PRIO_MASK(irq);
1046         v |= (prio) << IRQ_PRIO_BIT(irq);
1047         stm_nvic.ipr[n] = v;
1048 }
1049
1050 static inline uint8_t
1051 stm_nvic_get_priority(int irq) {
1052         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1053 }
1054
1055 struct stm_scb {
1056         vuint32_t       cpuid;
1057         vuint32_t       icsr;
1058         vuint32_t       vtor;
1059         vuint32_t       aircr;
1060
1061         vuint32_t       scr;
1062         vuint32_t       ccr;
1063         vuint32_t       shpr1;
1064         vuint32_t       shpr2;
1065
1066         vuint32_t       shpr3;
1067         vuint32_t       shcrs;
1068         vuint32_t       cfsr;
1069         vuint32_t       hfsr;
1070
1071         uint32_t        unused_30;
1072         vuint32_t       mmfar;
1073         vuint32_t       bfar;
1074 };
1075
1076 extern struct stm_scb stm_scb;
1077
1078 #define STM_SCB_AIRCR_VECTKEY           16
1079 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
1080 #define STM_SCB_AIRCR_PRIGROUP          8
1081 #define STM_SCB_AIRCR_SYSRESETREQ       2
1082 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
1083 #define STM_SCB_AIRCR_VECTRESET         0
1084
1085 struct stm_mpu {
1086         vuint32_t       typer;
1087         vuint32_t       cr;
1088         vuint32_t       rnr;
1089         vuint32_t       rbar;
1090
1091         vuint32_t       rasr;
1092         vuint32_t       rbar_a1;
1093         vuint32_t       rasr_a1;
1094         vuint32_t       rbar_a2;
1095         vuint32_t       rasr_a2;
1096         vuint32_t       rbar_a3;
1097         vuint32_t       rasr_a3;
1098 };
1099
1100 extern struct stm_mpu stm_mpu;
1101
1102 #define STM_MPU_TYPER_IREGION   16
1103 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1104 #define STM_MPU_TYPER_DREGION   8
1105 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1106 #define STM_MPU_TYPER_SEPARATE  0
1107
1108 #define STM_MPU_CR_PRIVDEFENA   2
1109 #define STM_MPU_CR_HFNMIENA     1
1110 #define STM_MPU_CR_ENABLE       0
1111
1112 #define STM_MPU_RNR_REGION      0
1113 #define STM_MPU_RNR_REGION_MASK         0xff
1114
1115 #define STM_MPU_RBAR_ADDR       5
1116 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1117
1118 #define STM_MPU_RBAR_VALID      4
1119 #define STM_MPU_RBAR_REGION     0
1120 #define STM_MPU_RBAR_REGION_MASK        0xf
1121
1122 #define STM_MPU_RASR_XN         28
1123 #define STM_MPU_RASR_AP         24
1124 #define  STM_MPU_RASR_AP_NONE_NONE      0
1125 #define  STM_MPU_RASR_AP_RW_NONE        1
1126 #define  STM_MPU_RASR_AP_RW_RO          2
1127 #define  STM_MPU_RASR_AP_RW_RW          3
1128 #define  STM_MPU_RASR_AP_RO_NONE        5
1129 #define  STM_MPU_RASR_AP_RO_RO          6
1130 #define  STM_MPU_RASR_AP_MASK           7
1131 #define STM_MPU_RASR_TEX        19
1132 #define  STM_MPU_RASR_TEX_MASK          7
1133 #define STM_MPU_RASR_S          18
1134 #define STM_MPU_RASR_C          17
1135 #define STM_MPU_RASR_B          16
1136 #define STM_MPU_RASR_SRD        8
1137 #define  STM_MPU_RASR_SRD_MASK          0xff
1138 #define STM_MPU_RASR_SIZE       1
1139 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1140 #define STM_MPU_RASR_ENABLE     0
1141
1142 #define isr_decl(name) void stm_ ## name ## _isr(void)
1143
1144 isr_decl(halt);
1145 isr_decl(ignore);
1146
1147 isr_decl(nmi);
1148 isr_decl(hardfault);
1149 isr_decl(usagefault);
1150 isr_decl(svc);
1151 isr_decl(debugmon);
1152 isr_decl(pendsv);
1153 isr_decl(systick);
1154 isr_decl(wwdg);
1155 isr_decl(pvd);
1156 isr_decl(rtc);
1157 isr_decl(flash);
1158 isr_decl(rcc_crs);
1159 isr_decl(exti1_0);
1160 isr_decl(exti3_2);
1161 isr_decl(exti15_4);
1162 isr_decl(dma1_channel1);
1163 isr_decl(dma1_channel3_2);
1164 isr_decl(dma1_channel7_4);
1165 isr_decl(adc_comp);
1166 isr_decl(lptim1);
1167 isr_decl(usart4_usart5);
1168 isr_decl(tim2);
1169 isr_decl(tim3);
1170 isr_decl(tim4);
1171 isr_decl(tim6);
1172 isr_decl(tim7);
1173 isr_decl(tim21);
1174 isr_decl(i2c3);
1175 isr_decl(tim22);
1176 isr_decl(i2c1);
1177 isr_decl(i2c2);
1178 isr_decl(spi1);
1179 isr_decl(spi2);
1180 isr_decl(usart1);
1181 isr_decl(usart2);
1182 isr_decl(usart3);
1183 isr_decl(lpuart1_aes);
1184
1185 #undef isr_decl
1186
1187 #define STM_ISR_WWDG_POS                0
1188 #define STM_ISR_PVD_POS                 1
1189 #define STM_ISR_RTC_POS                 2
1190 #define STM_ISR_FLASH_POS               3
1191 #define STM_ISR_RCC_CRS_POS             4
1192 #define STM_ISR_EXTI1_0_POS             5
1193 #define STM_ISR_EXTI3_2_POS             6
1194 #define STM_ISR_EXTI15_4_POS            7
1195 #define STM_ISR_DMA1_CHANNEL1_POS       9
1196 #define STM_ISR_DMA1_CHANNEL3_2_POS     10
1197 #define STM_ISR_DMA1_CHANNEL7_4_POS     11
1198 #define STM_ISR_ADC_COMP_POS            12
1199 #define STM_ISR_LPTIM1_POS              13
1200 #define STM_ISR_USART4_USART5_POS       14
1201 #define STM_ISR_TIM2_POS                15
1202 #define STM_ISR_TIM3_POS                16
1203 #define STM_ISR_TIM6_POS                17
1204 #define STM_ISR_TIM7_POS                18
1205 #define STM_ISR_TIM21_POS               20
1206 #define STM_ISR_I2C3_POS                21
1207 #define STM_ISR_TIM22_POS               22
1208 #define STM_ISR_I2C1_POS                23
1209 #define STM_ISR_I2C2_POS                24
1210 #define STM_ISR_SPI1_POS                25
1211 #define STM_ISR_SPI2_POS                26
1212 #define STM_ISR_USART1_POS              27
1213 #define STM_ISR_USART2_POS              28
1214 #define STM_ISR_LPUART1_AES_POS         29
1215
1216 struct stm_syscfg {
1217         vuint32_t       memrmp;
1218         vuint32_t       pmc;
1219         vuint32_t       exticr[4];
1220 };
1221
1222 extern struct stm_syscfg stm_syscfg;
1223
1224 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1225 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1226 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1227 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1228 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1229
1230 #define STM_SYSCFG_PMC_USB_PU           0
1231
1232 #define STM_SYSCFG_EXTICR_PA            0
1233 #define STM_SYSCFG_EXTICR_PB            1
1234 #define STM_SYSCFG_EXTICR_PC            2
1235 #define STM_SYSCFG_EXTICR_PD            3
1236 #define STM_SYSCFG_EXTICR_PE            4
1237 #define STM_SYSCFG_EXTICR_PH            5
1238
1239 static inline void
1240 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1241         uint8_t reg = pin >> 2;
1242         uint8_t shift = (pin & 3) << 2;
1243         uint8_t val = 0;
1244
1245         /* Enable SYSCFG */
1246         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1247
1248         if (gpio == &stm_gpioa)
1249                 val = STM_SYSCFG_EXTICR_PA;
1250         else if (gpio == &stm_gpiob)
1251                 val = STM_SYSCFG_EXTICR_PB;
1252         else if (gpio == &stm_gpioc)
1253                 val = STM_SYSCFG_EXTICR_PC;
1254         else if (gpio == &stm_gpiod)
1255                 val = STM_SYSCFG_EXTICR_PD;
1256         else if (gpio == &stm_gpioe)
1257                 val = STM_SYSCFG_EXTICR_PE;
1258
1259         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1260 }
1261
1262 struct stm_dma_channel {
1263         vuint32_t       ccr;
1264         vuint32_t       cndtr;
1265         vvoid_t         cpar;
1266         vvoid_t         cmar;
1267         vuint32_t       reserved;
1268 };
1269
1270 #define STM_NUM_DMA     7
1271
1272 struct stm_dma {
1273         vuint32_t               isr;
1274         vuint32_t               ifcr;
1275         struct stm_dma_channel  channel[STM_NUM_DMA];
1276 };
1277
1278 extern struct stm_dma stm_dma;
1279
1280 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1281  */
1282
1283 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1284
1285 #define STM_DMA_ISR(index)              ((index) << 2)
1286 #define STM_DMA_ISR_MASK                        0xf
1287 #define STM_DMA_ISR_TEIF                        3
1288 #define STM_DMA_ISR_HTIF                        2
1289 #define STM_DMA_ISR_TCIF                        1
1290 #define STM_DMA_ISR_GIF                         0
1291
1292 #define STM_DMA_IFCR(index)             ((index) << 2)
1293 #define STM_DMA_IFCR_MASK                       0xf
1294 #define STM_DMA_IFCR_CTEIF                      3
1295 #define STM_DMA_IFCR_CHTIF                      2
1296 #define STM_DMA_IFCR_CTCIF                      1
1297 #define STM_DMA_IFCR_CGIF                       0
1298
1299 #define STM_DMA_CCR_MEM2MEM             (14)
1300
1301 #define STM_DMA_CCR_PL                  (12)
1302 #define  STM_DMA_CCR_PL_LOW                     (0)
1303 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1304 #define  STM_DMA_CCR_PL_HIGH                    (2)
1305 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1306 #define  STM_DMA_CCR_PL_MASK                    (3)
1307
1308 #define STM_DMA_CCR_MSIZE               (10)
1309 #define  STM_DMA_CCR_MSIZE_8                    (0)
1310 #define  STM_DMA_CCR_MSIZE_16                   (1)
1311 #define  STM_DMA_CCR_MSIZE_32                   (2)
1312 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1313
1314 #define STM_DMA_CCR_PSIZE               (8)
1315 #define  STM_DMA_CCR_PSIZE_8                    (0)
1316 #define  STM_DMA_CCR_PSIZE_16                   (1)
1317 #define  STM_DMA_CCR_PSIZE_32                   (2)
1318 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1319
1320 #define STM_DMA_CCR_MINC                (7)
1321 #define STM_DMA_CCR_PINC                (6)
1322 #define STM_DMA_CCR_CIRC                (5)
1323 #define STM_DMA_CCR_DIR                 (4)
1324 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1325 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1326 #define STM_DMA_CCR_TEIE                (3)
1327 #define STM_DMA_CCR_HTIE                (2)
1328 #define STM_DMA_CCR_TCIE                (1)
1329 #define STM_DMA_CCR_EN                  (0)
1330
1331 #define STM_DMA_CHANNEL_ADC1            1
1332 #define STM_DMA_CHANNEL_SPI1_RX         2
1333 #define STM_DMA_CHANNEL_SPI1_TX         3
1334 #define STM_DMA_CHANNEL_SPI2_RX         4
1335 #define STM_DMA_CHANNEL_SPI2_TX         5
1336 #define STM_DMA_CHANNEL_USART3_TX       2
1337 #define STM_DMA_CHANNEL_USART3_RX       3
1338 #define STM_DMA_CHANNEL_USART1_TX       4
1339 #define STM_DMA_CHANNEL_USART1_RX       5
1340 #define STM_DMA_CHANNEL_USART2_RX       6
1341 #define STM_DMA_CHANNEL_USART2_TX       7
1342 #define STM_DMA_CHANNEL_I2C2_TX         4
1343 #define STM_DMA_CHANNEL_I2C2_RX         5
1344 #define STM_DMA_CHANNEL_I2C1_TX         6
1345 #define STM_DMA_CHANNEL_I2C1_RX         7
1346 #define STM_DMA_CHANNEL_TIM2_CH3        1
1347 #define STM_DMA_CHANNEL_TIM2_UP         2
1348 #define STM_DMA_CHANNEL_TIM2_CH1        5
1349 #define STM_DMA_CHANNEL_TIM2_CH2        7
1350 #define STM_DMA_CHANNEL_TIM2_CH4        7
1351 #define STM_DMA_CHANNEL_TIM3_CH3        2
1352 #define STM_DMA_CHANNEL_TIM3_CH4        3
1353 #define STM_DMA_CHANNEL_TIM3_UP         3
1354 #define STM_DMA_CHANNEL_TIM3_CH1        6
1355 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1356 #define STM_DMA_CHANNEL_TIM4_CH1        1
1357 #define STM_DMA_CHANNEL_TIM4_CH2        4
1358 #define STM_DMA_CHANNEL_TIM4_CH3        5
1359 #define STM_DMA_CHANNEL_TIM4_UP         7
1360 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1361 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1362 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1363 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1364
1365 /*
1366  * Only spi channel 1 and 2 can use DMA
1367  */
1368 #define STM_NUM_SPI     2
1369
1370 struct stm_spi {
1371         vuint32_t       cr1;
1372         vuint32_t       cr2;
1373         vuint32_t       sr;
1374         vuint32_t       dr;
1375         vuint32_t       crcpr;
1376         vuint32_t       rxcrcr;
1377         vuint32_t       txcrcr;
1378 };
1379
1380 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1381
1382 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1383  */
1384
1385 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1386
1387 #define STM_SPI_CR1_BIDIMODE            15
1388 #define STM_SPI_CR1_BIDIOE              14
1389 #define STM_SPI_CR1_CRCEN               13
1390 #define STM_SPI_CR1_CRCNEXT             12
1391 #define STM_SPI_CR1_DFF                 11
1392 #define STM_SPI_CR1_RXONLY              10
1393 #define STM_SPI_CR1_SSM                 9
1394 #define STM_SPI_CR1_SSI                 8
1395 #define STM_SPI_CR1_LSBFIRST            7
1396 #define STM_SPI_CR1_SPE                 6
1397 #define STM_SPI_CR1_BR                  3
1398 #define  STM_SPI_CR1_BR_PCLK_2                  0
1399 #define  STM_SPI_CR1_BR_PCLK_4                  1
1400 #define  STM_SPI_CR1_BR_PCLK_8                  2
1401 #define  STM_SPI_CR1_BR_PCLK_16                 3
1402 #define  STM_SPI_CR1_BR_PCLK_32                 4
1403 #define  STM_SPI_CR1_BR_PCLK_64                 5
1404 #define  STM_SPI_CR1_BR_PCLK_128                6
1405 #define  STM_SPI_CR1_BR_PCLK_256                7
1406 #define  STM_SPI_CR1_BR_MASK                    7
1407
1408 #define STM_SPI_CR1_MSTR                2
1409 #define STM_SPI_CR1_CPOL                1
1410 #define STM_SPI_CR1_CPHA                0
1411
1412 #define STM_SPI_CR2_TXEIE       7
1413 #define STM_SPI_CR2_RXNEIE      6
1414 #define STM_SPI_CR2_ERRIE       5
1415 #define STM_SPI_CR2_SSOE        2
1416 #define STM_SPI_CR2_TXDMAEN     1
1417 #define STM_SPI_CR2_RXDMAEN     0
1418
1419 #define STM_SPI_SR_FRE          8
1420 #define STM_SPI_SR_BSY          7
1421 #define STM_SPI_SR_OVR          6
1422 #define STM_SPI_SR_MODF         5
1423 #define STM_SPI_SR_CRCERR       4
1424 #define STM_SPI_SR_UDR          3
1425 #define STM_SPI_SR_CHSIDE       2
1426 #define STM_SPI_SR_TXE          1
1427 #define STM_SPI_SR_RXNE         0
1428
1429 struct stm_adc {
1430         vuint32_t       sr;
1431         vuint32_t       cr1;
1432         vuint32_t       cr2;
1433         vuint32_t       smpr1;
1434         vuint32_t       smpr2;
1435         vuint32_t       smpr3;
1436         vuint32_t       jofr1;
1437         vuint32_t       jofr2;
1438         vuint32_t       jofr3;
1439         vuint32_t       jofr4;
1440         vuint32_t       htr;
1441         vuint32_t       ltr;
1442         vuint32_t       sqr1;
1443         vuint32_t       sqr2;
1444         vuint32_t       sqr3;
1445         vuint32_t       sqr4;
1446         vuint32_t       sqr5;
1447         vuint32_t       jsqr;
1448         vuint32_t       jdr1;
1449         vuint32_t       jdr2;
1450         vuint32_t       jdr3;
1451         vuint32_t       jdr4;
1452         vuint32_t       dr;
1453         uint8_t         reserved[0x300 - 0x5c];
1454         vuint32_t       csr;
1455         vuint32_t       ccr;
1456 };
1457
1458 extern struct stm_adc stm_adc;
1459
1460 #define STM_ADC_SQ_TEMP         16
1461 #define STM_ADC_SQ_V_REF        17
1462
1463 #define STM_ADC_SR_JCNR         9
1464 #define STM_ADC_SR_RCNR         8
1465 #define STM_ADC_SR_ADONS        6
1466 #define STM_ADC_SR_OVR          5
1467 #define STM_ADC_SR_STRT         4
1468 #define STM_ADC_SR_JSTRT        3
1469 #define STM_ADC_SR_JEOC         2
1470 #define STM_ADC_SR_EOC          1
1471 #define STM_ADC_SR_AWD          0
1472
1473 #define STM_ADC_CR1_OVRIE       26
1474 #define STM_ADC_CR1_RES         24
1475 #define  STM_ADC_CR1_RES_12             0
1476 #define  STM_ADC_CR1_RES_10             1
1477 #define  STM_ADC_CR1_RES_8              2
1478 #define  STM_ADC_CR1_RES_6              3
1479 #define  STM_ADC_CR1_RES_MASK           3
1480 #define STM_ADC_CR1_AWDEN       23
1481 #define STM_ADC_CR1_JAWDEN      22
1482 #define STM_ADC_CR1_PDI         17
1483 #define STM_ADC_CR1_PDD         16
1484 #define STM_ADC_CR1_DISCNUM     13
1485 #define  STM_ADC_CR1_DISCNUM_1          0
1486 #define  STM_ADC_CR1_DISCNUM_2          1
1487 #define  STM_ADC_CR1_DISCNUM_3          2
1488 #define  STM_ADC_CR1_DISCNUM_4          3
1489 #define  STM_ADC_CR1_DISCNUM_5          4
1490 #define  STM_ADC_CR1_DISCNUM_6          5
1491 #define  STM_ADC_CR1_DISCNUM_7          6
1492 #define  STM_ADC_CR1_DISCNUM_8          7
1493 #define  STM_ADC_CR1_DISCNUM_MASK       7
1494 #define STM_ADC_CR1_JDISCEN     12
1495 #define STM_ADC_CR1_DISCEN      11
1496 #define STM_ADC_CR1_JAUTO       10
1497 #define STM_ADC_CR1_AWDSGL      9
1498 #define STM_ADC_CR1_SCAN        8
1499 #define STM_ADC_CR1_JEOCIE      7
1500 #define STM_ADC_CR1_AWDIE       6
1501 #define STM_ADC_CR1_EOCIE       5
1502 #define STM_ADC_CR1_AWDCH       0
1503 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1504
1505 #define STM_ADC_CR2_SWSTART     30
1506 #define STM_ADC_CR2_EXTEN       28
1507 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1508 #define  STM_ADC_CR2_EXTEN_RISING       1
1509 #define  STM_ADC_CR2_EXTEN_FALLING      2
1510 #define  STM_ADC_CR2_EXTEN_BOTH         3
1511 #define  STM_ADC_CR2_EXTEN_MASK         3
1512 #define STM_ADC_CR2_EXTSEL      24
1513 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1514 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1515 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1516 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1517 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1518 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1519 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1520 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1521 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1522 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1523 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1524 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1525 #define  STM_ADC_CR2_EXTSEL_MASK        15
1526 #define STM_ADC_CR2_JWSTART     22
1527 #define STM_ADC_CR2_JEXTEN      20
1528 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1529 #define  STM_ADC_CR2_JEXTEN_RISING      1
1530 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1531 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1532 #define  STM_ADC_CR2_JEXTEN_MASK        3
1533 #define STM_ADC_CR2_JEXTSEL     16
1534 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1535 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1536 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1537 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1538 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1539 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1540 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1541 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1542 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1543 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1544 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1545 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1546 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1547 #define STM_ADC_CR2_ALIGN       11
1548 #define STM_ADC_CR2_EOCS        10
1549 #define STM_ADC_CR2_DDS         9
1550 #define STM_ADC_CR2_DMA         8
1551 #define STM_ADC_CR2_DELS        4
1552 #define  STM_ADC_CR2_DELS_NONE          0
1553 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1554 #define  STM_ADC_CR2_DELS_7             2
1555 #define  STM_ADC_CR2_DELS_15            3
1556 #define  STM_ADC_CR2_DELS_31            4
1557 #define  STM_ADC_CR2_DELS_63            5
1558 #define  STM_ADC_CR2_DELS_127           6
1559 #define  STM_ADC_CR2_DELS_255           7
1560 #define  STM_ADC_CR2_DELS_MASK          7
1561 #define STM_ADC_CR2_CONT        1
1562 #define STM_ADC_CR2_ADON        0
1563
1564 #define STM_ADC_CCR_TSVREFE     23
1565 #define STM_ADC_CCR_ADCPRE      16
1566 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1567 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1568 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1569 #define  STM_ADC_CCR_ADCPRE_MASK        3
1570
1571 struct stm_temp_cal {
1572         uint16_t        vref;
1573         uint16_t        ts_cal_cold;
1574         uint16_t        reserved;
1575         uint16_t        ts_cal_hot;
1576 };
1577
1578 extern struct stm_temp_cal      stm_temp_cal;
1579
1580 #define stm_temp_cal_cold       25
1581 #define stm_temp_cal_hot        110
1582
1583 struct stm_dbg_mcu {
1584         uint32_t        idcode;
1585 };
1586
1587 extern struct stm_dbg_mcu       stm_dbg_mcu;
1588
1589 static inline uint16_t
1590 stm_dev_id(void) {
1591         return stm_dbg_mcu.idcode & 0xfff;
1592 }
1593
1594 struct stm_flash_size {
1595         uint16_t        f_size;
1596 };
1597
1598 extern struct stm_flash_size    stm_flash_size_reg;
1599 #define stm_flash_size_reg      (*((struct stm_flash_size *) 0x1ff8007c))
1600
1601 /* Returns flash size in bytes */
1602 extern uint32_t
1603 stm_flash_size(void);
1604
1605 struct stm_unique_id {
1606         uint32_t        u_id0;
1607         uint32_t        u_id1;
1608         uint32_t        u_id2;
1609 };
1610
1611 extern struct stm_unique_id     stm_unique_id;
1612 #define stm_unique_id   (*((struct stm_unique_id) 0x1ff80050))
1613
1614 struct stm_device_id {
1615         uint32_t        device_id;
1616 };
1617
1618 extern struct stm_device_id     stm_device_id;
1619 #define stm_device_id   (*((struct stm_device_id) 0x40015800))
1620
1621 #define STM_NUM_I2C     2
1622
1623 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1624
1625 struct stm_i2c {
1626         vuint32_t       cr1;
1627         vuint32_t       cr2;
1628         vuint32_t       oar1;
1629         vuint32_t       oar2;
1630         vuint32_t       dr;
1631         vuint32_t       sr1;
1632         vuint32_t       sr2;
1633         vuint32_t       ccr;
1634         vuint32_t       trise;
1635 };
1636
1637 extern struct stm_i2c stm_i2c1, stm_i2c2;
1638
1639 #define STM_I2C_CR1_SWRST       15
1640 #define STM_I2C_CR1_ALERT       13
1641 #define STM_I2C_CR1_PEC         12
1642 #define STM_I2C_CR1_POS         11
1643 #define STM_I2C_CR1_ACK         10
1644 #define STM_I2C_CR1_STOP        9
1645 #define STM_I2C_CR1_START       8
1646 #define STM_I2C_CR1_NOSTRETCH   7
1647 #define STM_I2C_CR1_ENGC        6
1648 #define STM_I2C_CR1_ENPEC       5
1649 #define STM_I2C_CR1_ENARP       4
1650 #define STM_I2C_CR1_SMBTYPE     3
1651 #define STM_I2C_CR1_SMBUS       1
1652 #define STM_I2C_CR1_PE          0
1653
1654 #define STM_I2C_CR2_LAST        12
1655 #define STM_I2C_CR2_DMAEN       11
1656 #define STM_I2C_CR2_ITBUFEN     10
1657 #define STM_I2C_CR2_ITEVTEN     9
1658 #define STM_I2C_CR2_ITERREN     8
1659 #define STM_I2C_CR2_FREQ        0
1660 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1661 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1662 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1663 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1664 #define  STM_I2C_CR2_FREQ_24_MHZ        24
1665 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1666 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1667
1668 #define STM_I2C_SR1_SMBALERT    15
1669 #define STM_I2C_SR1_TIMEOUT     14
1670 #define STM_I2C_SR1_PECERR      12
1671 #define STM_I2C_SR1_OVR         11
1672 #define STM_I2C_SR1_AF          10
1673 #define STM_I2C_SR1_ARLO        9
1674 #define STM_I2C_SR1_BERR        8
1675 #define STM_I2C_SR1_TXE         7
1676 #define STM_I2C_SR1_RXNE        6
1677 #define STM_I2C_SR1_STOPF       4
1678 #define STM_I2C_SR1_ADD10       3
1679 #define STM_I2C_SR1_BTF         2
1680 #define STM_I2C_SR1_ADDR        1
1681 #define STM_I2C_SR1_SB          0
1682
1683 #define STM_I2C_SR2_PEC         8
1684 #define  STM_I2C_SR2_PEC_MASK   0xff00
1685 #define STM_I2C_SR2_DUALF       7
1686 #define STM_I2C_SR2_SMBHOST     6
1687 #define STM_I2C_SR2_SMBDEFAULT  5
1688 #define STM_I2C_SR2_GENCALL     4
1689 #define STM_I2C_SR2_TRA         2
1690 #define STM_I2C_SR2_BUSY        1
1691 #define STM_I2C_SR2_MSL         0
1692
1693 #define STM_I2C_CCR_FS          15
1694 #define STM_I2C_CCR_DUTY        14
1695 #define STM_I2C_CCR_CCR         0
1696 #define  STM_I2C_CCR_MASK       0x7ff
1697
1698 struct stm_tim234 {
1699         vuint32_t       cr1;
1700         vuint32_t       cr2;
1701         vuint32_t       smcr;
1702         vuint32_t       dier;
1703
1704         vuint32_t       sr;
1705         vuint32_t       egr;
1706         vuint32_t       ccmr1;
1707         vuint32_t       ccmr2;
1708
1709         vuint32_t       ccer;
1710         vuint32_t       cnt;
1711         vuint32_t       psc;
1712         vuint32_t       arr;
1713
1714         uint32_t        reserved_30;
1715         vuint32_t       ccr1;
1716         vuint32_t       ccr2;
1717         vuint32_t       ccr3;
1718
1719         vuint32_t       ccr4;
1720         uint32_t        reserved_44;
1721         vuint32_t       dcr;
1722         vuint32_t       dmar;
1723
1724         uint32_t        reserved_50;
1725 };
1726
1727 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1728
1729 #define STM_TIM234_CR1_CKD      8
1730 #define  STM_TIM234_CR1_CKD_1           0
1731 #define  STM_TIM234_CR1_CKD_2           1
1732 #define  STM_TIM234_CR1_CKD_4           2
1733 #define  STM_TIM234_CR1_CKD_MASK        3
1734 #define STM_TIM234_CR1_ARPE     7
1735 #define STM_TIM234_CR1_CMS      5
1736 #define  STM_TIM234_CR1_CMS_EDGE        0
1737 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1738 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1739 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1740 #define  STM_TIM234_CR1_CMS_MASK        3
1741 #define STM_TIM234_CR1_DIR      4
1742 #define  STM_TIM234_CR1_DIR_UP          0
1743 #define  STM_TIM234_CR1_DIR_DOWN        1
1744 #define STM_TIM234_CR1_OPM      3
1745 #define STM_TIM234_CR1_URS      2
1746 #define STM_TIM234_CR1_UDIS     1
1747 #define STM_TIM234_CR1_CEN      0
1748
1749 #define STM_TIM234_CR2_TI1S     7
1750 #define STM_TIM234_CR2_MMS      4
1751 #define  STM_TIM234_CR2_MMS_RESET               0
1752 #define  STM_TIM234_CR2_MMS_ENABLE              1
1753 #define  STM_TIM234_CR2_MMS_UPDATE              2
1754 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1755 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1756 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1757 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1758 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1759 #define  STM_TIM234_CR2_MMS_MASK                7
1760 #define STM_TIM234_CR2_CCDS     3
1761
1762 #define STM_TIM234_SMCR_ETP     15
1763 #define STM_TIM234_SMCR_ECE     14
1764 #define STM_TIM234_SMCR_ETPS    12
1765 #define  STM_TIM234_SMCR_ETPS_OFF               0
1766 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1767 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1768 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1769 #define  STM_TIM234_SMCR_ETPS_MASK              3
1770 #define STM_TIM234_SMCR_ETF     8
1771 #define  STM_TIM234_SMCR_ETF_NONE               0
1772 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1773 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1774 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1775 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1776 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1777 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1778 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1779 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1780 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1781 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1782 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1783 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1784 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1785 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1786 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1787 #define  STM_TIM234_SMCR_ETF_MASK               15
1788 #define STM_TIM234_SMCR_MSM     7
1789 #define STM_TIM234_SMCR_TS      4
1790 #define  STM_TIM234_SMCR_TS_ITR0                0
1791 #define  STM_TIM234_SMCR_TS_ITR1                1
1792 #define  STM_TIM234_SMCR_TS_ITR2                2
1793 #define  STM_TIM234_SMCR_TS_ITR3                3
1794 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1795 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1796 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1797 #define  STM_TIM234_SMCR_TS_ETRF                7
1798 #define  STM_TIM234_SMCR_TS_MASK                7
1799 #define STM_TIM234_SMCR_OCCS    3
1800 #define STM_TIM234_SMCR_SMS     0
1801 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1802 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1803 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1804 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1805 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1806 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1807 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1808 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1809 #define  STM_TIM234_SMCR_SMS_MASK               7
1810
1811 #define STM_TIM234_DIER_TDE             14
1812 #define STM_TIM234_DIER_CC4DE           12
1813 #define STM_TIM234_DIER_CC3DE           11
1814 #define STM_TIM234_DIER_CC2DE           10
1815 #define STM_TIM234_DIER_CC1DE           9
1816 #define STM_TIM234_DIER_UDE             8
1817
1818 #define STM_TIM234_DIER_TIE             6
1819 #define STM_TIM234_DIER_CC4IE           4
1820 #define STM_TIM234_DIER_CC3IE           3
1821 #define STM_TIM234_DIER_CC2IE           2
1822 #define STM_TIM234_DIER_CC1IE           1
1823 #define STM_TIM234_DIER_UIE             0
1824
1825 #define STM_TIM234_SR_CC4OF     12
1826 #define STM_TIM234_SR_CC3OF     11
1827 #define STM_TIM234_SR_CC2OF     10
1828 #define STM_TIM234_SR_CC1OF     9
1829 #define STM_TIM234_SR_TIF       6
1830 #define STM_TIM234_SR_CC4IF     4
1831 #define STM_TIM234_SR_CC3IF     3
1832 #define STM_TIM234_SR_CC2IF     2
1833 #define STM_TIM234_SR_CC1IF     1
1834 #define STM_TIM234_SR_UIF       0
1835
1836 #define STM_TIM234_EGR_TG       6
1837 #define STM_TIM234_EGR_CC4G     4
1838 #define STM_TIM234_EGR_CC3G     3
1839 #define STM_TIM234_EGR_CC2G     2
1840 #define STM_TIM234_EGR_CC1G     1
1841 #define STM_TIM234_EGR_UG       0
1842
1843 #define STM_TIM234_CCMR1_OC2CE  15
1844 #define STM_TIM234_CCMR1_OC2M   12
1845 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1846 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1847 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1848 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1849 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1850 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1851 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1852 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1853 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1854 #define STM_TIM234_CCMR1_OC2PE  11
1855 #define STM_TIM234_CCMR1_OC2FE  10
1856 #define STM_TIM234_CCMR1_CC2S   8
1857 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1858 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1859 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1860 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1861 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1862
1863 #define STM_TIM234_CCMR1_OC1CE  7
1864 #define STM_TIM234_CCMR1_OC1M   4
1865 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1866 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1867 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1868 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1869 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1870 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1871 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1872 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1873 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1874 #define STM_TIM234_CCMR1_OC1PE  3
1875 #define STM_TIM234_CCMR1_OC1FE  2
1876 #define STM_TIM234_CCMR1_CC1S   0
1877 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1878 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1879 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1880 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1881 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1882
1883 #define STM_TIM234_CCMR1_IC2F   12
1884 #define  STM_TIM234_CCMR1_IC2F_NONE                     0
1885 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_2               1
1886 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_4               2
1887 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_8               3
1888 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_6                4
1889 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_8                5
1890 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_6                6
1891 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_8                7
1892 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_6                8
1893 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_8                9
1894 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_5               10
1895 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_6               11
1896 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_8               12
1897 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_5               13
1898 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_6               14
1899 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_8               15
1900 #define STM_TIM234_CCMR1_IC2PSC 10
1901 #define  STM_TIM234_CCMR1_IC2PSC_NONE                   0
1902 #define  STM_TIM234_CCMR1_IC2PSC_2                      1
1903 #define  STM_TIM234_CCMR1_IC2PSC_4                      2
1904 #define  STM_TIM234_CCMR1_IC2PSC_8                      3
1905 #define STM_TIM234_CCMR1_IC1F   4
1906 #define  STM_TIM234_CCMR1_IC1F_NONE                     0
1907 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_2               1
1908 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_4               2
1909 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_8               3
1910 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_6                4
1911 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_8                5
1912 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_6                6
1913 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_8                7
1914 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_6                8
1915 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_8                9
1916 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_5               10
1917 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_6               11
1918 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_8               12
1919 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_5               13
1920 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_6               14
1921 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_8               15
1922 #define STM_TIM234_CCMR1_IC1PSC 2
1923 #define  STM_TIM234_CCMR1_IC1PSC_NONE                   0
1924 #define  STM_TIM234_CCMR1_IC1PSC_2                      1
1925 #define  STM_TIM234_CCMR1_IC1PSC_4                      2
1926 #define  STM_TIM234_CCMR1_IC1PSC_8                      3
1927
1928 #define STM_TIM234_CCMR2_OC4CE  15
1929 #define STM_TIM234_CCMR2_OC4M   12
1930 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1931 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1932 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1933 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1934 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1935 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1936 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1937 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1938 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1939 #define STM_TIM234_CCMR2_OC4PE  11
1940 #define STM_TIM234_CCMR2_OC4FE  10
1941 #define STM_TIM234_CCMR2_CC4S   8
1942 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1943 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1944 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1945 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1946 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1947
1948 #define STM_TIM234_CCMR2_OC3CE  7
1949 #define STM_TIM234_CCMR2_OC3M   4
1950 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1951 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1952 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1953 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1954 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1955 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1956 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1957 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1958 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1959 #define STM_TIM234_CCMR2_OC3PE  3
1960 #define STM_TIM234_CCMR2_OC3FE  2
1961 #define STM_TIM234_CCMR2_CC3S   0
1962 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1963 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1964 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1965 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1966 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1967
1968 #define STM_TIM234_CCER_CC4NP   15
1969 #define STM_TIM234_CCER_CC4P    13
1970 #define  STM_TIM234_CCER_CC4P_ACTIVE_HIGH       0
1971 #define  STM_TIM234_CCER_CC4P_ACTIVE_LOW        1
1972 #define STM_TIM234_CCER_CC4E    12
1973 #define STM_TIM234_CCER_CC3NP   11
1974 #define STM_TIM234_CCER_CC3P    9
1975 #define  STM_TIM234_CCER_CC3P_ACTIVE_HIGH       0
1976 #define  STM_TIM234_CCER_CC3P_ACTIVE_LOW        1
1977 #define STM_TIM234_CCER_CC3E    8
1978 #define STM_TIM234_CCER_CC2NP   7
1979 #define STM_TIM234_CCER_CC2P    5
1980 #define  STM_TIM234_CCER_CC2P_ACTIVE_HIGH       0
1981 #define  STM_TIM234_CCER_CC2P_ACTIVE_LOW        1
1982 #define STM_TIM234_CCER_CC2E    4
1983 #define STM_TIM234_CCER_CC1NP   3
1984 #define STM_TIM234_CCER_CC1P    1
1985 #define  STM_TIM234_CCER_CC1P_ACTIVE_HIGH       0
1986 #define  STM_TIM234_CCER_CC1P_ACTIVE_LOW        1
1987 #define STM_TIM234_CCER_CC1E    0
1988
1989 struct stm_usb {
1990         vuint32_t       epr[8];
1991         uint8_t         reserved_20[0x40 - 0x20];
1992         vuint32_t       cntr;
1993         vuint32_t       istr;
1994         vuint32_t       fnr;
1995         vuint32_t       daddr;
1996         vuint32_t       btable;
1997 };
1998
1999 #define STM_USB_EPR_CTR_RX      15
2000 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
2001 #define STM_USB_EPR_DTOG_RX     14
2002 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
2003 #define STM_USB_EPR_STAT_RX     12
2004 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
2005 #define  STM_USB_EPR_STAT_RX_STALL                      1
2006 #define  STM_USB_EPR_STAT_RX_NAK                        2
2007 #define  STM_USB_EPR_STAT_RX_VALID                      3
2008 #define  STM_USB_EPR_STAT_RX_MASK                       3
2009 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
2010 #define STM_USB_EPR_SETUP       11
2011 #define STM_USB_EPR_EP_TYPE     9
2012 #define  STM_USB_EPR_EP_TYPE_BULK                       0
2013 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
2014 #define  STM_USB_EPR_EP_TYPE_ISO                        2
2015 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
2016 #define  STM_USB_EPR_EP_TYPE_MASK                       3
2017 #define STM_USB_EPR_EP_KIND     8
2018 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
2019 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
2020 #define STM_USB_EPR_CTR_TX      7
2021 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
2022 #define STM_USB_EPR_DTOG_TX     6
2023 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
2024 #define STM_USB_EPR_STAT_TX     4
2025 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
2026 #define  STM_USB_EPR_STAT_TX_STALL                      1
2027 #define  STM_USB_EPR_STAT_TX_NAK                        2
2028 #define  STM_USB_EPR_STAT_TX_VALID                      3
2029 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
2030 #define  STM_USB_EPR_STAT_TX_MASK                       3
2031 #define STM_USB_EPR_EA          0
2032 #define  STM_USB_EPR_EA_MASK                            0xf
2033
2034 #define STM_USB_CNTR_CTRM       15
2035 #define STM_USB_CNTR_PMAOVRM    14
2036 #define STM_USB_CNTR_ERRM       13
2037 #define STM_USB_CNTR_WKUPM      12
2038 #define STM_USB_CNTR_SUSPM      11
2039 #define STM_USB_CNTR_RESETM     10
2040 #define STM_USB_CNTR_SOFM       9
2041 #define STM_USB_CNTR_ESOFM      8
2042 #define STM_USB_CNTR_RESUME     4
2043 #define STM_USB_CNTR_FSUSP      3
2044 #define STM_USB_CNTR_LP_MODE    2
2045 #define STM_USB_CNTR_PDWN       1
2046 #define STM_USB_CNTR_FRES       0
2047
2048 #define STM_USB_ISTR_CTR        15
2049 #define STM_USB_ISTR_PMAOVR     14
2050 #define STM_USB_ISTR_ERR        13
2051 #define STM_USB_ISTR_WKUP       12
2052 #define STM_USB_ISTR_SUSP       11
2053 #define STM_USB_ISTR_RESET      10
2054 #define STM_USB_ISTR_SOF        9
2055 #define STM_USB_ISTR_ESOF       8
2056 #define STM_USB_ISTR_DIR        4
2057 #define STM_USB_ISTR_EP_ID      0
2058 #define  STM_USB_ISTR_EP_ID_MASK                0xf
2059
2060 #define STM_USB_FNR_RXDP        15
2061 #define STM_USB_FNR_RXDM        14
2062 #define STM_USB_FNR_LCK         13
2063 #define STM_USB_FNR_LSOF        11
2064 #define  STM_USB_FNR_LSOF_MASK                  0x3
2065 #define STM_USB_FNR_FN          0
2066 #define  STM_USB_FNR_FN_MASK                    0x7ff
2067
2068 #define STM_USB_DADDR_EF        7
2069 #define STM_USB_DADDR_ADD       0
2070 #define  STM_USB_DADDR_ADD_MASK                 0x7f
2071
2072 extern struct stm_usb stm_usb;
2073
2074 union stm_usb_bdt {
2075         struct {
2076                 vuint32_t       addr_tx;
2077                 vuint32_t       count_tx;
2078                 vuint32_t       addr_rx;
2079                 vuint32_t       count_rx;
2080         } single;
2081         struct {
2082                 vuint32_t       addr;
2083                 vuint32_t       count;
2084         } double_tx[2];
2085         struct {
2086                 vuint32_t       addr;
2087                 vuint32_t       count;
2088         } double_rx[2];
2089 };
2090
2091 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
2092 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
2093 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
2094 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
2095 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
2096
2097 #define STM_USB_BDT_SIZE        8
2098
2099 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
2100
2101 struct stm_exti {
2102         vuint32_t       imr;
2103         vuint32_t       emr;
2104         vuint32_t       rtsr;
2105         vuint32_t       ftsr;
2106
2107         vuint32_t       swier;
2108         vuint32_t       pr;
2109 };
2110
2111 extern struct stm_exti stm_exti;
2112
2113 #endif /* _STM32L0_H_ */