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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32L0_H_
  20 #define _STM32L0_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile uint16_t       vuint16_t;
  26 typedef volatile void *         vvoid_t;
  27
  28 struct stm_gpio {
  29         vuint32_t       moder;
  30         vuint32_t       otyper;
  31         vuint32_t       ospeedr;
  32         vuint32_t       pupdr;
  33
  34         vuint32_t       idr;
  35         vuint32_t       odr;
  36         vuint32_t       bsrr;
  37         vuint32_t       lckr;
  38
  39         vuint32_t       afrl;
  40         vuint32_t       afrh;
  41         vuint32_t       brr;
  42 };
  43
  44 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  45 #define STM_MODER_MASK                  3
  46 #define STM_MODER_INPUT                 0
  47 #define STM_MODER_OUTPUT                1
  48 #define STM_MODER_ALTERNATE             2
  49 #define STM_MODER_ANALOG                3
  50
  51 static inline void
  52 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  53         gpio->moder = ((gpio->moder &
  54                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  55                        value << STM_MODER_SHIFT(pin));
  56 }
  57
  58 static inline uint32_t
  59 stm_spread_mask(uint16_t mask) {
  60         uint32_t m = mask;
  61
  62         /* 0000000000000000mmmmmmmmmmmmmmmm */
  63         m = (m & 0xff) | ((m & 0xff00) << 8);
  64         /* 00000000mmmmmmmm00000000mmmmmmmm */
  65         m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4);
  66         /* 0000mmmm0000mmmm0000mmmm0000mmmm */
  67         m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2);
  68         /* 00mm00mm00mm00mm00mm00mm00mm00mm */
  69         m = (m & 0x11111111) | ((m & 0x22222222) << 2);
  70         /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */
  71         return m;
  72 }
  73
  74 static inline void
  75 stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
  76         uint32_t        bits32 = stm_spread_mask(mask);
  77         uint32_t        mask32 = 3 * bits32;
  78         uint32_t        value32 = (value & 3) * bits32;
  79
  80         gpio->moder = ((gpio->moder & ~mask32) | value32);
  81 }
  82
  83 static inline uint32_t
  84 stm_moder_get(struct stm_gpio *gpio, int pin) {
  85         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  86 }
  87
  88 #define STM_OTYPER_SHIFT(pin)           (pin)
  89 #define STM_OTYPER_MASK                 1
  90 #define STM_OTYPER_PUSH_PULL            0
  91 #define STM_OTYPER_OPEN_DRAIN           1
  92
  93 static inline void
  94 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  95         gpio->otyper = ((gpio->otyper &
  96                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  97                         value << STM_OTYPER_SHIFT(pin));
  98 }
  99
 100 static inline uint32_t
 101 stm_otyper_get(struct stm_gpio *gpio, int pin) {
 102         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
 103 }
 104
 105 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
 106 #define STM_OSPEEDR_MASK                3
 107 #define STM_OSPEEDR_LOW                 0
 108 #define STM_OSPEEDR_MEDIUM              1
 109 #define STM_OSPEEDR_HIGH                2
 110 #define STM_OSPEEDR_VERY_HIGH           3
 111
 112 static inline void
 113 stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 114         gpio->ospeedr = ((gpio->ospeedr &
 115                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
 116                        value << STM_OSPEEDR_SHIFT(pin));
 117 }
 118
 119 static inline void
 120 stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 121         uint32_t        bits32 = stm_spread_mask(mask);
 122         uint32_t        mask32 = 3 * bits32;
 123         uint32_t        value32 = (value & 3) * bits32;
 124
 125         gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32);
 126 }
 127
 128 static inline uint32_t
 129 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
 130         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
 131 }
 132
 133 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
 134 #define STM_PUPDR_MASK                  3
 135 #define STM_PUPDR_NONE                  0
 136 #define STM_PUPDR_PULL_UP               1
 137 #define STM_PUPDR_PULL_DOWN             2
 138 #define STM_PUPDR_RESERVED              3
 139
 140 static inline void
 141 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 142         gpio->pupdr = ((gpio->pupdr &
 143                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 144                        value << STM_PUPDR_SHIFT(pin));
 145 }
 146
 147 static inline void
 148 stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
 149         uint32_t        bits32 = stm_spread_mask(mask);
 150         uint32_t        mask32 = 3 * bits32;
 151         uint32_t        value32 = (value & 3) * bits32;
 152
 153         gpio->pupdr = (gpio->pupdr & ~mask32) | value32;
 154 }
 155
 156 static inline uint32_t
 157 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 158         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 159 }
 160
 161 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 162 #define STM_AFR_MASK                    0xf
 163 #define STM_AFR_NONE                    0
 164 #define STM_AFR_AF0                     0x0
 165 #define STM_AFR_AF1                     0x1
 166 #define STM_AFR_AF2                     0x2
 167 #define STM_AFR_AF3                     0x3
 168 #define STM_AFR_AF4                     0x4
 169 #define STM_AFR_AF5                     0x5
 170 #define STM_AFR_AF6                     0x6
 171 #define STM_AFR_AF7                     0x7
 172 #define STM_AFR_AF8                     0x8
 173 #define STM_AFR_AF9                     0x9
 174 #define STM_AFR_AF10                    0xa
 175 #define STM_AFR_AF11                    0xb
 176 #define STM_AFR_AF12                    0xc
 177 #define STM_AFR_AF13                    0xd
 178 #define STM_AFR_AF14                    0xe
 179 #define STM_AFR_AF15                    0xf
 180
 181 static inline void
 182 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 183         /*
 184          * Set alternate pin mode too
 185          */
 186         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 187         if (pin < 8)
 188                 gpio->afrl = ((gpio->afrl &
 189                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 190                               value << STM_AFR_SHIFT(pin));
 191         else {
 192                 pin -= 8;
 193                 gpio->afrh = ((gpio->afrh &
 194                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 195                               value << STM_AFR_SHIFT(pin));
 196         }
 197 }
 198
 199 static inline uint32_t
 200 stm_afr_get(struct stm_gpio *gpio, int pin) {
 201         if (pin < 8)
 202                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 203         else {
 204                 pin -= 8;
 205                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 206         }
 207 }
 208
 209 static inline void
 210 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 211         /* Use the bit set/reset register to do this atomically */
 212         gpio->bsrr = value ? (1 << pin) : (1 << (pin + 16));
 213 }
 214
 215 static inline void
 216 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
 217         /* Use the bit set/reset register to do this atomically */
 218         gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
 219 }
 220
 221 static inline void
 222 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 223         gpio->bsrr = bits;
 224 }
 225
 226 static inline void
 227 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 228         gpio->bsrr = ((uint32_t) bits) << 16;
 229 }
 230
 231 static inline uint8_t
 232 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 233         return (gpio->idr >> pin) & 1;
 234 }
 235
 236 static inline uint16_t
 237 stm_gpio_get_all(struct stm_gpio *gpio) {
 238         return gpio->idr;
 239 }
 240
 241 /*
 242  * We can't define these in registers.ld or our fancy
 243  * ao_enable_gpio macro will expand into a huge pile of code
 244  * as the compiler won't do correct constant folding and
 245  * dead-code elimination
 246  */
 247
 248 extern struct stm_gpio stm_gpioa;
 249 extern struct stm_gpio stm_gpiob;
 250 extern struct stm_gpio stm_gpioc;
 251 extern struct stm_gpio stm_gpiod;
 252 extern struct stm_gpio stm_gpioe;
 253 extern struct stm_gpio stm_gpioh;
 254
 255 #define stm_gpiob  (*((struct stm_gpio *) 0x50000400))
 256 #define stm_gpioa  (*((struct stm_gpio *) 0x50000000))
 257
 258 struct stm_usart {
 259         vuint32_t       cr1;    /* control register 1 */
 260         vuint32_t       cr2;    /* control register 2 */
 261         vuint32_t       cr3;    /* control register 3 */
 262         vuint32_t       brr;    /* baud rate register */
 263
 264         vuint32_t       gtpr;   /* guard time and prescaler */
 265         vuint32_t       rtor;   /* receiver timeout register */
 266         vuint32_t       rqr;    /* request register */
 267         vuint32_t       isr;    /* interrupt and status register */
 268
 269         vuint32_t       icr;    /* interrupt flag clear register */
 270         vuint32_t       rdr;    /* receive data register */
 271         vuint32_t       tdr;    /* transmit data register */
 272 };
 273
 274 #define STM_USART_CR1_M1        28
 275 #define STM_USART_CR1_EOBIE     27
 276 #define STM_USART_CR1_RTOIE     26
 277 #define STM_USART_CR1_DEAT      21
 278 #define STM_USART_CR1_DEDT      16
 279 #define STM_USART_CR1_OVER8     15
 280 #define STM_USART_CR1_CMIE      14
 281 #define STM_USART_CR1_MME       13
 282 #define STM_USART_CR1_M0        12
 283 #define STM_USART_CR1_WAKE      11
 284 #define STM_USART_CR1_PCE       10
 285 #define STM_USART_CR1_PS        9
 286 #define STM_USART_CR1_PEIE      8
 287 #define STM_USART_CR1_TXEIE     7
 288 #define STM_USART_CR1_TCIE      6
 289 #define STM_USART_CR1_RXNEIE    5
 290 #define STM_USART_CR1_IDLEIE    4
 291 #define STM_USART_CR1_TE        3
 292 #define STM_USART_CR1_RE        2
 293 #define STM_USART_CR1_UESM      1
 294 #define STM_USART_CR1_UE        0
 295
 296 #define STM_USART_CR2_ADD       24
 297 #define STM_USART_CR2_RTOEN     23
 298 #define STM_USART_CR2_ABRMOD    21
 299 #define STM_USART_CR2_ABREN     20
 300 #define STM_USART_CR2_MSBFIRST  19
 301 #define STM_USART_CR2_DATAINV   18
 302 #define STM_USART_CR2_TXINV     17
 303 #define STM_USART_CR2_RXINV     16
 304 #define STM_USART_CR2_SWAP      15
 305 #define STM_USART_CR2_LINEN     14
 306 #define STM_USART_CR2_STOP      12
 307 #define STM_USART_CR2_CLKEN     11
 308 #define STM_USART_CR2_CPOL      10
 309 #define STM_USART_CR2_CHPA      9
 310 #define STM_USART_CR2_LBCL      8
 311 #define STM_USART_CR2_LBDIE     6
 312 #define STM_USART_CR2_LBDL      5
 313 #define STM_USART_CR2_ADDM7     4
 314
 315 #define STM_USART_CR3_WUFIE     22
 316 #define STM_USART_CR3_WUS       20
 317 #define STM_USART_CR3_SCARCNT   17
 318 #define STM_USART_CR3_DEP       15
 319 #define STM_USART_CR3_DEM       14
 320 #define STM_USART_CR3_DDRE      13
 321 #define STM_USART_CR3_OVRDIS    12
 322 #define STM_USART_CR3_ONEBIT    11
 323 #define STM_USART_CR3_CTIIE     10
 324 #define STM_USART_CR3_CTSE      9
 325 #define STM_USART_CR3_RTSE      8
 326 #define STM_USART_CR3_DMAT      7
 327 #define STM_USART_CR3_DMAR      6
 328 #define STM_USART_CR3_SCEN      5
 329 #define STM_USART_CR3_NACK      4
 330 #define STM_USART_CR3_HDSEL     3
 331 #define STM_USART_CR3_IRLP      2
 332 #define STM_USART_CR3_IREN      1
 333 #define STM_USART_CR3_EIE       0
 334
 335 #define STM_USART_GTPR_GT       8
 336 #define STM_USART_GTPR_PSC      0
 337
 338 #define STM_USART_RQR_TXFRQ     4
 339 #define STM_USART_RQR_RXFRQ     3
 340 #define STM_USART_RQR_MMRQ      2
 341 #define STM_USART_RQR_SBKRQ     1
 342 #define STM_USART_RQR_ABRRQ     0
 343
 344 #define STM_USART_ISR_REACK     22
 345 #define STM_USART_ISR_TEACK     21
 346 #define STM_USART_ISR_WUF       20
 347 #define STM_USART_ISR_RWU       19
 348 #define STM_USART_ISR_SBKF      18
 349 #define STM_USART_ISR_CMF       17
 350 #define STM_USART_ISR_BUSY      16
 351 #define STM_USART_ISR_ABRF      15
 352 #define STM_USART_ISR_ABRE      14
 353 #define STM_USART_ISR_EOBF      12
 354 #define STM_USART_ISR_RTOF      11
 355 #define STM_USART_ISR_CTS       10
 356 #define STM_USART_ISR_CTSIF     9
 357 #define STM_USART_ISR_LBDF      8
 358 #define STM_USART_ISR_TXE       7
 359 #define STM_USART_ISR_TC        6
 360 #define STM_USART_ISR_RXNE      5
 361 #define STM_USART_ISR_IDLE      4
 362 #define STM_USART_ISR_ORE       3
 363 #define STM_USART_ISR_NF        2
 364 #define STM_USART_ISR_FE        1
 365 #define STM_USART_ISR_PE        0
 366
 367 #define STM_USART_ICR_WUCF      20
 368 #define STM_USART_ICR_CMCF      17
 369 #define STM_USART_ICR_EOBCF     12
 370 #define STM_USART_ICR_RTOCF     11
 371 #define STM_USART_ICR_CTSCF     9
 372 #define STM_USART_ICR_LBDCF     8
 373 #define STM_USART_ICR_TCCF      6
 374 #define STM_USART_ICR_IDLECF    4
 375 #define STM_USART_ICR_ORECF     3
 376 #define STM_USART_ICR_NCF       2
 377 #define STM_USART_ICR_FECF      1
 378 #define STM_USART_ICR_PECF      0
 379
 380 extern struct stm_usart stm_usart1;
 381 extern struct stm_usart stm_usart2;
 382 #define stm_usart1 (*((struct stm_usart *) 0x40013800))
 383 #define stm_usart2 (*((struct stm_usart *) 0x40004400))
 384
 385 struct stm_tim {
 386 };
 387
 388 extern struct stm_tim stm_tim9;
 389
 390 struct stm_tim1011 {
 391         vuint32_t       cr1;
 392         uint32_t        unused_4;
 393         vuint32_t       smcr;
 394         vuint32_t       dier;
 395         vuint32_t       sr;
 396         vuint32_t       egr;
 397         vuint32_t       ccmr1;
 398         uint32_t        unused_1c;
 399         vuint32_t       ccer;
 400         vuint32_t       cnt;
 401         vuint32_t       psc;
 402         vuint32_t       arr;
 403         uint32_t        unused_30;
 404         vuint32_t       ccr1;
 405         uint32_t        unused_38;
 406         uint32_t        unused_3c;
 407         uint32_t        unused_40;
 408         uint32_t        unused_44;
 409         uint32_t        unused_48;
 410         uint32_t        unused_4c;
 411         vuint32_t       or;
 412 };
 413
 414 extern struct stm_tim1011 stm_tim10;
 415 extern struct stm_tim1011 stm_tim11;
 416
 417 #define STM_TIM1011_CR1_CKD     8
 418 #define  STM_TIM1011_CR1_CKD_1          0
 419 #define  STM_TIM1011_CR1_CKD_2          1
 420 #define  STM_TIM1011_CR1_CKD_4          2
 421 #define  STM_TIM1011_CR1_CKD_MASK       3
 422 #define STM_TIM1011_CR1_ARPE    7
 423 #define STM_TIM1011_CR1_URS     2
 424 #define STM_TIM1011_CR1_UDIS    1
 425 #define STM_TIM1011_CR1_CEN     0
 426
 427 #define STM_TIM1011_SMCR_ETP    15
 428 #define STM_TIM1011_SMCR_ECE    14
 429 #define STM_TIM1011_SMCR_ETPS   12
 430 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 431 #define  STM_TIM1011_SMCR_ETPS_2        1
 432 #define  STM_TIM1011_SMCR_ETPS_4        2
 433 #define  STM_TIM1011_SMCR_ETPS_8        3
 434 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 435 #define STM_TIM1011_SMCR_ETF    8
 436 #define  STM_TIM1011_SMCR_ETF_NONE              0
 437 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 438 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 439 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 440 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 441 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 442 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 443 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 444 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 445 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 446 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 447 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 448 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 449 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 450 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 451 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 452 #define  STM_TIM1011_SMCR_ETF_MASK              15
 453
 454 #define STM_TIM1011_DIER_CC1E   1
 455 #define STM_TIM1011_DIER_UIE    0
 456
 457 #define STM_TIM1011_SR_CC1OF    9
 458 #define STM_TIM1011_SR_CC1IF    1
 459 #define STM_TIM1011_SR_UIF      0
 460
 461 #define STM_TIM1011_EGR_CC1G    1
 462 #define STM_TIM1011_EGR_UG      0
 463
 464 #define STM_TIM1011_CCMR1_OC1CE 7
 465 #define STM_TIM1011_CCMR1_OC1M  4
 466 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 467 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 468 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 469 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 470 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 471 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 472 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 473 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 474 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 475 #define STM_TIM1011_CCMR1_OC1PE 3
 476 #define STM_TIM1011_CCMR1_OC1FE 2
 477 #define STM_TIM1011_CCMR1_CC1S  0
 478 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 479 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 480 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 481 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 482 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 483
 484 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 485 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 486 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 487 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 488 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 489 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 490 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 491 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 492 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 493 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 494 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 495 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 496 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 497 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 498 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 499 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 500 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 501 #define STM_TIM1011_CCMR1_IC1PSC        2
 502 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 503 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 504 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 505 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 506 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 507 #define STM_TIM1011_CCMR1_CC1S          0
 508
 509 #define STM_TIM1011_CCER_CC1NP          3
 510 #define STM_TIM1011_CCER_CC1P           1
 511 #define STM_TIM1011_CCER_CC1E           0
 512
 513 #define STM_TIM1011_OR_TI1_RMP_RI       3
 514 #define STM_TIM1011_ETR_RMP             2
 515 #define STM_TIM1011_TI1_RMP             0
 516 #define  STM_TIM1011_TI1_RMP_GPIO               0
 517 #define  STM_TIM1011_TI1_RMP_LSI                1
 518 #define  STM_TIM1011_TI1_RMP_LSE                2
 519 #define  STM_TIM1011_TI1_RMP_RTC                3
 520 #define  STM_TIM1011_TI1_RMP_MASK               3
 521
 522 struct stm_rcc {
 523         vuint32_t       cr;
 524         vuint32_t       icscr;
 525         uint32_t        unused08;
 526         vuint32_t       cfgr;
 527
 528         vuint32_t       cier;
 529         vuint32_t       cifr;
 530         vuint32_t       cicr;
 531         vuint32_t       iopstr;
 532
 533         vuint32_t       ahbrstr;
 534         vuint32_t       apb2rstr;
 535         vuint32_t       apb1rstr;
 536         vuint32_t       iopenr;
 537
 538         vuint32_t       ahbenr;
 539         vuint32_t       apb2enr;
 540         vuint32_t       apb1enr;
 541         vuint32_t       iopsmen;
 542
 543         vuint32_t       ahbsmenr;
 544         vuint32_t       apb2smenr;
 545         vuint32_t       apb1smenr;
 546         vuint32_t       ccipr;
 547
 548         vuint32_t       csr;
 549 };
 550
 551 extern struct stm_rcc stm_rcc;
 552
 553 /* Nominal high speed internal oscillator frequency is 16MHz */
 554 #define STM_HSI_FREQ            16000000
 555 #define STM_MSI_FREQ_65536      65536
 556 #define STM_MSI_FREQ_131072     131072
 557 #define STM_MSI_FREQ_262144     262144
 558 #define STM_MSI_FREQ_524288     524288
 559 #define STM_MSI_FREQ_1048576    1048576
 560 #define STM_MSI_FREQ_2097152    2097152
 561 #define STM_MSI_FREQ_4194304    4194304
 562
 563 #define STM_RCC_CR_RTCPRE       (29)
 564 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 565 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 566 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 567 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 568 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 569
 570 #define STM_RCC_CR_CSSON        (28)
 571 #define STM_RCC_CR_PLLRDY       (25)
 572 #define STM_RCC_CR_PLLON        (24)
 573 #define STM_RCC_CR_HSEBYP       (18)
 574 #define STM_RCC_CR_HSERDY       (17)
 575 #define STM_RCC_CR_HSEON        (16)
 576 #define STM_RCC_CR_MSIRDY       (9)
 577 #define STM_RCC_CR_MSION        (8)
 578 #define STM_RCC_CR_HSIRDY       (1)
 579 #define STM_RCC_CR_HSION        (0)
 580
 581 #define STM_RCC_ICSCR_HSI16CAL  0
 582 #define STM_RCC_ICSCR_HSI16TRIM 8
 583 #define STM_RCC_ICSCR_MSIRANGE  13
 584 #define  STM_RCC_ICSCR_MSIRANGE_65536   0
 585 #define  STM_RCC_ICSCR_MSIRANGE_131072
 586 #define  STM_RCC_ICSCR_MSIRANGE_262144  2
 587 #define  STM_RCC_ICSCR_MSIRANGE_524288  3
 588 #define  STM_RCC_ICSCR_MSIRANGE_1048576 4
 589 #define  STM_RCC_ICSCR_MSIRANGE_2097152 5
 590 #define  STM_RCC_ICSCR_MSIRANGE_4194304 6
 591 #define  STM_RCC_ICSCR_MSIRANGE_MASK    0x7
 592 #define STM_RCC_ICSCR_MSICAL    16
 593 #define STM_RCC_ICSCR_MSITRIM   24
 594
 595 #define STM_RCC_CFGR_MCOPRE     (28)
 596 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 597 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 598 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 599 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 600 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 601 #define  STM_RCC_CFGR_MCOPRE_MASK       7
 602
 603 #define STM_RCC_CFGR_MCOSEL     (24)
 604 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 605 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 606 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 607 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 608 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 609 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 610 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 611 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 612 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 613
 614 #define STM_RCC_CFGR_PLLDIV     (22)
 615 #define  STM_RCC_CFGR_PLLDIV_2          1
 616 #define  STM_RCC_CFGR_PLLDIV_3          2
 617 #define  STM_RCC_CFGR_PLLDIV_4          3
 618 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 619
 620 #define STM_RCC_CFGR_PLLMUL     (18)
 621 #define  STM_RCC_CFGR_PLLMUL_3          0
 622 #define  STM_RCC_CFGR_PLLMUL_4          1
 623 #define  STM_RCC_CFGR_PLLMUL_6          2
 624 #define  STM_RCC_CFGR_PLLMUL_8          3
 625 #define  STM_RCC_CFGR_PLLMUL_12         4
 626 #define  STM_RCC_CFGR_PLLMUL_16         5
 627 #define  STM_RCC_CFGR_PLLMUL_24         6
 628 #define  STM_RCC_CFGR_PLLMUL_32         7
 629 #define  STM_RCC_CFGR_PLLMUL_48         8
 630 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 631
 632 #define STM_RCC_CFGR_PLLSRC     (16)
 633
 634 #define STM_RCC_CFGR_PPRE2      (11)
 635 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 636 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 637 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 638 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 639 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 640 #define  STM_RCC_CFGR_PPRE2_MASK        7
 641
 642 #define STM_RCC_CFGR_PPRE1      (8)
 643 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 644 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 645 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 646 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 647 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 648 #define  STM_RCC_CFGR_PPRE1_MASK        7
 649
 650 #define STM_RCC_CFGR_HPRE       (4)
 651 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 652 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 653 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 654 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 655 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 656 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 657 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 658 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 659 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 660 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 661
 662 #define STM_RCC_CFGR_SWS        (2)
 663 #define  STM_RCC_CFGR_SWS_MSI           0
 664 #define  STM_RCC_CFGR_SWS_HSI           1
 665 #define  STM_RCC_CFGR_SWS_HSE           2
 666 #define  STM_RCC_CFGR_SWS_PLL           3
 667 #define  STM_RCC_CFGR_SWS_MASK          3
 668
 669 #define STM_RCC_CFGR_SW         (0)
 670 #define  STM_RCC_CFGR_SW_MSI            0
 671 #define  STM_RCC_CFGR_SW_HSI            1
 672 #define  STM_RCC_CFGR_SW_HSE            2
 673 #define  STM_RCC_CFGR_SW_PLL            3
 674 #define  STM_RCC_CFGR_SW_MASK           3
 675
 676 #define STM_RCC_IOPENR_IOPAEN           0
 677 #define STM_RCC_IOPENR_IOPBEN           1
 678 #define STM_RCC_IOPENR_IOPCEN           2
 679 #define STM_RCC_IOPENR_IOPDEN           3
 680 #define STM_RCC_IOPENR_IOPEEN           4
 681 #define STM_RCC_IOPENR_IOPHEN           7
 682
 683 #define STM_RCC_AHBENR_DMA1EN           0
 684 #define STM_RCC_AHBENR_MIFEN            8
 685 #define STM_RCC_AHBENR_CRCEN            12
 686 #define STM_RCC_AHBENR_CRYPEN           24
 687
 688 #define STM_RCC_APB2ENR_DBGEN           (22)
 689 #define STM_RCC_APB2ENR_USART1EN        (14)
 690 #define STM_RCC_APB2ENR_SPI1EN          (12)
 691 #define STM_RCC_APB2ENR_ADCEN           (9)
 692 #define STM_RCC_APB2ENR_FWEN            (7)
 693 #define STM_RCC_APB2ENR_TIM22EN         (5)
 694 #define STM_RCC_APB2ENR_TIM21EN         (2)
 695 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 696
 697 #define STM_RCC_APB1ENR_LPTIM1EN        31
 698 #define STM_RCC_APB1ENR_I2C3EN          30
 699 #define STM_RCC_APB1ENR_PWREN           28
 700 #define STM_RCC_APB1ENR_I2C2EN          22
 701 #define STM_RCC_APB1ENR_I2C1EN          21
 702 #define STM_RCC_APB1ENR_USART5EN        20
 703 #define STM_RCC_APB1ENR_USART4EN        19
 704 #define STM_RCC_APB1ENR_LPUART1EN       18
 705 #define STM_RCC_APB1ENR_USART2EN        17
 706 #define STM_RCC_APB1ENR_SPI2EN          14
 707 #define STM_RCC_APB1ENR_WWDGEN          11
 708 #define STM_RCC_APB1ENR_TIM7EN          5
 709 #define STM_RCC_APB1ENR_TIM6EN          4
 710 #define STM_RCC_APB1ENR_TIM3EN          1
 711 #define STM_RCC_APB1ENR_TIM2EN          0
 712
 713 #define STM_RCC_CSR_LPWRRSTF            (31)
 714 #define STM_RCC_CSR_WWDGRSTF            (30)
 715 #define STM_RCC_CSR_IWDGRSTF            (29)
 716 #define STM_RCC_CSR_SFTRSTF             (28)
 717 #define STM_RCC_CSR_PORRSTF             (27)
 718 #define STM_RCC_CSR_PINRSTF             (26)
 719 #define STM_RCC_CSR_OBLRSTF             (25)
 720 #define STM_RCC_CSR_RMVF                (24)
 721 #define STM_RCC_CSR_RTFRST              (23)
 722 #define STM_RCC_CSR_RTCEN               (22)
 723 #define STM_RCC_CSR_RTCSEL              (16)
 724
 725 #define  STM_RCC_CSR_RTCSEL_NONE                0
 726 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 727 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 728 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 729 #define  STM_RCC_CSR_RTCSEL_MASK                3
 730
 731 #define STM_RCC_CSR_LSEBYP              (10)
 732 #define STM_RCC_CSR_LSERDY              (9)
 733 #define STM_RCC_CSR_LSEON               (8)
 734 #define STM_RCC_CSR_LSIRDY              (1)
 735 #define STM_RCC_CSR_LSION               (0)
 736
 737 struct stm_pwr {
 738         vuint32_t       cr;
 739         vuint32_t       csr;
 740 };
 741
 742 extern struct stm_pwr stm_pwr;
 743
 744
 745 #define STM_PWR_CR_LPDS         16
 746 #define STM_PWR_CR_LPRUN        14
 747 #define STM_PWR_CR_DS_EE_KOFF   13
 748 #define STM_PWR_CR_VOS          11
 749 #define  STM_PWR_CR_VOS_1_8             1
 750 #define  STM_PWR_CR_VOS_1_5             2
 751 #define  STM_PWR_CR_VOS_1_2             3
 752 #define  STM_PWR_CR_VOS_MASK            3
 753 #define STM_PWR_CR_FWU          10
 754 #define STM_PWR_CR_ULP          9
 755 #define STM_PWR_CR_DBP          8
 756 #define STM_PWR_CR_PLS          5
 757 #define  STM_PWR_CR_PLS_1_9     0
 758 #define  STM_PWR_CR_PLS_2_1     1
 759 #define  STM_PWR_CR_PLS_2_3     2
 760 #define  STM_PWR_CR_PLS_2_5     3
 761 #define  STM_PWR_CR_PLS_2_7     4
 762 #define  STM_PWR_CR_PLS_2_9     5
 763 #define  STM_PWR_CR_PLS_3_1     6
 764 #define  STM_PWR_CR_PLS_EXT     7
 765 #define  STM_PWR_CR_PLS_MASK    7
 766 #define STM_PWR_CR_PVDE         4
 767 #define STM_PWR_CR_CSBF         3
 768 #define STM_PWR_CR_CWUF         2
 769 #define STM_PWR_CR_PDDS         1
 770 #define STM_PWR_CR_LPSDSR       0
 771
 772 #define STM_PWR_CSR_EWUP3       (10)
 773 #define STM_PWR_CSR_EWUP2       (9)
 774 #define STM_PWR_CSR_EWUP1       (8)
 775 #define STM_PWR_CSR_REGLPF      (5)
 776 #define STM_PWR_CSR_VOSF        (4)
 777 #define STM_PWR_CSR_VREFINTRDYF (3)
 778 #define STM_PWR_CSR_PVDO        (2)
 779 #define STM_PWR_CSR_SBF         (1)
 780 #define STM_PWR_CSR_WUF         (0)
 781
 782 struct stm_tim67 {
 783         vuint32_t       cr1;
 784         vuint32_t       cr2;
 785         uint32_t        _unused_08;
 786         vuint32_t       dier;
 787
 788         vuint32_t       sr;
 789         vuint32_t       egr;
 790         uint32_t        _unused_18;
 791         uint32_t        _unused_1c;
 792
 793         uint32_t        _unused_20;
 794         vuint32_t       cnt;
 795         vuint32_t       psc;
 796         vuint32_t       arr;
 797 };
 798
 799 extern struct stm_tim67 stm_tim6;
 800
 801 #define STM_TIM67_CR1_ARPE      (7)
 802 #define STM_TIM67_CR1_OPM       (3)
 803 #define STM_TIM67_CR1_URS       (2)
 804 #define STM_TIM67_CR1_UDIS      (1)
 805 #define STM_TIM67_CR1_CEN       (0)
 806
 807 #define STM_TIM67_CR2_MMS       (4)
 808 #define  STM_TIM67_CR2_MMS_RESET        0
 809 #define  STM_TIM67_CR2_MMS_ENABLE       1
 810 #define  STM_TIM67_CR2_MMS_UPDATE       2
 811 #define  STM_TIM67_CR2_MMS_MASK         7
 812
 813 #define STM_TIM67_DIER_UDE      (8)
 814 #define STM_TIM67_DIER_UIE      (0)
 815
 816 #define STM_TIM67_SR_UIF        (0)
 817
 818 #define STM_TIM67_EGR_UG        (0)
 819
 820 struct stm_lcd {
 821         vuint32_t       cr;
 822         vuint32_t       fcr;
 823         vuint32_t       sr;
 824         vuint32_t       clr;
 825         uint32_t        unused_0x10;
 826         vuint32_t       ram[8*2];
 827 };
 828
 829 extern struct stm_lcd stm_lcd;
 830
 831 #define STM_LCD_CR_MUX_SEG              (7)
 832
 833 #define STM_LCD_CR_BIAS                 (5)
 834 #define  STM_LCD_CR_BIAS_1_4            0
 835 #define  STM_LCD_CR_BIAS_1_2            1
 836 #define  STM_LCD_CR_BIAS_1_3            2
 837 #define  STM_LCD_CR_BIAS_MASK           3
 838
 839 #define STM_LCD_CR_DUTY                 (2)
 840 #define  STM_LCD_CR_DUTY_STATIC         0
 841 #define  STM_LCD_CR_DUTY_1_2            1
 842 #define  STM_LCD_CR_DUTY_1_3            2
 843 #define  STM_LCD_CR_DUTY_1_4            3
 844 #define  STM_LCD_CR_DUTY_1_8            4
 845 #define  STM_LCD_CR_DUTY_MASK           7
 846
 847 #define STM_LCD_CR_VSEL                 (1)
 848 #define STM_LCD_CR_LCDEN                (0)
 849
 850 #define STM_LCD_FCR_PS                  (22)
 851 #define  STM_LCD_FCR_PS_1               0x0
 852 #define  STM_LCD_FCR_PS_2               0x1
 853 #define  STM_LCD_FCR_PS_4               0x2
 854 #define  STM_LCD_FCR_PS_8               0x3
 855 #define  STM_LCD_FCR_PS_16              0x4
 856 #define  STM_LCD_FCR_PS_32              0x5
 857 #define  STM_LCD_FCR_PS_64              0x6
 858 #define  STM_LCD_FCR_PS_128             0x7
 859 #define  STM_LCD_FCR_PS_256             0x8
 860 #define  STM_LCD_FCR_PS_512             0x9
 861 #define  STM_LCD_FCR_PS_1024            0xa
 862 #define  STM_LCD_FCR_PS_2048            0xb
 863 #define  STM_LCD_FCR_PS_4096            0xc
 864 #define  STM_LCD_FCR_PS_8192            0xd
 865 #define  STM_LCD_FCR_PS_16384           0xe
 866 #define  STM_LCD_FCR_PS_32768           0xf
 867 #define  STM_LCD_FCR_PS_MASK            0xf
 868
 869 #define STM_LCD_FCR_DIV                 (18)
 870 #define STM_LCD_FCR_DIV_16              0x0
 871 #define STM_LCD_FCR_DIV_17              0x1
 872 #define STM_LCD_FCR_DIV_18              0x2
 873 #define STM_LCD_FCR_DIV_19              0x3
 874 #define STM_LCD_FCR_DIV_20              0x4
 875 #define STM_LCD_FCR_DIV_21              0x5
 876 #define STM_LCD_FCR_DIV_22              0x6
 877 #define STM_LCD_FCR_DIV_23              0x7
 878 #define STM_LCD_FCR_DIV_24              0x8
 879 #define STM_LCD_FCR_DIV_25              0x9
 880 #define STM_LCD_FCR_DIV_26              0xa
 881 #define STM_LCD_FCR_DIV_27              0xb
 882 #define STM_LCD_FCR_DIV_28              0xc
 883 #define STM_LCD_FCR_DIV_29              0xd
 884 #define STM_LCD_FCR_DIV_30              0xe
 885 #define STM_LCD_FCR_DIV_31              0xf
 886 #define STM_LCD_FCR_DIV_MASK            0xf
 887
 888 #define STM_LCD_FCR_BLINK               (16)
 889 #define  STM_LCD_FCR_BLINK_DISABLE              0
 890 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 891 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 892 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 893 #define  STM_LCD_FCR_BLINK_MASK                 3
 894
 895 #define STM_LCD_FCR_BLINKF              (13)
 896 #define  STM_LCD_FCR_BLINKF_8                   0
 897 #define  STM_LCD_FCR_BLINKF_16                  1
 898 #define  STM_LCD_FCR_BLINKF_32                  2
 899 #define  STM_LCD_FCR_BLINKF_64                  3
 900 #define  STM_LCD_FCR_BLINKF_128                 4
 901 #define  STM_LCD_FCR_BLINKF_256                 5
 902 #define  STM_LCD_FCR_BLINKF_512                 6
 903 #define  STM_LCD_FCR_BLINKF_1024                7
 904 #define  STM_LCD_FCR_BLINKF_MASK                7
 905
 906 #define STM_LCD_FCR_CC                  (10)
 907 #define  STM_LCD_FCR_CC_MASK                    7
 908
 909 #define STM_LCD_FCR_DEAD                (7)
 910 #define  STM_LCD_FCR_DEAD_MASK                  7
 911
 912 #define STM_LCD_FCR_PON                 (4)
 913 #define  STM_LCD_FCR_PON_MASK                   7
 914
 915 #define STM_LCD_FCR_UDDIE               (3)
 916 #define STM_LCD_FCR_SOFIE               (1)
 917 #define STM_LCD_FCR_HD                  (0)
 918
 919 #define STM_LCD_SR_FCRSF                (5)
 920 #define STM_LCD_SR_RDY                  (4)
 921 #define STM_LCD_SR_UDD                  (3)
 922 #define STM_LCD_SR_UDR                  (2)
 923 #define STM_LCD_SR_SOF                  (1)
 924 #define STM_LCD_SR_ENS                  (0)
 925
 926 #define STM_LCD_CLR_UDDC                (3)
 927 #define STM_LCD_CLR_SOFC                (1)
 928
 929 /* The SYSTICK starts at 0xe000e010 */
 930
 931 struct stm_systick {
 932         vuint32_t       csr;
 933         vuint32_t       rvr;
 934         vuint32_t       cvr;
 935         vuint32_t       calib;
 936 };
 937
 938 extern struct stm_systick stm_systick;
 939
 940 #define STM_SYSTICK_CSR_ENABLE          0
 941 #define STM_SYSTICK_CSR_TICKINT         1
 942 #define STM_SYSTICK_CSR_CLKSOURCE       2
 943 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 944 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 945 #define STM_SYSTICK_CSR_COUNTFLAG       16
 946
 947 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 948
 949 struct stm_nvic {
 950         vuint32_t       iser;           /* 0x000 0xe000e100 Set Enable Register */
 951
 952         uint8_t         _unused020[0x080 - 0x004];
 953
 954         vuint32_t       icer;           /* 0x080 0xe000e180 Clear Enable Register */
 955
 956         uint8_t         _unused0a0[0x100 - 0x084];
 957
 958         vuint32_t       ispr;           /* 0x100 0xe000e200 Set Pending Register */
 959
 960         uint8_t         _unused120[0x180 - 0x104];
 961
 962         vuint32_t       icpr;           /* 0x180 0xe000e280 Clear Pending Register */
 963
 964         uint8_t         _unused1a0[0x300 - 0x184];
 965
 966         vuint32_t       ipr[8];         /* 0x300 0xe000e400 Priority Register */
 967 };
 968
 969 extern struct stm_nvic stm_nvic;
 970
 971 #define IRQ_MASK(irq)   (1 << (irq))
 972 #define IRQ_BOOL(v,irq) (((v) >> (irq)) & 1)
 973
 974 static inline void
 975 stm_nvic_set_enable(int irq) {
 976         stm_nvic.iser = IRQ_MASK(irq);
 977 }
 978
 979 static inline void
 980 stm_nvic_clear_enable(int irq) {
 981         stm_nvic.icer = IRQ_MASK(irq);
 982 }
 983
 984 static inline int
 985 stm_nvic_enabled(int irq) {
 986         return IRQ_BOOL(stm_nvic.iser, irq);
 987 }
 988
 989 static inline void
 990 stm_nvic_set_pending(int irq) {
 991         stm_nvic.ispr = IRQ_MASK(irq);
 992 }
 993
 994 static inline void
 995 stm_nvic_clear_pending(int irq) {
 996         stm_nvic.icpr = IRQ_MASK(irq);
 997 }
 998
 999 static inline int
1000 stm_nvic_pending(int irq) {
1001         return IRQ_BOOL(stm_nvic.ispr, irq);
1002 }
1003
1004 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
1005 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
1006 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
1007
1008 static inline void
1009 stm_nvic_set_priority(int irq, uint8_t prio) {
1010         int             n = IRQ_PRIO_REG(irq);
1011         uint32_t        v;
1012
1013         v = stm_nvic.ipr[n];
1014         v &= ~IRQ_PRIO_MASK(irq);
1015         v |= (prio) << IRQ_PRIO_BIT(irq);
1016         stm_nvic.ipr[n] = v;
1017 }
1018
1019 static inline uint8_t
1020 stm_nvic_get_priority(int irq) {
1021         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1022 }
1023
1024 struct stm_scb {
1025         vuint32_t       cpuid;
1026         vuint32_t       icsr;
1027         vuint32_t       vtor;
1028         vuint32_t       aircr;
1029
1030         vuint32_t       scr;
1031         vuint32_t       ccr;
1032         vuint32_t       shpr1;
1033         vuint32_t       shpr2;
1034
1035         vuint32_t       shpr3;
1036         vuint32_t       shcrs;
1037         vuint32_t       cfsr;
1038         vuint32_t       hfsr;
1039
1040         uint32_t        unused_30;
1041         vuint32_t       mmfar;
1042         vuint32_t       bfar;
1043 };
1044
1045 extern struct stm_scb stm_scb;
1046
1047 #define STM_SCB_AIRCR_VECTKEY           16
1048 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
1049 #define STM_SCB_AIRCR_PRIGROUP          8
1050 #define STM_SCB_AIRCR_SYSRESETREQ       2
1051 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
1052 #define STM_SCB_AIRCR_VECTRESET         0
1053
1054 struct stm_mpu {
1055         vuint32_t       typer;
1056         vuint32_t       cr;
1057         vuint32_t       rnr;
1058         vuint32_t       rbar;
1059
1060         vuint32_t       rasr;
1061         vuint32_t       rbar_a1;
1062         vuint32_t       rasr_a1;
1063         vuint32_t       rbar_a2;
1064         vuint32_t       rasr_a2;
1065         vuint32_t       rbar_a3;
1066         vuint32_t       rasr_a3;
1067 };
1068
1069 extern struct stm_mpu stm_mpu;
1070
1071 #define STM_MPU_TYPER_IREGION   16
1072 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1073 #define STM_MPU_TYPER_DREGION   8
1074 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1075 #define STM_MPU_TYPER_SEPARATE  0
1076
1077 #define STM_MPU_CR_PRIVDEFENA   2
1078 #define STM_MPU_CR_HFNMIENA     1
1079 #define STM_MPU_CR_ENABLE       0
1080
1081 #define STM_MPU_RNR_REGION      0
1082 #define STM_MPU_RNR_REGION_MASK         0xff
1083
1084 #define STM_MPU_RBAR_ADDR       5
1085 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1086
1087 #define STM_MPU_RBAR_VALID      4
1088 #define STM_MPU_RBAR_REGION     0
1089 #define STM_MPU_RBAR_REGION_MASK        0xf
1090
1091 #define STM_MPU_RASR_XN         28
1092 #define STM_MPU_RASR_AP         24
1093 #define  STM_MPU_RASR_AP_NONE_NONE      0
1094 #define  STM_MPU_RASR_AP_RW_NONE        1
1095 #define  STM_MPU_RASR_AP_RW_RO          2
1096 #define  STM_MPU_RASR_AP_RW_RW          3
1097 #define  STM_MPU_RASR_AP_RO_NONE        5
1098 #define  STM_MPU_RASR_AP_RO_RO          6
1099 #define  STM_MPU_RASR_AP_MASK           7
1100 #define STM_MPU_RASR_TEX        19
1101 #define  STM_MPU_RASR_TEX_MASK          7
1102 #define STM_MPU_RASR_S          18
1103 #define STM_MPU_RASR_C          17
1104 #define STM_MPU_RASR_B          16
1105 #define STM_MPU_RASR_SRD        8
1106 #define  STM_MPU_RASR_SRD_MASK          0xff
1107 #define STM_MPU_RASR_SIZE       1
1108 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1109 #define STM_MPU_RASR_ENABLE     0
1110
1111 #define isr_decl(name) void stm_ ## name ## _isr(void)
1112
1113 isr_decl(halt);
1114 isr_decl(ignore);
1115
1116 isr_decl(nmi);
1117 isr_decl(hardfault);
1118 isr_decl(usagefault);
1119 isr_decl(svc);
1120 isr_decl(debugmon);
1121 isr_decl(pendsv);
1122 isr_decl(systick);
1123 isr_decl(wwdg);
1124 isr_decl(pvd);
1125 isr_decl(rtc);
1126 isr_decl(flash);
1127 isr_decl(rcc_crs);
1128 isr_decl(exti1_0);
1129 isr_decl(exti3_2);
1130 isr_decl(exti15_4);
1131 isr_decl(dma1_channel1);
1132 isr_decl(dma1_channel3_2);
1133 isr_decl(dma1_channel7_4);
1134 isr_decl(adc_comp);
1135 isr_decl(lptim1);
1136 isr_decl(usart4_usart5);
1137 isr_decl(tim2);
1138 isr_decl(tim3);
1139 isr_decl(tim4);
1140 isr_decl(tim6);
1141 isr_decl(tim7);
1142 isr_decl(tim21);
1143 isr_decl(i2c3);
1144 isr_decl(tim22);
1145 isr_decl(i2c1);
1146 isr_decl(i2c2);
1147 isr_decl(spi1);
1148 isr_decl(spi2);
1149 isr_decl(usart1);
1150 isr_decl(usart2);
1151 isr_decl(usart3);
1152 isr_decl(lpuart1_aes);
1153
1154 #undef isr_decl
1155
1156 #define STM_ISR_WWDG_POS                0
1157 #define STM_ISR_PVD_POS                 1
1158 #define STM_ISR_RTC_POS                 2
1159 #define STM_ISR_FLASH_POS               3
1160 #define STM_ISR_RCC_CRS_POS             4
1161 #define STM_ISR_EXTI1_0_POS             5
1162 #define STM_ISR_EXTI3_2_POS             6
1163 #define STM_ISR_EXTI15_4_POS            7
1164 #define STM_ISR_DMA1_CHANNEL1_POS       9
1165 #define STM_ISR_DMA1_CHANNEL3_2_POS     10
1166 #define STM_ISR_DMA1_CHANNEL7_4_POS     11
1167 #define STM_ISR_ADC_COMP_POS            12
1168 #define STM_ISR_LPTIM1_POS              13
1169 #define STM_ISR_USART4_USART5_POS       14
1170 #define STM_ISR_TIM2_POS                15
1171 #define STM_ISR_TIM3_POS                16
1172 #define STM_ISR_TIM6_POS                17
1173 #define STM_ISR_TIM7_POS                18
1174 #define STM_ISR_TIM21_POS               20
1175 #define STM_ISR_I2C3_POS                21
1176 #define STM_ISR_TIM22_POS               22
1177 #define STM_ISR_I2C1_POS                23
1178 #define STM_ISR_I2C2_POS                24
1179 #define STM_ISR_SPI1_POS                25
1180 #define STM_ISR_SPI2_POS                26
1181 #define STM_ISR_USART1_POS              27
1182 #define STM_ISR_USART2_POS              28
1183 #define STM_ISR_LPUART1_AES_POS         29
1184
1185 struct stm_syscfg {
1186         vuint32_t       memrmp;
1187         vuint32_t       pmc;
1188         vuint32_t       exticr[4];
1189 };
1190
1191 extern struct stm_syscfg stm_syscfg;
1192
1193 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1194 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1195 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1196 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1197 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1198
1199 #define STM_SYSCFG_PMC_USB_PU           0
1200
1201 #define STM_SYSCFG_EXTICR_PA            0
1202 #define STM_SYSCFG_EXTICR_PB            1
1203 #define STM_SYSCFG_EXTICR_PC            2
1204 #define STM_SYSCFG_EXTICR_PD            3
1205 #define STM_SYSCFG_EXTICR_PE            4
1206 #define STM_SYSCFG_EXTICR_PH            5
1207
1208 static inline void
1209 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1210         uint8_t reg = pin >> 2;
1211         uint8_t shift = (pin & 3) << 2;
1212         uint8_t val = 0;
1213
1214         /* Enable SYSCFG */
1215         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1216
1217         if (gpio == &stm_gpioa)
1218                 val = STM_SYSCFG_EXTICR_PA;
1219         else if (gpio == &stm_gpiob)
1220                 val = STM_SYSCFG_EXTICR_PB;
1221         else if (gpio == &stm_gpioc)
1222                 val = STM_SYSCFG_EXTICR_PC;
1223         else if (gpio == &stm_gpiod)
1224                 val = STM_SYSCFG_EXTICR_PD;
1225         else if (gpio == &stm_gpioe)
1226                 val = STM_SYSCFG_EXTICR_PE;
1227
1228         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1229 }
1230
1231 struct stm_dma_channel {
1232         vuint32_t       ccr;
1233         vuint32_t       cndtr;
1234         vvoid_t         cpar;
1235         vvoid_t         cmar;
1236         vuint32_t       reserved;
1237 };
1238
1239 #define STM_NUM_DMA     7
1240
1241 struct stm_dma {
1242         vuint32_t               isr;
1243         vuint32_t               ifcr;
1244         struct stm_dma_channel  channel[STM_NUM_DMA];
1245         uint8_t                 unused94[0xa8 - 0x94];
1246         vuint32_t               cselr;
1247 };
1248
1249 extern struct stm_dma stm_dma1;
1250 #define stm_dma1 (*(struct stm_dma *) 0x40020000)
1251
1252 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1253  */
1254
1255 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1256
1257 #define STM_DMA_ISR(index)              ((index) << 2)
1258 #define STM_DMA_ISR_MASK                        0xf
1259 #define STM_DMA_ISR_TEIF                        3
1260 #define STM_DMA_ISR_HTIF                        2
1261 #define STM_DMA_ISR_TCIF                        1
1262 #define STM_DMA_ISR_GIF                         0
1263
1264 #define STM_DMA_IFCR(index)             ((index) << 2)
1265 #define STM_DMA_IFCR_MASK                       0xf
1266 #define STM_DMA_IFCR_CTEIF                      3
1267 #define STM_DMA_IFCR_CHTIF                      2
1268 #define STM_DMA_IFCR_CTCIF                      1
1269 #define STM_DMA_IFCR_CGIF                       0
1270
1271 #define STM_DMA_CCR_MEM2MEM             (14)
1272
1273 #define STM_DMA_CCR_PL                  (12)
1274 #define  STM_DMA_CCR_PL_LOW                     (0)
1275 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1276 #define  STM_DMA_CCR_PL_HIGH                    (2)
1277 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1278 #define  STM_DMA_CCR_PL_MASK                    (3)
1279
1280 #define STM_DMA_CCR_MSIZE               (10)
1281 #define  STM_DMA_CCR_MSIZE_8                    (0)
1282 #define  STM_DMA_CCR_MSIZE_16                   (1)
1283 #define  STM_DMA_CCR_MSIZE_32                   (2)
1284 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1285
1286 #define STM_DMA_CCR_PSIZE               (8)
1287 #define  STM_DMA_CCR_PSIZE_8                    (0)
1288 #define  STM_DMA_CCR_PSIZE_16                   (1)
1289 #define  STM_DMA_CCR_PSIZE_32                   (2)
1290 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1291
1292 #define STM_DMA_CCR_MINC                (7)
1293 #define STM_DMA_CCR_PINC                (6)
1294 #define STM_DMA_CCR_CIRC                (5)
1295 #define STM_DMA_CCR_DIR                 (4)
1296 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1297 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1298 #define STM_DMA_CCR_TEIE                (3)
1299 #define STM_DMA_CCR_HTIE                (2)
1300 #define STM_DMA_CCR_TCIE                (1)
1301 #define STM_DMA_CCR_EN                  (0)
1302
1303 #define STM_DMA_CSELR_C7S_SPI2_TX               0x2
1304 #define STM_DMA_CSELR_C7S_USART2_TX             0x4
1305 #define STM_DMA_CSELR_C7S_LPUART1_TX            0x5
1306 #define STM_DMA_CSELR_C7S_I2C1_RX               0x6
1307 #define STM_DMA_CSELR_C7S_TIM2_CH2_TIM2_CH4     0x8
1308 #define STM_DMA_CSELR_C7S_USART4_TX             0xc
1309 #define STM_DMA_CSELR_C7S_USART5_TX             0xd
1310
1311 #define STM_DMA_CSELR_C6S_SPI2_RX               0x2
1312 #define STM_DMA_CSELR_C6S_USART2_RX             0x4
1313 #define STM_DMA_CSELR_C6S_LPUART1_RX            0x5
1314 #define STM_DMA_CSELR_C6S_I2C1_TX               0x6
1315 #define STM_DMA_CSELR_C6S_TIM3_TRIG             0xa
1316 #define STM_DMA_CSELR_C6S_USART4_RX             0xc
1317 #define STM_DMA_CSELR_C6S_USART5_RX             0xd
1318
1319 #define STM_DMA_CSELR_C5S_SPI2_TX               0x2
1320 #define STM_DMA_CSELR_C5S_USART1_RX             0x3
1321 #define STM_DMA_CSELR_C5S_USART2_RX             0x4
1322 #define STM_DMA_CSELR_C5S_I2C2_RX               0x7
1323 #define STM_DMA_CSELR_C5S_TIM2_CH1              0x8
1324 #define STM_DMA_CSELR_C5S_TIM3_CH1              0xa
1325 #define STM_DMA_CSELR_C5S_AES_IN                0xb
1326 #define STM_DMA_CSELR_C5S_I2C3_RX               0xe
1327
1328 #define STM_DMA_CSELR_C4S_SPI2_RX               0x2
1329 #define STM_DMA_CSELR_C4S_USART1_TX             0x3
1330 #define STM_DMA_CSELR_C4S_USART2_TX             0x4
1331 #define STM_DMA_CSELR_C4S_I2C2_TX               0x7
1332 #define STM_DMA_CSELR_C4S_TIM2_CH4              0x8
1333 #define STM_DMA_CSELR_C4S_I2C3_TX               0xe
1334 #define STM_DMA_CSELR_C4S_TIM7_UP               0xf
1335
1336 #define STM_DMA_CSELR_C3S_SPI1_TX               0x1
1337 #define STM_DMA_CSELR_C3S_USART1_RX             0x3
1338 #define STM_DMA_CSELR_C3S_LPUART1_RX            0x5
1339 #define STM_DMA_CSELR_C3S_I2C1_RX               0x6
1340 #define STM_DMA_CSELR_C3S_TIM2_CH2              0x8
1341 #define STM_DMA_CSELR_C3S_TIM4_CH4_TIM4_UP      0xa
1342 #define STM_DMA_CSELR_C3S_AES_OUT               0xb
1343 #define STM_DMA_CSELR_C3S_USART4_TX             0xc
1344 #define STM_DMA_CSELR_C3S_USART5_TX             0xd
1345 #define STM_DMA_CSELR_C3S_I2C3_RX               0xe
1346
1347 #define STM_DMA_CSELR_C2S_ADC                   0x0
1348 #define STM_DMA_CSELR_C2S_SPI1_RX               0x1
1349 #define STM_DMA_CSELR_C2S_USART1_TX             0x3
1350 #define STM_DMA_CSELR_C2S_LPUART1_TX            0x5
1351 #define STM_DMA_CSELR_C2S_I2C1_TX               0x6
1352 #define STM_DMA_CSELR_C2S_TIM2_UP               0x8
1353 #define STM_DMA_CSELR_C2S_TIM6_UP               0x9
1354 #define STM_DMA_CSELR_C2S_TIM3_CH3              0xa
1355 #define STM_DMA_CSELR_C2S_AES_OUT               0xb
1356 #define STM_DMA_CSELR_C2S_USART4_RX             0xc
1357 #define STM_DMA_CSELR_C2S_USART5_RX             0xd
1358 #define STM_DMA_CSELR_C2S_I2C3_TX               0xe
1359
1360 #define STM_DMA_CSELR_C1S_ADC                   0x0
1361 #define STM_DMA_CSELR_C1S_TIM2_CH3              0x8
1362 #define STM_DMA_CSELR_C1S_AES_IN                0xb
1363
1364 #define STM_NUM_SPI     1
1365
1366 struct stm_spi {
1367         vuint32_t       cr1;
1368         vuint32_t       cr2;
1369         vuint32_t       sr;
1370         vuint32_t       dr;
1371         vuint32_t       crcpr;
1372         vuint32_t       rxcrcr;
1373         vuint32_t       txcrcr;
1374 };
1375
1376 extern struct stm_spi stm_spi1;
1377 #define stm_spi1 (*(struct stm_spi *) 0x40013000)
1378
1379 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1380  */
1381
1382 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1383
1384 #define STM_SPI_CR1_BIDIMODE            15
1385 #define STM_SPI_CR1_BIDIOE              14
1386 #define STM_SPI_CR1_CRCEN               13
1387 #define STM_SPI_CR1_CRCNEXT             12
1388 #define STM_SPI_CR1_DFF                 11
1389 #define STM_SPI_CR1_RXONLY              10
1390 #define STM_SPI_CR1_SSM                 9
1391 #define STM_SPI_CR1_SSI                 8
1392 #define STM_SPI_CR1_LSBFIRST            7
1393 #define STM_SPI_CR1_SPE                 6
1394 #define STM_SPI_CR1_BR                  3
1395 #define  STM_SPI_CR1_BR_PCLK_2                  0
1396 #define  STM_SPI_CR1_BR_PCLK_4                  1
1397 #define  STM_SPI_CR1_BR_PCLK_8                  2
1398 #define  STM_SPI_CR1_BR_PCLK_16                 3
1399 #define  STM_SPI_CR1_BR_PCLK_32                 4
1400 #define  STM_SPI_CR1_BR_PCLK_64                 5
1401 #define  STM_SPI_CR1_BR_PCLK_128                6
1402 #define  STM_SPI_CR1_BR_PCLK_256                7
1403 #define  STM_SPI_CR1_BR_MASK                    7
1404
1405 #define STM_SPI_CR1_MSTR                2
1406 #define STM_SPI_CR1_CPOL                1
1407 #define STM_SPI_CR1_CPHA                0
1408
1409 #define STM_SPI_CR2_TXEIE       7
1410 #define STM_SPI_CR2_RXNEIE      6
1411 #define STM_SPI_CR2_ERRIE       5
1412 #define STM_SPI_CR2_SSOE        2
1413 #define STM_SPI_CR2_TXDMAEN     1
1414 #define STM_SPI_CR2_RXDMAEN     0
1415
1416 #define STM_SPI_SR_FRE          8
1417 #define STM_SPI_SR_BSY          7
1418 #define STM_SPI_SR_OVR          6
1419 #define STM_SPI_SR_MODF         5
1420 #define STM_SPI_SR_CRCERR       4
1421 #define STM_SPI_SR_UDR          3
1422 #define STM_SPI_SR_CHSIDE       2
1423 #define STM_SPI_SR_TXE          1
1424 #define STM_SPI_SR_RXNE         0
1425
1426 struct stm_adc {
1427         vuint32_t       isr;
1428         vuint32_t       ier;
1429         vuint32_t       cr;
1430         vuint32_t       cfgr1;
1431
1432         vuint32_t       cfgr2;
1433         vuint32_t       smpr;
1434         vuint32_t       r_18;
1435         vuint32_t       r_1c;
1436
1437         vuint32_t       tr;
1438         vuint32_t       r_24;
1439         vuint32_t       chselr;
1440         vuint32_t       r_2c;
1441
1442         vuint32_t       r_30[4];
1443
1444         vuint32_t       dr;
1445
1446         uint8_t         r_44[0xb4 - 0x44];
1447
1448         vuint32_t       calfact;
1449
1450         uint8_t         r_b8[0x308 - 0xb8];
1451         vuint32_t       ccr;
1452 };
1453
1454 extern struct stm_adc stm_adc;
1455 #define stm_adc (*(struct stm_adc *) 0x40012400)
1456
1457 #define STM_ADC_ISR_AWD         7
1458 #define STM_ADC_ISR_OVR         4
1459 #define STM_ADC_ISR_EOSEQ       3
1460 #define STM_ADC_ISR_EOC         2
1461 #define STM_ADC_ISR_EOSMP       1
1462 #define STM_ADC_ISR_ADRDY       0
1463
1464 #define STM_ADC_IER_AWDIE       7
1465 #define STM_ADC_IER_OVRIE       4
1466 #define STM_ADC_IER_EOSEQIE     3
1467 #define STM_ADC_IER_EOCIE       2
1468 #define STM_ADC_IER_EOSMPIE     1
1469 #define STM_ADC_IER_ADRDYIE     0
1470
1471 #define STM_ADC_CR_ADCAL        31
1472 #define STM_ADC_CR_ADVREGEN     28
1473 #define STM_ADC_CR_ADSTP        4
1474 #define STM_ADC_CR_ADSTART      2
1475 #define STM_ADC_CR_ADDIS        1
1476 #define STM_ADC_CR_ADEN         0
1477
1478 #define STM_ADC_CFGR1_AWDCH     26
1479 #define STM_ADC_CFGR1_AWDEN     23
1480 #define STM_ADC_CFGR1_AWDSGL    22
1481 #define STM_ADC_CFGR1_DISCEN    16
1482 #define STM_ADC_CFGR1_AUTOOFF   15
1483 #define STM_ADC_CFGR1_WAIT      14
1484 #define STM_ADC_CFGR1_CONT      13
1485 #define STM_ADC_CFGR1_OVRMOD    12
1486 #define STM_ADC_CFGR1_EXTEN     10
1487 #define  STM_ADC_CFGR1_EXTEN_DISABLE    0
1488 #define  STM_ADC_CFGR1_EXTEN_RISING     1
1489 #define  STM_ADC_CFGR1_EXTEN_FALLING    2
1490 #define  STM_ADC_CFGR1_EXTEN_BOTH       3
1491 #define  STM_ADC_CFGR1_EXTEN_MASK       3
1492
1493 #define STM_ADC_CFGR1_EXTSEL    6
1494 #define STM_ADC_CFGR1_ALIGN     5
1495 #define STM_ADC_CFGR1_RES       3
1496 #define  STM_ADC_CFGR1_RES_12           0
1497 #define  STM_ADC_CFGR1_RES_10           1
1498 #define  STM_ADC_CFGR1_RES_8            2
1499 #define  STM_ADC_CFGR1_RES_6            3
1500 #define  STM_ADC_CFGR1_RES_MASK         3
1501 #define STM_ADC_CFGR1_SCANDIR   2
1502 #define  STM_ADC_CFGR1_SCANDIR_UP       0
1503 #define  STM_ADC_CFGR1_SCANDIR_DOWN     1
1504 #define STM_ADC_CFGR1_DMACFG    1
1505 #define  STM_ADC_CFGR1_DMACFG_ONESHOT   0
1506 #define  STM_ADC_CFGR1_DMACFG_CIRCULAR  1
1507 #define STM_ADC_CFGR1_DMAEN     0
1508
1509 #define STM_ADC_CFGR2_CKMODE    30
1510 #define  STM_ADC_CFGR2_CKMODE_ADCCLK    0
1511 #define  STM_ADC_CFGR2_CKMODE_PCLK_2    1
1512 #define  STM_ADC_CFGR2_CKMODE_PCLK_4    2
1513 #define  STM_ADC_CFGR2_CKMODE_PCLK      3
1514
1515 #define STM_ADC_SMPR_SMP        0
1516 #define  STM_ADC_SMPR_SMP_1_5           0
1517 #define  STM_ADC_SMPR_SMP_7_5           1
1518 #define  STM_ADC_SMPR_SMP_13_5          2
1519 #define  STM_ADC_SMPR_SMP_28_5          3
1520 #define  STM_ADC_SMPR_SMP_41_5          4
1521 #define  STM_ADC_SMPR_SMP_55_5          5
1522 #define  STM_ADC_SMPR_SMP_71_5          6
1523 #define  STM_ADC_SMPR_SMP_239_5         7
1524
1525 #define STM_ADC_TR_HT           16
1526 #define STM_ADC_TR_LT           0
1527
1528 #define STM_ADC_CCR_LFMEN       25
1529 #define STM_ADC_CCR_VLCDEN      24
1530 #define STM_ADC_CCR_TSEN        23
1531 #define STM_ADC_CCR_VREFEN      22
1532 #define STM_ADC_CCR_PRESC       18
1533
1534 #define STM_ADC_CHSEL_TEMP      18
1535 #define STM_ADC_CHSEL_VREF      17
1536 #define STM_ADC_CHSEL_VLCD      16
1537
1538 struct stm_cal {
1539         uint16_t        ts_cal_cold;    /* 30°C */
1540         uint16_t        vrefint_cal;
1541         uint16_t        unused_c0;
1542         uint16_t        ts_cal_hot;     /* 110°C */
1543 };
1544
1545 extern struct stm_cal   stm_cal;
1546
1547 #define stm_temp_cal_cold       30
1548 #define stm_temp_cal_hot        110
1549
1550 struct stm_dbg_mcu {
1551         uint32_t        idcode;
1552 };
1553
1554 extern struct stm_dbg_mcu       stm_dbg_mcu;
1555
1556 static inline uint16_t
1557 stm_dev_id(void) {
1558         return stm_dbg_mcu.idcode & 0xfff;
1559 }
1560
1561 struct stm_flash_size {
1562         uint16_t        f_size;
1563 };
1564
1565 extern struct stm_flash_size    stm_flash_size_reg;
1566 #define stm_flash_size_reg      (*((struct stm_flash_size *) 0x1ff8007c))
1567
1568 /* Returns flash size in bytes */
1569 extern uint32_t
1570 stm_flash_size(void);
1571
1572 struct stm_unique_id {
1573         uint32_t        u_id0;
1574         uint32_t        u_id1;
1575         uint32_t        u_id2;
1576 };
1577
1578 extern struct stm_unique_id     stm_unique_id;
1579 #define stm_unique_id   (*((struct stm_unique_id) 0x1ff80050))
1580
1581 struct stm_device_id {
1582         uint32_t        device_id;
1583 };
1584
1585 extern struct stm_device_id     stm_device_id;
1586 #define stm_device_id   (*((struct stm_device_id) 0x40015800))
1587
1588 #define STM_NUM_I2C     2
1589
1590 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1591
1592 struct stm_i2c {
1593         vuint32_t       cr1;
1594         vuint32_t       cr2;
1595         vuint32_t       oar1;
1596         vuint32_t       oar2;
1597         vuint32_t       dr;
1598         vuint32_t       sr1;
1599         vuint32_t       sr2;
1600         vuint32_t       ccr;
1601         vuint32_t       trise;
1602 };
1603
1604 extern struct stm_i2c stm_i2c1, stm_i2c2;
1605
1606 #define STM_I2C_CR1_SWRST       15
1607 #define STM_I2C_CR1_ALERT       13
1608 #define STM_I2C_CR1_PEC         12
1609 #define STM_I2C_CR1_POS         11
1610 #define STM_I2C_CR1_ACK         10
1611 #define STM_I2C_CR1_STOP        9
1612 #define STM_I2C_CR1_START       8
1613 #define STM_I2C_CR1_NOSTRETCH   7
1614 #define STM_I2C_CR1_ENGC        6
1615 #define STM_I2C_CR1_ENPEC       5
1616 #define STM_I2C_CR1_ENARP       4
1617 #define STM_I2C_CR1_SMBTYPE     3
1618 #define STM_I2C_CR1_SMBUS       1
1619 #define STM_I2C_CR1_PE          0
1620
1621 #define STM_I2C_CR2_LAST        12
1622 #define STM_I2C_CR2_DMAEN       11
1623 #define STM_I2C_CR2_ITBUFEN     10
1624 #define STM_I2C_CR2_ITEVTEN     9
1625 #define STM_I2C_CR2_ITERREN     8
1626 #define STM_I2C_CR2_FREQ        0
1627 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1628 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1629 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1630 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1631 #define  STM_I2C_CR2_FREQ_24_MHZ        24
1632 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1633 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1634
1635 #define STM_I2C_SR1_SMBALERT    15
1636 #define STM_I2C_SR1_TIMEOUT     14
1637 #define STM_I2C_SR1_PECERR      12
1638 #define STM_I2C_SR1_OVR         11
1639 #define STM_I2C_SR1_AF          10
1640 #define STM_I2C_SR1_ARLO        9
1641 #define STM_I2C_SR1_BERR        8
1642 #define STM_I2C_SR1_TXE         7
1643 #define STM_I2C_SR1_RXNE        6
1644 #define STM_I2C_SR1_STOPF       4
1645 #define STM_I2C_SR1_ADD10       3
1646 #define STM_I2C_SR1_BTF         2
1647 #define STM_I2C_SR1_ADDR        1
1648 #define STM_I2C_SR1_SB          0
1649
1650 #define STM_I2C_SR2_PEC         8
1651 #define  STM_I2C_SR2_PEC_MASK   0xff00
1652 #define STM_I2C_SR2_DUALF       7
1653 #define STM_I2C_SR2_SMBHOST     6
1654 #define STM_I2C_SR2_SMBDEFAULT  5
1655 #define STM_I2C_SR2_GENCALL     4
1656 #define STM_I2C_SR2_TRA         2
1657 #define STM_I2C_SR2_BUSY        1
1658 #define STM_I2C_SR2_MSL         0
1659
1660 #define STM_I2C_CCR_FS          15
1661 #define STM_I2C_CCR_DUTY        14
1662 #define STM_I2C_CCR_CCR         0
1663 #define  STM_I2C_CCR_MASK       0x7ff
1664
1665 struct stm_tim234 {
1666         vuint32_t       cr1;
1667         vuint32_t       cr2;
1668         vuint32_t       smcr;
1669         vuint32_t       dier;
1670
1671         vuint32_t       sr;
1672         vuint32_t       egr;
1673         vuint32_t       ccmr1;
1674         vuint32_t       ccmr2;
1675
1676         vuint32_t       ccer;
1677         vuint32_t       cnt;
1678         vuint32_t       psc;
1679         vuint32_t       arr;
1680
1681         uint32_t        reserved_30;
1682         vuint32_t       ccr1;
1683         vuint32_t       ccr2;
1684         vuint32_t       ccr3;
1685
1686         vuint32_t       ccr4;
1687         uint32_t        reserved_44;
1688         vuint32_t       dcr;
1689         vuint32_t       dmar;
1690
1691         uint32_t        reserved_50;
1692 };
1693
1694 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1695
1696 #define STM_TIM234_CR1_CKD      8
1697 #define  STM_TIM234_CR1_CKD_1           0
1698 #define  STM_TIM234_CR1_CKD_2           1
1699 #define  STM_TIM234_CR1_CKD_4           2
1700 #define  STM_TIM234_CR1_CKD_MASK        3
1701 #define STM_TIM234_CR1_ARPE     7
1702 #define STM_TIM234_CR1_CMS      5
1703 #define  STM_TIM234_CR1_CMS_EDGE        0
1704 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1705 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1706 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1707 #define  STM_TIM234_CR1_CMS_MASK        3
1708 #define STM_TIM234_CR1_DIR      4
1709 #define  STM_TIM234_CR1_DIR_UP          0
1710 #define  STM_TIM234_CR1_DIR_DOWN        1
1711 #define STM_TIM234_CR1_OPM      3
1712 #define STM_TIM234_CR1_URS      2
1713 #define STM_TIM234_CR1_UDIS     1
1714 #define STM_TIM234_CR1_CEN      0
1715
1716 #define STM_TIM234_CR2_TI1S     7
1717 #define STM_TIM234_CR2_MMS      4
1718 #define  STM_TIM234_CR2_MMS_RESET               0
1719 #define  STM_TIM234_CR2_MMS_ENABLE              1
1720 #define  STM_TIM234_CR2_MMS_UPDATE              2
1721 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1722 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1723 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1724 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1725 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1726 #define  STM_TIM234_CR2_MMS_MASK                7
1727 #define STM_TIM234_CR2_CCDS     3
1728
1729 #define STM_TIM234_SMCR_ETP     15
1730 #define STM_TIM234_SMCR_ECE     14
1731 #define STM_TIM234_SMCR_ETPS    12
1732 #define  STM_TIM234_SMCR_ETPS_OFF               0
1733 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1734 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1735 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1736 #define  STM_TIM234_SMCR_ETPS_MASK              3
1737 #define STM_TIM234_SMCR_ETF     8
1738 #define  STM_TIM234_SMCR_ETF_NONE               0
1739 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1740 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1741 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1742 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1743 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1744 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1745 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1746 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1747 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1748 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1749 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1750 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1751 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1752 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1753 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1754 #define  STM_TIM234_SMCR_ETF_MASK               15
1755 #define STM_TIM234_SMCR_MSM     7
1756 #define STM_TIM234_SMCR_TS      4
1757 #define  STM_TIM234_SMCR_TS_ITR0                0
1758 #define  STM_TIM234_SMCR_TS_ITR1                1
1759 #define  STM_TIM234_SMCR_TS_ITR2                2
1760 #define  STM_TIM234_SMCR_TS_ITR3                3
1761 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1762 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1763 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1764 #define  STM_TIM234_SMCR_TS_ETRF                7
1765 #define  STM_TIM234_SMCR_TS_MASK                7
1766 #define STM_TIM234_SMCR_OCCS    3
1767 #define STM_TIM234_SMCR_SMS     0
1768 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1769 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1770 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1771 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1772 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1773 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1774 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1775 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1776 #define  STM_TIM234_SMCR_SMS_MASK               7
1777
1778 #define STM_TIM234_DIER_TDE             14
1779 #define STM_TIM234_DIER_CC4DE           12
1780 #define STM_TIM234_DIER_CC3DE           11
1781 #define STM_TIM234_DIER_CC2DE           10
1782 #define STM_TIM234_DIER_CC1DE           9
1783 #define STM_TIM234_DIER_UDE             8
1784
1785 #define STM_TIM234_DIER_TIE             6
1786 #define STM_TIM234_DIER_CC4IE           4
1787 #define STM_TIM234_DIER_CC3IE           3
1788 #define STM_TIM234_DIER_CC2IE           2
1789 #define STM_TIM234_DIER_CC1IE           1
1790 #define STM_TIM234_DIER_UIE             0
1791
1792 #define STM_TIM234_SR_CC4OF     12
1793 #define STM_TIM234_SR_CC3OF     11
1794 #define STM_TIM234_SR_CC2OF     10
1795 #define STM_TIM234_SR_CC1OF     9
1796 #define STM_TIM234_SR_TIF       6
1797 #define STM_TIM234_SR_CC4IF     4
1798 #define STM_TIM234_SR_CC3IF     3
1799 #define STM_TIM234_SR_CC2IF     2
1800 #define STM_TIM234_SR_CC1IF     1
1801 #define STM_TIM234_SR_UIF       0
1802
1803 #define STM_TIM234_EGR_TG       6
1804 #define STM_TIM234_EGR_CC4G     4
1805 #define STM_TIM234_EGR_CC3G     3
1806 #define STM_TIM234_EGR_CC2G     2
1807 #define STM_TIM234_EGR_CC1G     1
1808 #define STM_TIM234_EGR_UG       0
1809
1810 #define STM_TIM234_CCMR1_OC2CE  15
1811 #define STM_TIM234_CCMR1_OC2M   12
1812 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1813 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1814 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1815 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1816 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1817 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1818 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1819 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1820 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1821 #define STM_TIM234_CCMR1_OC2PE  11
1822 #define STM_TIM234_CCMR1_OC2FE  10
1823 #define STM_TIM234_CCMR1_CC2S   8
1824 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1825 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1826 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1827 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1828 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1829
1830 #define STM_TIM234_CCMR1_OC1CE  7
1831 #define STM_TIM234_CCMR1_OC1M   4
1832 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1833 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1834 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1835 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1836 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1837 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1838 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1839 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1840 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1841 #define STM_TIM234_CCMR1_OC1PE  3
1842 #define STM_TIM234_CCMR1_OC1FE  2
1843 #define STM_TIM234_CCMR1_CC1S   0
1844 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1845 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1846 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1847 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1848 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1849
1850 #define STM_TIM234_CCMR1_IC2F   12
1851 #define  STM_TIM234_CCMR1_IC2F_NONE                     0
1852 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_2               1
1853 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_4               2
1854 #define  STM_TIM234_CCMR1_IC2F_CK_INT_N_8               3
1855 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_6                4
1856 #define  STM_TIM234_CCMR1_IC2F_DTS_2_N_8                5
1857 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_6                6
1858 #define  STM_TIM234_CCMR1_IC2F_DTS_4_N_8                7
1859 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_6                8
1860 #define  STM_TIM234_CCMR1_IC2F_DTS_8_N_8                9
1861 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_5               10
1862 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_6               11
1863 #define  STM_TIM234_CCMR1_IC2F_DTS_16_N_8               12
1864 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_5               13
1865 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_6               14
1866 #define  STM_TIM234_CCMR1_IC2F_DTS_32_N_8               15
1867 #define STM_TIM234_CCMR1_IC2PSC 10
1868 #define  STM_TIM234_CCMR1_IC2PSC_NONE                   0
1869 #define  STM_TIM234_CCMR1_IC2PSC_2                      1
1870 #define  STM_TIM234_CCMR1_IC2PSC_4                      2
1871 #define  STM_TIM234_CCMR1_IC2PSC_8                      3
1872 #define STM_TIM234_CCMR1_IC1F   4
1873 #define  STM_TIM234_CCMR1_IC1F_NONE                     0
1874 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_2               1
1875 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_4               2
1876 #define  STM_TIM234_CCMR1_IC1F_CK_INT_N_8               3
1877 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_6                4
1878 #define  STM_TIM234_CCMR1_IC1F_DTS_2_N_8                5
1879 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_6                6
1880 #define  STM_TIM234_CCMR1_IC1F_DTS_4_N_8                7
1881 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_6                8
1882 #define  STM_TIM234_CCMR1_IC1F_DTS_8_N_8                9
1883 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_5               10
1884 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_6               11
1885 #define  STM_TIM234_CCMR1_IC1F_DTS_16_N_8               12
1886 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_5               13
1887 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_6               14
1888 #define  STM_TIM234_CCMR1_IC1F_DTS_32_N_8               15
1889 #define STM_TIM234_CCMR1_IC1PSC 2
1890 #define  STM_TIM234_CCMR1_IC1PSC_NONE                   0
1891 #define  STM_TIM234_CCMR1_IC1PSC_2                      1
1892 #define  STM_TIM234_CCMR1_IC1PSC_4                      2
1893 #define  STM_TIM234_CCMR1_IC1PSC_8                      3
1894
1895 #define STM_TIM234_CCMR2_OC4CE  15
1896 #define STM_TIM234_CCMR2_OC4M   12
1897 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1898 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1899 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1900 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1901 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1902 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1903 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1904 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1905 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1906 #define STM_TIM234_CCMR2_OC4PE  11
1907 #define STM_TIM234_CCMR2_OC4FE  10
1908 #define STM_TIM234_CCMR2_CC4S   8
1909 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1910 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1911 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1912 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1913 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1914
1915 #define STM_TIM234_CCMR2_OC3CE  7
1916 #define STM_TIM234_CCMR2_OC3M   4
1917 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1918 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1919 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1920 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1921 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1922 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1923 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1924 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1925 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1926 #define STM_TIM234_CCMR2_OC3PE  3
1927 #define STM_TIM234_CCMR2_OC3FE  2
1928 #define STM_TIM234_CCMR2_CC3S   0
1929 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1930 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1931 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1932 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1933 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1934
1935 #define STM_TIM234_CCER_CC4NP   15
1936 #define STM_TIM234_CCER_CC4P    13
1937 #define  STM_TIM234_CCER_CC4P_ACTIVE_HIGH       0
1938 #define  STM_TIM234_CCER_CC4P_ACTIVE_LOW        1
1939 #define STM_TIM234_CCER_CC4E    12
1940 #define STM_TIM234_CCER_CC3NP   11
1941 #define STM_TIM234_CCER_CC3P    9
1942 #define  STM_TIM234_CCER_CC3P_ACTIVE_HIGH       0
1943 #define  STM_TIM234_CCER_CC3P_ACTIVE_LOW        1
1944 #define STM_TIM234_CCER_CC3E    8
1945 #define STM_TIM234_CCER_CC2NP   7
1946 #define STM_TIM234_CCER_CC2P    5
1947 #define  STM_TIM234_CCER_CC2P_ACTIVE_HIGH       0
1948 #define  STM_TIM234_CCER_CC2P_ACTIVE_LOW        1
1949 #define STM_TIM234_CCER_CC2E    4
1950 #define STM_TIM234_CCER_CC1NP   3
1951 #define STM_TIM234_CCER_CC1P    1
1952 #define  STM_TIM234_CCER_CC1P_ACTIVE_HIGH       0
1953 #define  STM_TIM234_CCER_CC1P_ACTIVE_LOW        1
1954 #define STM_TIM234_CCER_CC1E    0
1955
1956 struct stm_exti {
1957         vuint32_t       imr;
1958         vuint32_t       emr;
1959         vuint32_t       rtsr;
1960         vuint32_t       ftsr;
1961
1962         vuint32_t       swier;
1963         vuint32_t       pr;
1964 };
1965
1966 extern struct stm_exti stm_exti;
1967 #define stm_exti (*(struct stm_exti *) 0x40010400)
1968
1969 struct stm_vrefint_cal {
1970         vuint16_t       vrefint_cal;
1971 };
1972
1973 extern struct stm_vrefint_cal stm_vrefint_cal;
1974 #define stm_vrefint_cal (*(struct stm_vrefint_cal *) 0x1ff80078)
1975
1976 /* Flash interface */
1977
1978 struct stm_flash {
1979         vuint32_t       acr;
1980         vuint32_t       pecr;
1981         vuint32_t       pdkeyr;
1982         vuint32_t       pekeyr;
1983
1984         vuint32_t       prgkeyr;
1985         vuint32_t       optkeyr;
1986         vuint32_t       sr;
1987         vuint32_t       obr;
1988
1989         vuint32_t       wrpr;
1990 };
1991
1992
1993 extern uint32_t __storage[], __storage_size[];
1994
1995 #define STM_FLASH_PAGE_SIZE     128
1996
1997 #define ao_storage_unit         128
1998 #define ao_storage_total        ((uintptr_t) __storage_size)
1999 #define ao_storage_block        STM_FLASH_PAGE_SIZE
2000 #define AO_STORAGE_ERASED_BYTE  0x00
2001
2002 extern struct stm_flash stm_flash;
2003
2004 #define STM_FLASH_ACR_PRE_READ  (6)
2005 #define STM_FLASH_ACR_DISAB_BUF (5)
2006 #define STM_FLASH_ACR_RUN_PD    (4)
2007 #define STM_FLASH_ACR_SLEEP_PD  (3)
2008 #define STM_FLASH_ACR_PRFEN     (1)
2009 #define STM_FLASH_ACR_LATENCY   (0)
2010
2011 #define STM_FLASH_PECR_NZDISABLE        23
2012 #define STM_FLASH_PECR_OBL_LAUNCH       18
2013 #define STM_FLASH_PECR_ERRIE            17
2014 #define STM_FLASH_PECR_EOPIE            16
2015 #define STM_FLASH_PECR_PARRALELLBANK    15
2016 #define STM_FLASH_PECR_FPRG             10
2017 #define STM_FLASH_PECR_ERASE            9
2018 #define STM_FLASH_PECR_FIX              8
2019 #define STM_FLASH_PECR_DATA             4
2020 #define STM_FLASH_PECR_PROG             3
2021 #define STM_FLASH_PECR_OPT_LOCK         2
2022 #define STM_FLASH_PECR_PRG_LOCK         1
2023 #define STM_FLASH_PECR_PE_LOCK          0
2024
2025 #define STM_FLASH_SR_OPTVERR            11
2026 #define STM_FLASH_SR_SIZERR             10
2027 #define STM_FLASH_SR_PGAERR             9
2028 #define STM_FLASH_SR_WRPERR             8
2029 #define STM_FLASH_SR_READY              3
2030 #define STM_FLASH_SR_ENDHV              2
2031 #define STM_FLASH_SR_EOP                1
2032 #define STM_FLASH_SR_BSY                0
2033
2034 #define STM_FLASH_OPTKEYR_OPTKEY1 0xFBEAD9C8
2035 #define STM_FLASH_OPTKEYR_OPTKEY2 0x24252627
2036
2037 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
2038 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
2039
2040 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
2041 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
2042
2043 #endif /* _STM32L0_H_ */