2 * Copyright © 2020 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
23 while (!(stm_usart1.isr & (1 << STM_USART_ISR_TXE)));
28 _ao_usart_tx_start(struct ao_stm_usart *usart)
30 if (!ao_fifo_empty(usart->tx_fifo)) {
31 #if HAS_SERIAL_SW_FLOW
32 if (usart->gpio_cts && ao_gpio_get(usart->gpio_cts, usart->pin_cts) == 1) {
33 ao_exti_enable(usart->gpio_cts, usart->pin_cts);
37 if (usart->reg->isr & (1 << STM_USART_ISR_TXE))
39 usart->tx_running = 1;
40 usart->reg->cr1 |= (1 << STM_USART_CR1_TXEIE) | (1 << STM_USART_CR1_TCIE);
41 ao_fifo_remove(usart->tx_fifo, usart->reg->tdr);
42 ao_wakeup(&usart->tx_fifo);
49 #if HAS_SERIAL_SW_FLOW
51 _ao_usart_cts(struct ao_stm_usart *usart)
53 if (_ao_usart_tx_start(usart))
54 ao_exti_disable(usart->gpio_cts, usart->pin_cts);
59 _ao_usart_rx(struct ao_stm_usart *usart, int is_stdin)
61 if (usart->reg->isr & (1 << STM_USART_ISR_RXNE)) {
62 usart->reg->icr = (1 << STM_USART_ICR_ORECF);
63 if (!ao_fifo_full(usart->rx_fifo)) {
64 ao_fifo_insert(usart->rx_fifo, usart->reg->rdr);
65 ao_wakeup(&usart->rx_fifo);
67 ao_wakeup(&ao_stdin_ready);
68 #if HAS_SERIAL_SW_FLOW
69 /* If the fifo is nearly full, turn off RTS and wait
70 * for it to drain a bunch
72 if (usart->gpio_rts && ao_fifo_mostly(usart->rx_fifo)) {
73 ao_gpio_set(usart->gpio_rts, usart->pin_rts, 1);
78 usart->reg->cr1 &= ~(1 << STM_USART_CR1_RXNEIE);
84 ao_usart_isr(struct ao_stm_usart *usart, int is_stdin)
86 _ao_usart_rx(usart, is_stdin);
88 if (!_ao_usart_tx_start(usart))
89 usart->reg->cr1 &= ~(1<< STM_USART_CR1_TXEIE);
91 if (usart->reg->isr & (1 << STM_USART_ISR_TC)) {
92 usart->tx_running = 0;
93 usart->reg->cr1 &= ~(1 << STM_USART_CR1_TCIE);
94 if (usart->draining) {
96 ao_wakeup(&usart->tx_fifo);
102 _ao_usart_pollchar(struct ao_stm_usart *usart)
106 if (ao_fifo_empty(usart->rx_fifo))
110 ao_fifo_remove(usart->rx_fifo,u);
111 if ((usart->reg->cr1 & (1 << STM_USART_CR1_RXNEIE)) == 0) {
112 if (ao_fifo_barely(usart->rx_fifo))
113 usart->reg->cr1 |= (1 << STM_USART_CR1_RXNEIE);
115 #if HAS_SERIAL_SW_FLOW
116 /* If we've cleared RTS, check if there's space now and turn it back on */
117 if (usart->gpio_rts && usart->rts == 0 && ao_fifo_barely(usart->rx_fifo)) {
118 ao_gpio_set(usart->gpio_rts, usart->pin_rts, 0);
128 ao_usart_getchar(struct ao_stm_usart *usart)
131 ao_arch_block_interrupts();
132 while ((c = _ao_usart_pollchar(usart)) == AO_READ_AGAIN)
133 ao_sleep(&usart->rx_fifo);
134 ao_arch_release_interrupts();
139 static inline uint8_t
140 _ao_usart_sleep_for(struct ao_stm_usart *usart, uint16_t timeout)
142 return ao_sleep_for(&usart->rx_fifo, timeout);
147 ao_usart_putchar(struct ao_stm_usart *usart, char c)
149 ao_arch_block_interrupts();
150 while (ao_fifo_full(usart->tx_fifo))
151 ao_sleep(&usart->tx_fifo);
152 ao_fifo_insert(usart->tx_fifo, c);
153 _ao_usart_tx_start(usart);
154 ao_arch_release_interrupts();
158 ao_usart_drain(struct ao_stm_usart *usart)
160 ao_arch_block_interrupts();
161 while (!ao_fifo_empty(usart->tx_fifo) || usart->tx_running) {
163 ao_sleep(&usart->tx_fifo);
165 ao_arch_release_interrupts();
168 static const uint32_t ao_usart_speeds[] = {
169 [AO_SERIAL_SPEED_4800] = 4800,
170 [AO_SERIAL_SPEED_9600] = 9600,
171 [AO_SERIAL_SPEED_19200] = 19200,
172 [AO_SERIAL_SPEED_57600] = 57600,
173 [AO_SERIAL_SPEED_115200] = 115200,
177 ao_usart_set_speed(struct ao_stm_usart *usart, uint8_t speed)
179 if (speed > AO_SERIAL_SPEED_115200)
181 usart->reg->brr = AO_PCLK2 / ao_usart_speeds[speed];
185 ao_usart_init(struct ao_stm_usart *usart, int hw_flow)
187 usart->reg->cr1 = ((0 << STM_USART_CR1_M1) |
188 (0 << STM_USART_CR1_EOBIE) |
189 (0 << STM_USART_CR1_RTOIE) |
190 (0 << STM_USART_CR1_DEAT) |
191 (0 << STM_USART_CR1_DEDT) |
192 (0 << STM_USART_CR1_OVER8) |
193 (0 << STM_USART_CR1_CMIE) |
194 (0 << STM_USART_CR1_MME) |
195 (0 << STM_USART_CR1_M0) |
196 (0 << STM_USART_CR1_WAKE) |
197 (0 << STM_USART_CR1_PCE) |
198 (0 << STM_USART_CR1_PS) |
199 (0 << STM_USART_CR1_PEIE) |
200 (0 << STM_USART_CR1_TXEIE) |
201 (0 << STM_USART_CR1_TCIE) |
202 (1 << STM_USART_CR1_RXNEIE) |
203 (0 << STM_USART_CR1_IDLEIE) |
204 (1 << STM_USART_CR1_TE) |
205 (1 << STM_USART_CR1_RE) |
206 (0 << STM_USART_CR1_UESM) |
207 (0 << STM_USART_CR1_UE));
209 usart->reg->cr2 = ((0 << STM_USART_CR2_ADD) |
210 (0 << STM_USART_CR2_RTOEN) |
211 (0 << STM_USART_CR2_ABRMOD) |
212 (0 << STM_USART_CR2_ABREN) |
213 (0 << STM_USART_CR2_MSBFIRST) |
214 (0 << STM_USART_CR2_DATAINV) |
215 (0 << STM_USART_CR2_TXINV) |
216 (0 << STM_USART_CR2_RXINV) |
217 (0 << STM_USART_CR2_SWAP) |
218 (0 << STM_USART_CR2_LINEN) |
219 (0 << STM_USART_CR2_STOP) |
220 (0 << STM_USART_CR2_CLKEN) |
221 (0 << STM_USART_CR2_CPOL) |
222 (0 << STM_USART_CR2_CHPA) |
223 (0 << STM_USART_CR2_LBCL) |
224 (0 << STM_USART_CR2_LBDIE) |
225 (0 << STM_USART_CR2_LBDL) |
226 (0 << STM_USART_CR2_ADDM7));
228 uint32_t cr3 = ((0 << STM_USART_CR3_WUFIE) |
229 (0 << STM_USART_CR3_WUS) |
230 (0 << STM_USART_CR3_SCARCNT) |
231 (0 << STM_USART_CR3_DEP) |
232 (0 << STM_USART_CR3_DEM) |
233 (0 << STM_USART_CR3_DDRE) |
234 (0 << STM_USART_CR3_OVRDIS) |
235 (0 << STM_USART_CR3_ONEBIT) |
236 (0 << STM_USART_CR3_CTIIE) |
237 (0 << STM_USART_CR3_CTSE) |
238 (0 << STM_USART_CR3_RTSE) |
239 (0 << STM_USART_CR3_DMAT) |
240 (0 << STM_USART_CR3_DMAR) |
241 (0 << STM_USART_CR3_SCEN) |
242 (0 << STM_USART_CR3_NACK) |
243 (0 << STM_USART_CR3_HDSEL) |
244 (0 << STM_USART_CR3_IRLP) |
245 (0 << STM_USART_CR3_IREN) |
246 (0 << STM_USART_CR3_EIE));
249 cr3 |= ((1 << STM_USART_CR3_CTSE) |
250 (1 << STM_USART_CR3_RTSE));
252 usart->reg->cr3 = cr3;
254 /* Pick a 9600 baud rate */
255 ao_usart_set_speed(usart, AO_SERIAL_SPEED_9600);
257 /* Enable the usart */
258 usart->reg->cr1 |= (1 << STM_USART_CR1_UE);
263 struct ao_stm_usart ao_stm_usart1;
265 void stm_usart1_isr(void) { ao_usart_isr(&ao_stm_usart1, USE_SERIAL_1_STDIN); }
268 ao_serial1_getchar(void)
270 return ao_usart_getchar(&ao_stm_usart1);
274 ao_serial1_putchar(char c)
276 ao_usart_putchar(&ao_stm_usart1, c);
280 _ao_serial1_pollchar(void)
282 return _ao_usart_pollchar(&ao_stm_usart1);
287 _ao_serial1_sleep_for(uint16_t timeout)
289 return _ao_usart_sleep_for(&ao_stm_usart1, timeout);
294 ao_serial1_drain(void)
296 ao_usart_drain(&ao_stm_usart1);
300 ao_serial1_set_speed(uint8_t speed)
302 ao_usart_drain(&ao_stm_usart1);
303 ao_usart_set_speed(&ao_stm_usart1, speed);
305 #endif /* HAS_SERIAL_1 */
309 struct ao_stm_usart ao_stm_usart2;
311 void stm_usart2_isr(void) { ao_usart_isr(&ao_stm_usart2, USE_SERIAL_2_STDIN); }
314 ao_serial2_getchar(void)
316 return ao_usart_getchar(&ao_stm_usart2);
320 ao_serial2_putchar(char c)
322 ao_usart_putchar(&ao_stm_usart2, c);
326 _ao_serial2_pollchar(void)
328 return _ao_usart_pollchar(&ao_stm_usart2);
333 _ao_serial2_sleep_for(uint16_t timeout)
335 return _ao_usart_sleep_for(&ao_stm_usart2, timeout);
340 ao_serial2_drain(void)
342 ao_usart_drain(&ao_stm_usart2);
346 ao_serial2_set_speed(uint8_t speed)
348 ao_usart_drain(&ao_stm_usart2);
349 ao_usart_set_speed(&ao_stm_usart2, speed);
352 #if USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
356 _ao_usart_cts(&ao_stm_usart2);
360 #endif /* HAS_SERIAL_2 */
362 #if HAS_SERIAL_SW_FLOW
364 ao_serial_set_sw_rts_cts(struct ao_stm_usart *usart,
366 struct stm_gpio *port_rts,
368 struct stm_gpio *port_cts,
371 /* Pull RTS low to note that there's space in the FIFO
373 ao_enable_output(port_rts, pin_rts, 0);
374 usart->gpio_rts = port_rts;
375 usart->pin_rts = pin_rts;
378 ao_exti_setup(port_cts, pin_cts, AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_MED, isr);
379 usart->gpio_cts = port_cts;
380 usart->pin_cts = pin_cts;
385 ao_serial_shutdown(void)
388 stm_rcc.apb2enr &= ~(1 << STM_RCC_APB2ENR_USART1EN);
391 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USART2EN);
410 # if SERIAL_2_PA2_PA3
411 ao_enable_port(&stm_gpioa);
412 stm_afr_set(&stm_gpioa, 2, STM_AFR_AF4);
413 stm_afr_set(&stm_gpioa, 3, STM_AFR_AF4);
414 # elif SERIAL_2_PA9_PA10
415 ao_enable_port(&stm_gpioa);
416 stm_afr_set(&stm_gpioa, 9, STM_AFR_AF4);
417 stm_afr_set(&stm_gpioa, 10, STM_AFR_AF4);
418 # elif SERIAL_2_PA14_PA15
419 ao_enable_port(&stm_gpioa);
420 stm_afr_set(&stm_gpioa, 14, STM_AFR_AF4);
421 stm_afr_set(&stm_gpioa, 15, STM_AFR_AF4);
422 # elif SERIAL_2_PB6_PB7
423 ao_enable_port(&stm_gpiob);
424 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF0);
425 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF0);
427 # error "No SERIAL_2 port configuration specified"
430 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USART2EN);
432 ao_stm_usart2.reg = &stm_usart2;
433 ao_usart_init(&ao_stm_usart2, USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW);
435 stm_nvic_set_enable(STM_ISR_USART2_POS);
436 stm_nvic_set_priority(STM_ISR_USART2_POS, 4);
437 # if USE_SERIAL_2_STDIN && !DELAY_SERIAL_2_STDIN
438 ao_add_stdio(_ao_serial2_pollchar,