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   1 /*
   2  * Copyright © 2020 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  */
  14
  15 #include <ao.h>
  16 #include <ao_exti.h>
  17 #include <ao_lpuart.h>
  18
  19 struct ao_stm_lpuart {
  20         struct ao_fifo          rx_fifo;
  21         struct ao_fifo          tx_fifo;
  22         struct stm_lpuart       *reg;
  23         uint8_t                 tx_running;
  24         uint8_t                 draining;
  25 #if HAS_SERIAL_SW_FLOW
  26         /* RTS - 0 if we have FIFO space, 1 if not
  27          * CTS - 0 if we can send, 0 if not
  28          */
  29         struct stm_gpio         *gpio_rts;
  30         struct stm_gpio         *gpio_cts;
  31         uint8_t                 pin_rts;
  32         uint8_t                 pin_cts;
  33         uint8_t                 rts;
  34 #endif
  35 };
  36
  37 static int
  38 _ao_lpuart_tx_start(struct ao_stm_lpuart *lpuart)
  39 {
  40         if (!ao_fifo_empty(lpuart->tx_fifo)) {
  41 #if HAS_LPUART_SW_FLOW
  42                 if (lpuart->gpio_cts && ao_gpio_get(lpuart->gpio_cts, lpuart->pin_cts) == 1) {
  43                         ao_exti_enable(lpuart->gpio_cts, lpuart->pin_cts);
  44                         return 0;
  45                 }
  46 #endif
  47                 if (lpuart->reg->isr & (1 << STM_LPUART_ISR_TXE))
  48                 {
  49                         lpuart->tx_running = 1;
  50                         lpuart->reg->cr1 |= (1 << STM_LPUART_CR1_TXEIE) | (1 << STM_LPUART_CR1_TCIE);
  51                         ao_fifo_remove(lpuart->tx_fifo, lpuart->reg->tdr);
  52                         ao_wakeup(&lpuart->tx_fifo);
  53                         return 1;
  54                 }
  55         }
  56         return 0;
  57 }
  58
  59 #if HAS_LPUART_SW_FLOW
  60 static void
  61 _ao_lpuart_cts(struct ao_stm_lpuart *lpuart)
  62 {
  63         if (_ao_lpuart_tx_start(lpuart))
  64                 ao_exti_disable(lpuart->gpio_cts, lpuart->pin_cts);
  65 }
  66 #endif
  67
  68 static void
  69 _ao_lpuart_rx(struct ao_stm_lpuart *lpuart, int is_stdin)
  70 {
  71         if (lpuart->reg->isr & (1 << STM_LPUART_ISR_RXNE)) {
  72                 lpuart->reg->icr = (1 << STM_LPUART_ICR_ORECF);
  73                 if (!ao_fifo_full(lpuart->rx_fifo)) {
  74                         ao_fifo_insert(lpuart->rx_fifo, lpuart->reg->rdr);
  75                         ao_wakeup(&lpuart->rx_fifo);
  76                         if (is_stdin)
  77                                 ao_wakeup(&ao_stdin_ready);
  78 #if HAS_LPUART_SW_FLOW
  79                         /* If the fifo is nearly full, turn off RTS and wait
  80                          * for it to drain a bunch
  81                          */
  82                         if (lpuart->gpio_rts && ao_fifo_mostly(lpuart->rx_fifo)) {
  83                                 ao_gpio_set(lpuart->gpio_rts, lpuart->pin_rts, 1);
  84                                 lpuart->rts = 0;
  85                         }
  86 #endif
  87                 } else {
  88                         lpuart->reg->cr1 &= ~(1UL << STM_LPUART_CR1_RXNEIE);
  89                 }
  90         }
  91 }
  92
  93 static void
  94 ao_lpuart_isr(struct ao_stm_lpuart *lpuart, int is_stdin)
  95 {
  96         _ao_lpuart_rx(lpuart, is_stdin);
  97
  98         if (!_ao_lpuart_tx_start(lpuart))
  99                 lpuart->reg->cr1 &= ~(1UL << STM_LPUART_CR1_TXEIE);
 100
 101         if (lpuart->reg->isr & (1 << STM_LPUART_ISR_TC)) {
 102                 lpuart->tx_running = 0;
 103                 lpuart->reg->cr1 &= ~(1UL << STM_LPUART_CR1_TCIE);
 104                 if (lpuart->draining) {
 105                         lpuart->draining = 0;
 106                         ao_wakeup(&lpuart->tx_fifo);
 107                 }
 108         }
 109 }
 110
 111 static int
 112 _ao_lpuart_pollchar(struct ao_stm_lpuart *lpuart)
 113 {
 114         int     c;
 115
 116         if (ao_fifo_empty(lpuart->rx_fifo))
 117                 c = AO_READ_AGAIN;
 118         else {
 119                 uint8_t u;
 120                 ao_fifo_remove(lpuart->rx_fifo,u);
 121                 if ((lpuart->reg->cr1 & (1 << STM_LPUART_CR1_RXNEIE)) == 0) {
 122                         if (ao_fifo_barely(lpuart->rx_fifo))
 123                                 lpuart->reg->cr1 |= (1 << STM_LPUART_CR1_RXNEIE);
 124                 }
 125 #if HAS_LPUART_SW_FLOW
 126                 /* If we've cleared RTS, check if there's space now and turn it back on */
 127                 if (lpuart->gpio_rts && lpuart->rts == 0 && ao_fifo_barely(lpuart->rx_fifo)) {
 128                         ao_gpio_set(lpuart->gpio_rts, lpuart->pin_rts, 0);
 129                         lpuart->rts = 1;
 130                 }
 131 #endif
 132                 c = u;
 133         }
 134         return c;
 135 }
 136
 137 static char
 138 ao_lpuart_getchar(struct ao_stm_lpuart *lpuart)
 139 {
 140         int c;
 141         ao_arch_block_interrupts();
 142         while ((c = _ao_lpuart_pollchar(lpuart)) == AO_READ_AGAIN)
 143                 ao_sleep(&lpuart->rx_fifo);
 144         ao_arch_release_interrupts();
 145         return (char) c;
 146 }
 147
 148 #if 0
 149 static inline uint8_t
 150 _ao_lpuart_sleep_for(struct ao_stm_lpuart *lpuart, uint16_t timeout)
 151 {
 152         return ao_sleep_for(&lpuart->rx_fifo, timeout);
 153 }
 154 #endif
 155
 156 static void
 157 ao_lpuart_putchar(struct ao_stm_lpuart *lpuart, char c)
 158 {
 159         ao_arch_block_interrupts();
 160         while (ao_fifo_full(lpuart->tx_fifo))
 161                 ao_sleep(&lpuart->tx_fifo);
 162         ao_fifo_insert(lpuart->tx_fifo, c);
 163         _ao_lpuart_tx_start(lpuart);
 164         ao_arch_release_interrupts();
 165 }
 166
 167 static void
 168 ao_lpuart_drain(struct ao_stm_lpuart *lpuart)
 169 {
 170         ao_arch_block_interrupts();
 171         while (!ao_fifo_empty(lpuart->tx_fifo) || lpuart->tx_running) {
 172                 lpuart->draining = 1;
 173                 ao_sleep(&lpuart->tx_fifo);
 174         }
 175         ao_arch_release_interrupts();
 176 }
 177
 178 extern const uint32_t ao_usart_speeds[];
 179
 180 static void
 181 ao_lpuart_set_speed(struct ao_stm_lpuart *lpuart, uint8_t speed)
 182 {
 183         if (speed > AO_SERIAL_SPEED_115200)
 184                 return;
 185         lpuart->reg->brr = 256 * AO_PCLK1 / ao_usart_speeds[speed];
 186 }
 187
 188 static void
 189 ao_lpuart_enable(struct ao_stm_lpuart *lpuart, int hw_flow)
 190 {
 191         lpuart->reg->cr1 = ((0 << STM_LPUART_CR1_M1) |
 192                            (0 << STM_LPUART_CR1_DEAT) |
 193                            (0 << STM_LPUART_CR1_DEDT) |
 194                            (0 << STM_LPUART_CR1_CMIE) |
 195                            (0 << STM_LPUART_CR1_MME) |
 196                            (0 << STM_LPUART_CR1_M0) |
 197                            (0 << STM_LPUART_CR1_WAKE) |
 198                            (0 << STM_LPUART_CR1_PCE) |
 199                            (0 << STM_LPUART_CR1_PS) |
 200                            (0 << STM_LPUART_CR1_PEIE) |
 201                            (0 << STM_LPUART_CR1_TXEIE) |
 202                            (0 << STM_LPUART_CR1_TCIE) |
 203                            (1 << STM_LPUART_CR1_RXNEIE) |
 204                            (0 << STM_LPUART_CR1_IDLEIE) |
 205                            (1 << STM_LPUART_CR1_TE) |
 206                            (1 << STM_LPUART_CR1_RE) |
 207                            (0 << STM_LPUART_CR1_UESM) |
 208                            (0 << STM_LPUART_CR1_UE));
 209
 210         lpuart->reg->cr2 = ((0 << STM_LPUART_CR2_ADD) |
 211                            (0 << STM_LPUART_CR2_MSBFIRST) |
 212                            (0 << STM_LPUART_CR2_DATAINV) |
 213                            (0 << STM_LPUART_CR2_TXINV) |
 214                            (0 << STM_LPUART_CR2_RXINV) |
 215                            (0 << STM_LPUART_CR2_SWAP) |
 216                            (0 << STM_LPUART_CR2_STOP) |
 217                            (0 << STM_LPUART_CR2_ADDM7));
 218
 219         uint32_t cr3 = ((0 << STM_LPUART_CR3_UCESM) |
 220                         (0 << STM_LPUART_CR3_WUFIE) |
 221                         (0 << STM_LPUART_CR3_WUS) |
 222                         (0 << STM_LPUART_CR3_DEP) |
 223                         (0 << STM_LPUART_CR3_DEM) |
 224                         (0 << STM_LPUART_CR3_DDRE) |
 225                         (0 << STM_LPUART_CR3_OVRDIS) |
 226                         (0 << STM_LPUART_CR3_CTSIE) |
 227                         (0 << STM_LPUART_CR3_CTSE) |
 228                         (0 << STM_LPUART_CR3_RTSE) |
 229                         (0 << STM_LPUART_CR3_DMAT) |
 230                         (0 << STM_LPUART_CR3_DMAR) |
 231                         (0 << STM_LPUART_CR3_HDSEL) |
 232                         (0 << STM_LPUART_CR3_EIE));
 233
 234         if (hw_flow)
 235                 cr3 |= ((1 << STM_LPUART_CR3_CTSE) |
 236                         (1 << STM_LPUART_CR3_RTSE));
 237
 238         lpuart->reg->cr3 = cr3;
 239
 240         /* Pick a 9600 baud rate */
 241         ao_lpuart_set_speed(lpuart, AO_SERIAL_SPEED_9600);
 242
 243         /* Enable the lpuart */
 244         lpuart->reg->cr1 |= (1 << STM_LPUART_CR1_UE);
 245 }
 246
 247 static void
 248 ao_lpuart_disable(struct ao_stm_lpuart *lpuart)
 249 {
 250         ao_lpuart_drain(lpuart);
 251         lpuart->reg->cr1 = 0;
 252 }
 253
 254 #if HAS_LPUART_1
 255
 256 struct ao_stm_lpuart ao_stm_lpuart1;
 257
 258 void stm_lpuart1_aes_isr(void) {
 259         ao_lpuart_isr(&ao_stm_lpuart1, USE_LPUART_1_STDIN);
 260 }
 261
 262 char
 263 ao_lpuart1_getchar(void)
 264 {
 265         return ao_lpuart_getchar(&ao_stm_lpuart1);
 266 }
 267
 268 void
 269 ao_lpuart1_putchar(char c)
 270 {
 271         ao_lpuart_putchar(&ao_stm_lpuart1, c);
 272 }
 273
 274 int
 275 _ao_lpuart1_pollchar(void)
 276 {
 277         return _ao_lpuart_pollchar(&ao_stm_lpuart1);
 278 }
 279
 280 void
 281 ao_lpuart1_drain(void)
 282 {
 283         ao_lpuart_drain(&ao_stm_lpuart1);
 284 }
 285
 286 void
 287 ao_lpuart1_set_speed(uint8_t speed)
 288 {
 289         ao_lpuart_drain(&ao_stm_lpuart1);
 290         ao_lpuart_set_speed(&ao_stm_lpuart1, speed);
 291 }
 292
 293 #endif  /* HAS_LPUART_1 */
 294
 295 #if HAS_LPUART_SW_FLOW
 296 static void
 297 ao_lpuart_set_sw_rts_cts(struct ao_stm_lpuart *lpuart,
 298                          void (*isr)(void),
 299                          struct stm_gpio *port_rts,
 300                          int pin_rts,
 301                          struct stm_gpio *port_cts,
 302                          int pin_cts)
 303 {
 304         /* Pull RTS low to note that there's space in the FIFO
 305          */
 306         ao_enable_output(port_rts, pin_rts, 0);
 307         lpuart->gpio_rts = port_rts;
 308         lpuart->pin_rts = pin_rts;
 309         lpuart->rts = 1;
 310
 311         ao_exti_setup(port_cts, pin_cts, AO_EXTI_MODE_FALLING|AO_EXTI_PRIORITY_MED, isr);
 312         lpuart->gpio_cts = port_cts;
 313         lpuart->pin_cts = pin_cts;
 314 }
 315 #endif
 316
 317 void
 318 ao_lpuart1_enable(void)
 319 {
 320         /*
 321          *      TX      RX
 322          *      PA1     PA0
 323          *      PA2     PA3
 324          *      PA4     PA3
 325          *      PA14    PA13
 326          *      PB6     PB7
 327          */
 328
 329 #ifdef HAS_LPUART_1
 330         /* Clock source defaults to PCLK1, so just leave it */
 331
 332 # if LPUART_1_PA0_PA1
 333         ao_enable_port(&stm_gpioa);
 334         stm_afr_set(&stm_gpioa, 0, STM_AFR_AF6);
 335         stm_afr_set(&stm_gpioa, 1, STM_AFR_AF6);
 336 # else
 337 #  error "No LPUART_1 port configuration specified"
 338 # endif
 339         /* Enable LPUART */
 340         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_LPUART1EN);
 341
 342         ao_stm_lpuart1.reg = &stm_lpuart1;
 343         ao_lpuart_enable(&ao_stm_lpuart1, USE_LPUART_1_FLOW && !USE_LPUART_1_SW_FLOW);
 344
 345         stm_nvic_set_enable(STM_ISR_LPUART1_AES_POS);
 346         stm_nvic_set_priority(STM_ISR_LPUART1_AES_POS, 4);
 347 # if USE_LPUART_1_STDIN && !DELAY_LPUART_1_STDIN
 348         ao_add_stdio(_ao_lpuart1_pollchar,
 349                      ao_lpuart1_putchar,
 350                      NULL);
 351 # endif
 352 #endif
 353 }
 354
 355 void
 356 ao_lpuart1_disable(void)
 357 {
 358         /* Stop LPUART */
 359         ao_lpuart_disable(&ao_stm_lpuart1);
 360
 361         /* Disable interrupts */
 362         stm_nvic_clear_enable(STM_ISR_LPUART1_AES_POS);
 363
 364         /* Remap pins to GPIO use */
 365 # if LPUART_1_PA0_PA1
 366         stm_moder_set(&stm_gpioa, 0, STM_MODER_INPUT);
 367         stm_moder_set(&stm_gpioa, 1, STM_MODER_OUTPUT);
 368 # else
 369 #  error "No LPUART_1 port configuration specified"
 370 # endif
 371
 372         /* Disable LPUART */
 373         stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_LPUART1EN);
 374 }
 375