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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20
  21 #define NUM_DMA 7
  22
  23 struct ao_dma_config {
  24         void            (*isr)(int index);
  25 };
  26
  27 uint8_t ao_dma_done[NUM_DMA];
  28
  29 static struct ao_dma_config ao_dma_config[NUM_DMA];
  30 static uint8_t ao_dma_allocated[NUM_DMA];
  31 static uint8_t ao_dma_mutex[NUM_DMA];
  32 static uint8_t ao_dma_active;
  33
  34 #ifndef LEAVE_DMA_ON
  35 static uint8_t ao_dma_active;
  36 #endif
  37
  38 #define ch_mask(id)     (STM_DMA_ISR_MASK << STM_DMA_ISR(id))
  39
  40 static void
  41 ao_dma_isr(uint8_t low_index, uint8_t high_index, uint32_t mask) {
  42         /* Get channel interrupt bits */
  43         uint32_t        isr = stm_dma1.isr & mask;
  44         uint8_t         index;
  45
  46         /* Ack them */
  47         stm_dma1.ifcr = isr;
  48         for (index = low_index; index <= high_index; index++) {
  49                 if (isr & ch_mask(index)) {
  50                         if (ao_dma_config[index].isr)
  51                                 (*ao_dma_config[index].isr)(index);
  52                         else {
  53                                 ao_dma_done[index] = 1;
  54                                 ao_wakeup(&ao_dma_done[index]);
  55                         }
  56                 }
  57         }
  58 }
  59
  60 void stm_dma1_channel1_isr(void) {
  61         ao_dma_isr(STM_DMA_INDEX(1),
  62                    STM_DMA_INDEX(1),
  63                    ch_mask(STM_DMA_INDEX(1)));
  64 }
  65
  66 void stm_dma1_channel3_2_isr(void) {
  67         ao_dma_isr(STM_DMA_INDEX(2),
  68                    STM_DMA_INDEX(3),
  69                    ch_mask(STM_DMA_INDEX(2)) |
  70                    ch_mask(STM_DMA_INDEX(3)));
  71 }
  72
  73 void stm_dma1_channel7_4_isr(void) {
  74         ao_dma_isr(STM_DMA_INDEX(4), STM_DMA_INDEX(7),
  75                    ch_mask(STM_DMA_INDEX(4)) |
  76                    ch_mask(STM_DMA_INDEX(5)) |
  77                    ch_mask(STM_DMA_INDEX(6)) |
  78                    ch_mask(STM_DMA_INDEX(7)));
  79 }
  80
  81 void
  82 ao_dma_set_transfer(uint8_t             index,
  83                     volatile void       *peripheral,
  84                     void                *memory,
  85                     uint16_t            count,
  86                     uint32_t            ccr)
  87 {
  88         if (ao_dma_allocated[index]) {
  89                 if (ao_dma_mutex[index])
  90                         ao_panic(AO_PANIC_DMA);
  91                 ao_dma_mutex[index] = 0xff;
  92         } else
  93                 ao_mutex_get(&ao_dma_mutex[index]);
  94 #ifndef LEAVE_DMA_ON
  95         ao_arch_critical(
  96                 if (ao_dma_active++ == 0)
  97                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
  98                 );
  99 #endif
 100         stm_dma1.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
 101         stm_dma1.channel[index].cndtr = count;
 102         stm_dma1.channel[index].cpar = peripheral;
 103         stm_dma1.channel[index].cmar = memory;
 104         ao_dma_config[index].isr = NULL;
 105 }
 106
 107 void
 108 ao_dma_set_isr(uint8_t index, void (*isr)(int))
 109 {
 110         ao_dma_config[index].isr = isr;
 111 }
 112
 113 void
 114 ao_dma_start(uint8_t index)
 115 {
 116         ao_dma_done[index] = 0;
 117         stm_dma1.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
 118 }
 119
 120 void
 121 ao_dma_done_transfer(uint8_t index)
 122 {
 123         stm_dma1.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
 124 #ifndef LEAVE_DMA_ON
 125         ao_arch_critical(
 126                 if (--ao_dma_active == 0)
 127                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
 128                 );
 129 #endif
 130         if (ao_dma_allocated[index])
 131                 ao_dma_mutex[index] = 0;
 132         else
 133                 ao_mutex_put(&ao_dma_mutex[index]);
 134 }
 135
 136 void
 137 ao_dma_alloc(uint8_t index, uint8_t cselr)
 138 {
 139         if (ao_dma_allocated[index])
 140                 ao_panic(AO_PANIC_DMA);
 141         ao_dma_allocated[index] = 1;
 142
 143         int shift = (index << 2);
 144         uint32_t mask = ~(0xf << shift);
 145         stm_dma1.cselr = (stm_dma1.cselr & mask) | (cselr << shift);
 146 }
 147
 148 #if DEBUG
 149 void
 150 ao_dma_dump_cmd(void)
 151 {
 152         int i;
 153
 154 #ifndef LEAVE_DMA_ON
 155         ao_arch_critical(
 156                 if (ao_dma_active++ == 0)
 157                         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
 158                 );
 159 #endif
 160         printf ("isr %08x ifcr%08x\n", stm_dma1.isr, stm_dma1.ifcr);
 161         for (i = 0; i < NUM_DMA; i++)
 162                 printf("%d: done %d allocated %d mutex %2d ccr %04x cndtr %04x cpar %08x cmar %08x isr %08x\n",
 163                        i,
 164                        ao_dma_done[i],
 165                        ao_dma_allocated[i],
 166                        ao_dma_mutex[i],
 167                        stm_dma1.channel[i].ccr,
 168                        stm_dma1.channel[i].cndtr,
 169                        stm_dma1.channel[i].cpar,
 170                        stm_dma1.channel[i].cmar,
 171                        ao_dma_config[i].isr);
 172 #ifndef LEAVE_DMA_ON
 173         ao_arch_critical(
 174                 if (--ao_dma_active == 0)
 175                         stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
 176                 );
 177 #endif
 178 }
 179
 180 static const struct ao_cmds ao_dma_cmds[] = {
 181         { ao_dma_dump_cmd,      "D\0Dump DMA status" },
 182         { 0, NULL }
 183 };
 184 #endif
 185
 186 void
 187 ao_dma_init(void)
 188 {
 189         int     index;
 190
 191 #ifdef LEAVE_DMA_ON
 192         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
 193 #endif
 194         for (index = 0; index < STM_NUM_DMA; index++) {
 195                 stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
 196                 stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index,
 197                                       AO_STM_NVIC_MED_PRIORITY);
 198                 ao_dma_allocated[index] = 0;
 199                 ao_dma_mutex[index] = 0;
 200         }
 201 #if DEBUG
 202         ao_cmd_register(&ao_dma_cmds[0]);
 203 #endif
 204 }