2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
28 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
38 /* Companion bus wants something no faster than 200kHz */
40 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
42 #define AO_SPI_CPOL_BIT 4
43 #define AO_SPI_CPHA_BIT 5
45 #define AO_SPI_CONFIG_1 0x00
46 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
48 #define AO_SPI_CONFIG_2 0x04
49 #define AO_SPI_1_CONFIG_PA12_PA13_PA14 AO_SPI_CONFIG_2
50 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
52 #define AO_SPI_CONFIG_3 0x08
53 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_3
55 #define AO_SPI_CONFIG_NONE 0x0c
57 #define AO_SPI_INDEX_MASK 0x01
58 #define AO_SPI_CONFIG_MASK 0x0c
60 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
61 #define AO_SPI_1_PA12_PA13_PA14 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA12_PA13_PA14)
62 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
64 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
65 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
67 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
68 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
69 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
70 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
71 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
73 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
74 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
75 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
76 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
77 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
80 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
83 ao_spi_get(uint8_t spi_index, uint32_t speed);
86 ao_spi_put(uint8_t spi_index);
89 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
92 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
95 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
98 ao_spi_start_bytes(uint8_t spi_index);
101 ao_spi_stop_bytes(uint8_t spi_index);
104 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
106 struct stm_spi *stm_spi = &stm_spi1;
109 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
112 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
117 static inline uint8_t
118 ao_spi_recv_byte(uint8_t spi_index)
120 struct stm_spi *stm_spi = &stm_spi1;
123 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
126 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
132 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
135 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
137 extern uint16_t ao_spi_speed[STM_NUM_SPI];
142 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
143 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
145 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
146 ao_spi_get(bus, speed); \
147 ao_spi_set_cs(reg,mask); \
150 static inline uint8_t
151 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
153 if (!ao_spi_try_get(bus, speed, task_id))
155 ao_spi_set_cs(reg, mask);
159 #define ao_spi_put_mask(reg,mask,bus) do { \
160 ao_spi_clr_cs(reg,mask); \
164 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
165 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
167 #define ao_enable_port(port) do { \
168 if ((port) == &stm_gpioa) \
169 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPAEN); \
170 else if ((port) == &stm_gpiob) \
171 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPBEN); \
172 else if ((port) == &stm_gpioc) \
173 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPCEN); \
174 else if ((port) == &stm_gpiod) \
175 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPDEN); \
176 else if ((port) == &stm_gpioe) \
177 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPEEN); \
178 else if ((port) == &stm_gpioh) \
179 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPHEN); \
182 #define ao_disable_port(port) do { \
183 if ((port) == &stm_gpioa) \
184 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPAEN); \
185 else if ((port) == &stm_gpiob) \
186 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPBEN); \
187 else if ((port) == &stm_gpioc) \
188 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPCEN); \
189 else if ((port) == &stm_gpiod) \
190 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPDEN); \
191 else if ((port) == &stm_gpioe) \
192 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPEEN); \
193 else if ((port) == &stm_gpioh) \
194 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPHEN); \
198 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
200 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
202 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
204 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
206 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
208 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
210 #define ao_enable_output(port,bit,v) do { \
211 ao_enable_port(port); \
212 ao_gpio_set(port, bit, v); \
213 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
216 #define ao_enable_output_mask(port,bits,mask) do { \
217 ao_enable_port(port); \
218 ao_gpio_set_mask(port, bits, mask); \
219 ao_set_output_mask(port, mask); \
222 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
223 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
225 #define ao_gpio_set_output_mode(port,bit,mode) \
226 stm_otyper_set(port, pin, mode)
228 #define ao_gpio_set_mode(port,bit,mode) do { \
229 if (mode == AO_EXTI_MODE_PULL_UP) \
230 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
231 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
232 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
234 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
237 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
238 if (mode == AO_EXTI_MODE_PULL_UP) \
239 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
240 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
241 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
243 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
246 #define ao_set_input(port, bit) do { \
247 stm_moder_set(port, bit, STM_MODER_INPUT); \
250 #define ao_set_output(port, bit, v) do { \
251 ao_gpio_set(port, bit, v); \
252 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
255 #define ao_set_output_mask(port, mask) do { \
256 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
259 #define ao_set_input_mask(port, mask) do { \
260 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
263 #define ao_enable_input(port,bit,mode) do { \
264 ao_enable_port(port); \
265 ao_set_input(port, bit); \
266 ao_gpio_set_mode(port, bit, mode); \
269 #define ao_enable_input_mask(port,mask,mode) do { \
270 ao_enable_port(port); \
271 ao_gpio_set_mode_mask(port, mask, mode); \
272 ao_set_input_mask(port, mask); \
275 #define _ao_enable_cs(port, bit) do { \
276 stm_gpio_set((port), bit, 1); \
277 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
280 #define ao_enable_cs(port,bit) do { \
281 ao_enable_port(port); \
282 _ao_enable_cs(port, bit); \
285 #define ao_spi_init_cs(port, mask) do { \
286 ao_enable_port(port); \
287 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
288 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
289 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
290 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
291 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
292 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
293 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
294 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
295 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
296 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
297 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
298 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
299 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
300 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
301 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
302 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
308 extern uint8_t ao_dma_done[STM_NUM_DMA];
311 ao_dma_set_transfer(uint8_t index,
312 volatile void *peripheral,
318 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
321 ao_dma_start(uint8_t index);
324 ao_dma_done_transfer(uint8_t index);
327 ao_dma_alloc(uint8_t index, uint8_t cselr);
335 ao_i2c_get(uint8_t i2c_index);
338 ao_i2c_start(uint8_t i2c_index, uint16_t address);
341 ao_i2c_put(uint8_t i2c_index);
344 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
347 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
352 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
353 #define HAS_SERIAL_SW_FLOW 1
355 #define HAS_SERIAL_SW_FLOW 0
358 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
359 #define HAS_SERIAL_HW_FLOW 1
361 #define HAS_SERIAL_HW_FLOW 0
364 /* ao_serial_stm.c */
365 struct ao_stm_usart {
366 struct ao_fifo rx_fifo;
367 struct ao_fifo tx_fifo;
368 struct stm_usart *reg;
371 #if HAS_SERIAL_SW_FLOW
372 /* RTS - 0 if we have FIFO space, 1 if not
373 * CTS - 0 if we can send, 0 if not
375 struct stm_gpio *gpio_rts;
376 struct stm_gpio *gpio_cts;
384 ao_debug_out(char c);
387 extern struct ao_stm_usart ao_stm_usart1;
391 extern struct ao_stm_usart ao_stm_usart2;
395 extern struct ao_stm_usart ao_stm_usart3;
398 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
400 typedef uint32_t ao_arch_irq_t;
403 ao_arch_block_interrupts(void) {
404 #ifdef AO_NONMASK_INTERRUPTS
405 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
412 ao_arch_release_interrupts(void) {
413 #ifdef AO_NONMASK_INTERRUPTS
414 asm("msr basepri,%0" : : "r" (0x0));
420 static inline uint32_t
421 ao_arch_irqsave(void) {
423 #ifdef AO_NONMASK_INTERRUPTS
424 asm("mrs %0,basepri" : "=r" (val));
426 asm("mrs %0,primask" : "=r" (val));
428 ao_arch_block_interrupts();
433 ao_arch_irqrestore(uint32_t basepri) {
434 #ifdef AO_NONMASK_INTERRUPTS
435 asm("msr basepri,%0" : : "r" (basepri));
437 asm("msr primask,%0" : : "r" (basepri));
442 ao_arch_memory_barrier(void) {
443 asm volatile("" ::: "memory");
447 ao_arch_irq_check(void) {
448 #ifdef AO_NONMASK_INTERRUPTS
450 asm("mrs %0,basepri" : "=r" (basepri));
452 ao_panic(AO_PANIC_IRQ);
455 asm("mrs %0,primask" : "=r" (primask));
456 if ((primask & 1) == 0)
457 ao_panic(AO_PANIC_IRQ);
463 ao_arch_init_stack(struct ao_task *task, void *start)
465 uint32_t *sp = &task->stack32[AO_STACK_SIZE >> 2];
466 uint32_t a = (uint32_t) start;
469 /* Return address (goes into LR) */
472 /* Clear register values r0-r7 */
480 /* PRIMASK with interrupts enabled */
486 static inline void ao_arch_save_regs(void) {
487 /* Save general registers */
488 asm("push {r0-r7,lr}\n");
495 asm("mrs r0,primask");
499 static inline void ao_arch_save_stack(void) {
501 asm("mov %0,sp" : "=&r" (sp) );
502 ao_cur_task->sp32 = (sp);
505 static inline void ao_arch_restore_stack(void) {
507 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
509 /* Restore PRIMASK */
511 asm("msr primask,r0");
515 asm("msr apsr_nczvq,r0");
517 /* Restore general registers */
518 asm("pop {r0-r7,pc}\n");
521 #ifndef HAS_SAMPLE_PROFILE
522 #define HAS_SAMPLE_PROFILE 0
526 #define HAS_ARCH_VALIDATE_CUR_STACK 1
529 ao_validate_cur_stack(void)
533 asm("mrs %0,psp" : "=&r" (psp));
535 psp <= ao_cur_task->stack &&
536 psp >= ao_cur_task->stack - 256)
537 ao_panic(AO_PANIC_STACK);
541 #if !HAS_SAMPLE_PROFILE
542 #define HAS_ARCH_START_SCHEDULER 1
544 static inline void ao_arch_start_scheduler(void) {
548 asm("mrs %0,msp" : "=&r" (sp));
549 asm("msr psp,%0" : : "r" (sp));
550 asm("mrs %0,control" : "=r" (control));
552 asm("msr control,%0" : : "r" (control));
557 #define ao_arch_isr_stack()
562 ao_arch_wait_interrupt(void) {
563 #ifdef AO_NONMASK_INTERRUPTS
565 "dsb\n" /* Serialize data */
566 "isb\n" /* Serialize instructions */
567 "cpsid i\n" /* Block all interrupts */
568 "msr basepri,%0\n" /* Allow all interrupts through basepri */
569 "wfi\n" /* Wait for an interrupt */
570 "cpsie i\n" /* Allow all interrupts */
571 "msr basepri,%1\n" /* Block interrupts through basepri */
572 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
575 ao_arch_release_interrupts();
576 ao_arch_block_interrupts();
580 #define ao_arch_critical(b) do { \
581 uint32_t __mask = ao_arch_irqsave(); \
582 do { b } while (0); \
583 ao_arch_irqrestore(__mask); \
588 #endif /* _AO_ARCH_FUNCS_H_ */