git.gag.com Git - fw/altos/blob - src/stm32f4/ao_timer.c

   1 /*
   2  * Copyright © 2018 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20 #include <ao_task.h>
  21
  22 #ifndef HAS_TICK
  23 #define HAS_TICK 1
  24 #endif
  25
  26 #if HAS_TICK || defined(AO_TIMER_HOOK)
  27
  28 #if HAS_TICK
  29 volatile AO_TICK_TYPE ao_tick_count;
  30
  31 AO_TICK_TYPE
  32 ao_time(void)
  33 {
  34         return ao_tick_count;
  35 }
  36 #endif
  37
  38 #if AO_DATA_ALL
  39 volatile uint8_t        ao_data_interval = 1;
  40 volatile uint8_t        ao_data_count;
  41 #endif
  42
  43 void stm_systick_isr(void)
  44 {
  45         ao_validate_cur_stack();
  46         if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
  47 #if HAS_TICK
  48                 ++ao_tick_count;
  49 #endif
  50 #if HAS_TASK_QUEUE
  51                 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
  52                         ao_task_check_alarm((uint16_t) ao_tick_count);
  53 #endif
  54 #if AO_DATA_ALL
  55                 if (++ao_data_count == ao_data_interval) {
  56                         ao_data_count = 0;
  57 #if HAS_FAKE_FLIGHT
  58                         if (ao_fake_flight_active)
  59                                 ao_fake_flight_poll();
  60                         else
  61 #endif
  62                                 ao_adc_poll();
  63 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
  64                         ao_wakeup((void *) &ao_data_count);
  65 #endif
  66                 }
  67 #endif
  68 #ifdef AO_TIMER_HOOK
  69                 AO_TIMER_HOOK;
  70 #endif
  71         }
  72 }
  73
  74 #if HAS_ADC
  75 void
  76 ao_timer_set_adc_interval(uint8_t interval)
  77 {
  78         ao_arch_critical(
  79                 ao_data_interval = interval;
  80                 ao_data_count = 0;
  81                 );
  82 }
  83 #endif
  84
  85 #define SYSTICK_RELOAD ((AO_SYSTICK / 8) / 100 - 1)
  86
  87 void
  88 ao_timer_init(void)
  89 {
  90         stm_systick.rvr = SYSTICK_RELOAD;
  91         stm_systick.cvr = 0;
  92         stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
  93                            (1 << STM_SYSTICK_CSR_TICKINT) |
  94                            (STM_SYSTICK_CSR_CLKSOURCE_AHB_8 << STM_SYSTICK_CSR_CLKSOURCE));
  95         stm_scb.shpr3 |= AO_STM_NVIC_CLOCK_PRIORITY << 24;
  96 }
  97
  98 #endif
  99
 100 void
 101 ao_clock_init(void)
 102 {
 103         uint32_t        cfgr;
 104         uint32_t        pllcfgr;
 105
 106         /* Switch to HSI while messing about */
 107         stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
 108         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
 109                 ao_arch_nop();
 110
 111         stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
 112                 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
 113
 114         /* wait for system to switch to HSI */
 115         while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
 116                (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
 117                 ao_arch_nop();
 118
 119         /* reset everything but the HSI selection and status */
 120         stm_rcc.cfgr &= (uint32_t)0x0000000f;
 121
 122         /* reset everything but HSI */
 123         stm_rcc.cr &= 0x0000ffff;
 124
 125         /* Disable and clear all interrupts */
 126         stm_rcc.cir = 0xffff0000;
 127
 128 #if AO_HSE
 129 #if AO_HSE_BYPASS
 130         stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
 131 #else
 132         stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
 133 #endif
 134         /* Enable HSE clock */
 135         stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
 136         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
 137                 asm("nop");
 138
 139 #define STM_RCC_CFGR_SWS_TARGET_CLOCK           (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
 140 #define STM_RCC_CFGR_SW_TARGET_CLOCK            (STM_RCC_CFGR_SW_HSE)
 141 #define STM_PLLSRC                              AO_HSE
 142 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK        (1 << STM_RCC_CFGR_PLLSRC)
 143 #else
 144 #define STM_RCC_CFGR_SWS_TARGET_CLOCK           (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
 145 #define STM_RCC_CFGR_SW_TARGET_CLOCK            (STM_RCC_CFGR_SW_HSI)
 146 #define STM_PLLSRC                              STM_HSI
 147 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK        (0 << STM_RCC_CFGR_PLLSRC)
 148 #endif
 149
 150 #if !AO_HSE || HAS_ADC || HAS_ADC_SINGLE
 151         /* Enable HSI RC clock 16MHz */
 152         stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
 153         while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
 154                 asm("nop");
 155 #endif
 156
 157         /* Set flash latency to tolerate SYSCLK */
 158
 159 #define FLASH_LATENCY   ((AO_SYSCLK - 1) / 25000000)
 160
 161         /* Enable icache, dcache and prefetch. Set latency */
 162         stm_flash.acr = ((1 << STM_FLASH_ACR_DCEN) |
 163                          (1 << STM_FLASH_ACR_ICEN) |
 164                          (1 << STM_FLASH_ACR_PRFTEN) |
 165                          (FLASH_LATENCY << STM_FLASH_ACR_LATENCY));
 166
 167         /* Enable power interface clock */
 168         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
 169
 170 #if AO_SYSCLK <= 64000000
 171 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 172 #elif AO_SYSCLK <= 84000000
 173 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_2
 174 #else
 175 #define VOS_SCALE_MODE  STM_PWR_CR_VOS_SCALE_MODE_1
 176 #endif
 177
 178         /* Set voltage scale mode */
 179         stm_pwr.cr = ((stm_pwr.cr & ~(STM_PWR_CR_VOS_SCALE_MODE_MASK)) |
 180                       (VOS_SCALE_MODE << STM_PWR_CR_VOS));
 181
 182         /* HCLK */
 183         cfgr = stm_rcc.cfgr;
 184         cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
 185         cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
 186         stm_rcc.cfgr = cfgr;
 187
 188         /* APB1 Prescaler = AO_APB1_PRESCALER */
 189         cfgr = stm_rcc.cfgr;
 190         cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
 191         cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
 192         stm_rcc.cfgr = cfgr;
 193
 194         /* APB2 Prescaler = AO_APB2_PRESCALER */
 195         cfgr = stm_rcc.cfgr;
 196         cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
 197         cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
 198         stm_rcc.cfgr = cfgr;
 199
 200         /* Disable the PLL */
 201         stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
 202         while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
 203                 asm("nop");
 204
 205         /* PLL1VCO */
 206         pllcfgr = stm_rcc.pllcfgr;
 207         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLM_MASK << STM_RCC_PLLCFGR_PLLM);
 208         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLN_MASK << STM_RCC_PLLCFGR_PLLN);
 209         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLP_MASK << STM_RCC_PLLCFGR_PLLP);
 210         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLQ_MASK << STM_RCC_PLLCFGR_PLLQ);
 211         pllcfgr &= ~(STM_RCC_PLLCFGR_PLLR_MASK << STM_RCC_PLLCFGR_PLLR);
 212
 213         pllcfgr |= (AO_PLL_M << STM_RCC_PLLCFGR_PLLM);
 214         pllcfgr |= (AO_PLL1_N << STM_RCC_PLLCFGR_PLLN);
 215 #if AO_PLL1_P
 216         pllcfgr |= (AO_PLL1_P << STM_RCC_PLLCFGR_PLLP);
 217 #endif
 218 #if AO_PLL1_Q
 219         pllcfgr |= (AO_PLL1_Q << STM_RCC_PLLCFGR_PLLQ);
 220 #endif
 221         /* PLL source */
 222         pllcfgr &= ~(1 << STM_RCC_PLLCFGR_PLLSRC);
 223 #if AO_HSI
 224         pllcfgr |= STM_RCC_PLLCFGR_PLLSRC_HSI;
 225 #endif
 226 #if AO_HSE
 227         pllcfgr |= STM_RCC_PLLCFGR_PLLSRC_HSE;
 228 #endif
 229         stm_rcc.pllcfgr = pllcfgr;
 230
 231         /* Enable the PLL and wait for it */
 232         stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
 233         while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
 234                 asm("nop");
 235
 236         /* Switch to the PLL for the system clock */
 237
 238         cfgr = stm_rcc.cfgr;
 239         cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
 240         cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
 241         stm_rcc.cfgr = cfgr;
 242         for (;;) {
 243                 uint32_t        c, part, mask, val;
 244
 245                 c = stm_rcc.cfgr;
 246                 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
 247                 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
 248                 part = c & mask;
 249                 if (part == val)
 250                         break;
 251         }
 252
 253 #if 0
 254         stm_rcc.apb2rstr = 0xffff;
 255         stm_rcc.apb1rstr = 0xffff;
 256         stm_rcc.ahbrstr = 0x3f;
 257         stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
 258         stm_rcc.apb2enr = 0;
 259         stm_rcc.apb1enr = 0;
 260         stm_rcc.ahbrstr = 0;
 261         stm_rcc.apb1rstr = 0;
 262         stm_rcc.apb2rstr = 0;
 263 #endif
 264
 265         /* Clear reset flags */
 266         stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
 267
 268 #if DEBUG_THE_CLOCK
 269         /* Output SYSCLK on PA8 for measurments */
 270
 271         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
 272
 273         stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
 274         stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
 275         stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
 276
 277         stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
 278         stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
 279 #endif
 280 }