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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #ifndef _STM32L_H_
  19 #define _STM32L_H_
  20
  21 #include <stdint.h>
  22
  23 typedef volatile uint32_t       vuint32_t;
  24
  25 struct stm_gpio {
  26         vuint32_t       moder;
  27         vuint32_t       otyper;
  28         vuint32_t       ospeedr;
  29         vuint32_t       pupdr;
  30
  31         vuint32_t       idr;
  32         vuint32_t       odr;
  33         vuint32_t       bsrr;
  34         vuint32_t       lckr;
  35
  36         vuint32_t       afrl;
  37         vuint32_t       afrh;
  38 };
  39
  40 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  41 #define STM_MODER_MASK                  3
  42 #define STM_MODER_INPUT                 0
  43 #define STM_MODER_OUTPUT                1
  44 #define STM_MODER_ALTERNATE             2
  45 #define STM_MODER_ANALOG                3
  46
  47 static inline void
  48 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  49         gpio->moder = ((gpio->moder &
  50                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  51                        value << STM_MODER_SHIFT(pin));
  52 }
  53
  54 static inline vuint32_t
  55 stm_moder_get(struct stm_gpio *gpio, int pin) {
  56         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  57 }
  58
  59 #define STM_OTYPER_SHIFT(pin)           (pin)
  60 #define STM_OTYPER_MASK                 1
  61 #define STM_OTYPER_PUSH_PULL            0
  62 #define STM_OTYPER_OPEN_DRAIN           1
  63
  64 static inline void
  65 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  66         gpio->otyper = ((gpio->otyper &
  67                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  68                         value << STM_OTYPER_SHIFT(pin));
  69 }
  70
  71 static inline vuint32_t
  72 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  73         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  74 }
  75
  76 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  77 #define STM_OSPEEDR_MASK                3
  78 #define STM_OSPEEDR_400kHz              0
  79 #define STM_OSPEEDR_2MHz                1
  80 #define STM_OSPEEDR_10MHz               2
  81 #define STM_OSPEEDR_40MHz               3
  82
  83 static inline void
  84 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  85         gpio->ospeedr = ((gpio->ospeedr &
  86                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  87                        value << STM_OSPEEDR_SHIFT(pin));
  88 }
  89
  90 static inline vuint32_t
  91 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  92         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  93 }
  94
  95 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  96 #define STM_PUPDR_MASK                  3
  97 #define STM_PUPDR_NONE                  0
  98 #define STM_PUPDR_PULL_UP               1
  99 #define STM_PUPDR_PULL_DOWN             2
 100 #define STM_PUPDR_RESERVED              3
 101
 102 static inline void
 103 stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
 104         gpio->pupdr = ((gpio->pupdr &
 105                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 106                        value << STM_PUPDR_SHIFT(pin));
 107 }
 108
 109 static inline vuint32_t
 110 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 111         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 112 }
 113
 114 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 115 #define STM_AFR_MASK                    0xf
 116 #define STM_AFR_NONE                    0
 117 #define STM_AFR_AF0                     0x0
 118 #define STM_AFR_AF1                     0x1
 119 #define STM_AFR_AF2                     0x2
 120 #define STM_AFR_AF3                     0x3
 121 #define STM_AFR_AF4                     0x4
 122 #define STM_AFR_AF5                     0x5
 123 #define STM_AFR_AF6                     0x6
 124 #define STM_AFR_AF7                     0x7
 125 #define STM_AFR_AF8                     0x8
 126 #define STM_AFR_AF9                     0x9
 127 #define STM_AFR_AF10                    0xa
 128 #define STM_AFR_AF11                    0xb
 129 #define STM_AFR_AF12                    0xc
 130 #define STM_AFR_AF13                    0xd
 131 #define STM_AFR_AF14                    0xe
 132 #define STM_AFR_AF15                    0xf
 133
 134 static inline void
 135 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 136         /*
 137          * Set alternate pin mode too
 138          */
 139         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 140         if (pin < 8)
 141                 gpio->afrl = ((gpio->afrl &
 142                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 143                               value << STM_AFR_SHIFT(pin));
 144         else {
 145                 pin -= 8;
 146                 gpio->afrh = ((gpio->afrh &
 147                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 148                               value << STM_AFR_SHIFT(pin));
 149         }
 150 }
 151
 152 static inline uint32_t
 153 stm_afr_get(struct stm_gpio *gpio, int pin) {
 154         if (pin < 8)
 155                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 156         else {
 157                 pin -= 8;
 158                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 159         }
 160 }
 161
 162 static inline void
 163 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 164         /* Use the bit set/reset register to do this atomically */
 165         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 166 }
 167
 168 static inline uint8_t
 169 stm_gpio_isset(struct stm_gpio *gpio, int pin) {
 170         return (gpio->idr >> pin) & 1;
 171 }
 172
 173 extern struct stm_gpio stm_gpioa;
 174 extern struct stm_gpio stm_gpiob;
 175 extern struct stm_gpio stm_gpioc;
 176 extern struct stm_gpio stm_gpiod;
 177 extern struct stm_gpio stm_gpioe;
 178 extern struct stm_gpio stm_gpioh;
 179
 180 struct stm_usart {
 181         vuint32_t       sr;     /* status register */
 182         vuint32_t       dr;     /* data register */
 183         vuint32_t       brr;    /* baud rate register */
 184         vuint32_t       cr1;    /* control register 1 */
 185
 186         vuint32_t       cr2;    /* control register 2 */
 187         vuint32_t       cr3;    /* control register 3 */
 188         vuint32_t       gtpr;   /* guard time and prescaler */
 189 };
 190
 191 extern struct stm_usart stm_usart1;
 192 extern struct stm_usart stm_usart2;
 193 extern struct stm_usart stm_usart3;
 194
 195 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 196 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 197 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 198 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 199 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 200 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 201 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 202 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 203 #define STM_USART_SR_FE         (1)     /* Framing error */
 204 #define STM_USART_SR_PE         (0)     /* Parity error */
 205
 206 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 207 #define STM_USART_CR1_UE        (13)    /* USART enable */
 208 #define STM_USART_CR1_M         (12)    /* Word length */
 209 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 210 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 211 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 212 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 213 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 214 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 215 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 216 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 217 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 218 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 219 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 220 #define STM_USART_CR1_SBK       (0)     /* Send break */
 221
 222 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 223 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 224 #define STM_USART_CR2_STOP_MASK 3
 225 #define STM_USART_CR2_STOP_1    0
 226 #define STM_USART_CR2_STOP_0_5  1
 227 #define STM_USART_CR2_STOP_2    2
 228 #define STM_USART_CR2_STOP_1_5  3
 229
 230 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 231 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 232 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 233 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 234 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 235 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 236 #define STM_USART_CR2_ADD       (0)
 237 #define STM_USART_CR2_ADD_MASK  0xf
 238
 239 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 240 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 241 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 242 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 243 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 244 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 245 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 246 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 247 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 248 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 249 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 250 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 251
 252 struct stm_tim {
 253 };
 254
 255 extern struct stm_tim stm_tim9;
 256 extern struct stm_tim stm_tim10;
 257 extern struct stm_tim stm_tim11;
 258
 259 /* Flash interface */
 260
 261 struct stm_flash {
 262         vuint32_t       acr;
 263         vuint32_t       pecr;
 264         vuint32_t       pdkeyr;
 265         vuint32_t       pekeyr;
 266
 267         vuint32_t       prgkeyr;
 268         vuint32_t       optkeyr;
 269         vuint32_t       sr;
 270         vuint32_t       obr;
 271
 272         vuint32_t       wrpr;
 273 };
 274
 275 extern struct stm_flash stm_flash;
 276
 277 #define STM_FLASH_ACR_RUN_PD    (4)
 278 #define STM_FLASH_ACR_SLEEP_PD  (3)
 279 #define STM_FLASH_ACR_ACC64     (2)
 280 #define STM_FLASH_ACR_PRFEN     (1)
 281 #define STM_FLASH_ACR_LATENCY   (0)
 282
 283 struct stm_rcc {
 284         vuint32_t       cr;
 285         vuint32_t       icscr;
 286         vuint32_t       cfgr;
 287         vuint32_t       cir;
 288
 289         vuint32_t       ahbrstr;
 290         vuint32_t       apb2rstr;
 291         vuint32_t       abp1rstr;
 292         vuint32_t       ahbenr;
 293
 294         vuint32_t       apb2enr;
 295         vuint32_t       apb1enr;
 296         vuint32_t       ahblenr;
 297         vuint32_t       apb2lpenr;
 298
 299         vuint32_t       apb1lpenr;
 300         vuint32_t       csr;
 301 };
 302
 303 extern struct stm_rcc stm_rcc;
 304
 305 #define STM_RCC_CR_RTCPRE       (29)
 306 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 307 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 308 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 309 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 310 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 311
 312 #define STM_RCC_CR_CSSON        (28)
 313 #define STM_RCC_CR_PLLRDY       (25)
 314 #define STM_RCC_CR_PLLON        (24)
 315 #define STM_RCC_CR_HSEBYP       (18)
 316 #define STM_RCC_CR_HSERDY       (17)
 317 #define STM_RCC_CR_HSEON        (16)
 318 #define STM_RCC_CR_MSIRDY       (9)
 319 #define STM_RCC_CR_MSION        (8)
 320 #define STM_RCC_CR_HSIRDY       (1)
 321 #define STM_RCC_CR_HSION        (0)
 322
 323 #define STM_RCC_CFGR_MCOPRE     (28)
 324 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 325 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 326 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 327 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 328 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 329 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 330
 331 #define STM_RCC_CFGR_MCOSEL     (24)
 332 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 333 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 334 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 335 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 336 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 337 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 338 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 339 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 340 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 341
 342 #define STM_RCC_CFGR_PLLDIV     (22)
 343 #define  STM_RCC_CFGR_PLLDIV_2          1
 344 #define  STM_RCC_CFGR_PLLDIV_3          2
 345 #define  STM_RCC_CFGR_PLLDIV_4          3
 346 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 347
 348 #define STM_RCC_CFGR_PLLMUL     (18)
 349 #define  STM_RCC_CFGR_PLLMUL_3          0
 350 #define  STM_RCC_CFGR_PLLMUL_4          1
 351 #define  STM_RCC_CFGR_PLLMUL_6          2
 352 #define  STM_RCC_CFGR_PLLMUL_8          3
 353 #define  STM_RCC_CFGR_PLLMUL_12         4
 354 #define  STM_RCC_CFGR_PLLMUL_16         5
 355 #define  STM_RCC_CFGR_PLLMUL_24         6
 356 #define  STM_RCC_CFGR_PLLMUL_32         7
 357 #define  STM_RCC_CFGR_PLLMUL_48         8
 358 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 359
 360 #define STM_RCC_CFGR_PLLSRC     (16)
 361
 362 #define STM_RCC_CFGR_PPRE2      (11)
 363 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 364 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 365 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 366 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 367 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 368 #define  STM_RCC_CFGR_PPRE2_MASK        7
 369
 370 #define STM_RCC_CFGR_PPRE1      (8)
 371 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 372 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 373 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 374 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 375 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 376 #define  STM_RCC_CFGR_PPRE1_MASK        7
 377
 378 #define STM_RCC_CFGR_HPRE       (4)
 379 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 380 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 381 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 382 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 383 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 384 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 385 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 386 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 387 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 388 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 389
 390 #define STM_RCC_CFGR_SWS        (2)
 391 #define  STM_RCC_CFGR_SWS_MSI           0
 392 #define  STM_RCC_CFGR_SWS_HSI           1
 393 #define  STM_RCC_CFGR_SWS_HSE           2
 394 #define  STM_RCC_CFGR_SWS_PLL           3
 395 #define  STM_RCC_CFGR_SWS_MASK          3
 396
 397 #define STM_RCC_CFGR_SW         (0)
 398 #define  STM_RCC_CFGR_SW_MSI            0
 399 #define  STM_RCC_CFGR_SW_HSI            1
 400 #define  STM_RCC_CFGR_SW_HSE            2
 401 #define  STM_RCC_CFGR_SW_PLL            3
 402 #define  STM_RCC_CFGR_SW_MASK           3
 403
 404 #define STM_RCC_AHBENR_DMA1EN           (24)
 405 #define STM_RCC_AHBENR_FLITFEN          (15)
 406 #define STM_RCC_AHBENR_CRCEN            (12)
 407 #define STM_RCC_AHBENR_GPIOHEN          (5)
 408 #define STM_RCC_AHBENR_GPIOEEN          (4)
 409 #define STM_RCC_AHBENR_GPIODEN          (3)
 410 #define STM_RCC_AHBENR_GPIOCEN          (2)
 411 #define STM_RCC_AHBENR_GPIOBEN          (1)
 412 #define STM_RCC_AHBENR_GPIOAEN          (0)
 413
 414 #define STM_RCC_APB2ENR_USART1EN        (14)
 415 #define STM_RCC_APB2ENR_SPI1EN          (12)
 416 #define STM_RCC_APB2ENR_ADC1EN          (9)
 417 #define STM_RCC_APB2ENR_TIM11EN         (4)
 418 #define STM_RCC_APB2ENR_TIM10EN         (3)
 419 #define STM_RCC_APB2ENR_TIM9EN          (2)
 420 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 421
 422 #define STM_RCC_APB1ENR_COMPEN          (31)
 423 #define STM_RCC_APB1ENR_DACEN           (29)
 424 #define STM_RCC_APB1ENR_PWREN           (28)
 425 #define STM_RCC_APB1ENR_USBEN           (23)
 426 #define STM_RCC_APB1ENR_I2C2EN          (22)
 427 #define STM_RCC_APB1ENR_I2C1EN          (21)
 428 #define STM_RCC_APB1ENR_USART3EN        (18)
 429 #define STM_RCC_APB1ENR_USART2EN        (17)
 430 #define STM_RCC_APB1ENR_SPI2EN          (14)
 431 #define STM_RCC_APB1ENR_WWDGEN          (11)
 432 #define STM_RCC_APB1ENR_LCDEN           (9)
 433 #define STM_RCC_APB1ENR_TIM7EN          (5)
 434 #define STM_RCC_APB1ENR_TIM6EN          (4)
 435 #define STM_RCC_APB1ENR_TIM4EN          (2)
 436 #define STM_RCC_APB1ENR_TIM3EN          (1)
 437 #define STM_RCC_APB1ENR_TIM2EN          (0)
 438
 439 #define STM_RCC_CSR_LPWRRSTF            (31)
 440 #define STM_RCC_CSR_WWDGRSTF            (30)
 441 #define STM_RCC_CSR_IWDGRSTF            (29)
 442 #define STM_RCC_CSR_SFTRSTF             (28)
 443 #define STM_RCC_CSR_PORRSTF             (27)
 444 #define STM_RCC_CSR_PINRSTF             (26)
 445 #define STM_RCC_CSR_OBLRSTF             (25)
 446 #define STM_RCC_CSR_RMVF                (24)
 447 #define STM_RCC_CSR_RTFRST              (23)
 448 #define STM_RCC_CSR_RTCEN               (22)
 449 #define STM_RCC_CSR_RTCSEL              (16)
 450
 451 #define  STM_RCC_CSR_RTCSEL_NONE                0
 452 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 453 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 454 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 455 #define  STM_RCC_CSR_RTCSEL_MASK                3
 456
 457 #define STM_RCC_CSR_LSEBYP              (10)
 458 #define STM_RCC_CSR_LSERDY              (9)
 459 #define STM_RCC_CSR_LSEON               (8)
 460 #define STM_RCC_CSR_LSIRDY              (1)
 461 #define STM_RCC_CSR_LSION               (0)
 462
 463 struct stm_pwr {
 464         vuint32_t       cr;
 465         vuint32_t       csr;
 466 };
 467
 468 extern struct stm_pwr stm_pwr;
 469
 470 #define STM_PWR_CR_LPRUN        (14)
 471
 472 #define STM_PWR_CR_VOS          (11)
 473 #define  STM_PWR_CR_VOS_1_8             1
 474 #define  STM_PWR_CR_VOS_1_5             2
 475 #define  STM_PWR_CR_VOS_1_2             3
 476 #define  STM_PWR_CR_VOS_MASK            3
 477
 478 #define STM_PWR_CR_FWU          (10)
 479 #define STM_PWR_CR_ULP          (9)
 480 #define STM_PWR_CR_DBP          (8)
 481
 482 #define STM_PWR_CR_PLS          (5)
 483 #define  STM_PWR_CR_PLS_1_9     0
 484 #define  STM_PWR_CR_PLS_2_1     1
 485 #define  STM_PWR_CR_PLS_2_3     2
 486 #define  STM_PWR_CR_PLS_2_5     3
 487 #define  STM_PWR_CR_PLS_2_7     4
 488 #define  STM_PWR_CR_PLS_2_9     5
 489 #define  STM_PWR_CR_PLS_3_1     6
 490 #define  STM_PWR_CR_PLS_EXT     7
 491 #define  STM_PWR_CR_PLS_MASK    7
 492
 493 #define STM_PWR_CR_PVDE         (4)
 494 #define STM_PWR_CR_CSBF         (3)
 495 #define STM_PWR_CR_CWUF         (2)
 496 #define STM_PWR_CR_PDDS         (1)
 497 #define STM_PWR_CR_LPSDSR       (0)
 498
 499 #define STM_PWR_CSR_EWUP3       (10)
 500 #define STM_PWR_CSR_EWUP2       (9)
 501 #define STM_PWR_CSR_EWUP1       (8)
 502 #define STM_PWR_CSR_REGLPF      (5)
 503 #define STM_PWR_CSR_VOSF        (4)
 504 #define STM_PWR_CSR_VREFINTRDYF (3)
 505 #define STM_PWR_CSR_PVDO        (2)
 506 #define STM_PWR_CSR_SBF         (1)
 507 #define STM_PWR_CSR_WUF         (0)
 508
 509 struct stm_tim67 {
 510         vuint32_t       cr1;
 511         vuint32_t       cr2;
 512         uint32_t        _unused_08;
 513         vuint32_t       dier;
 514
 515         vuint32_t       sr;
 516         vuint32_t       egr;
 517         uint32_t        _unused_18;
 518         uint32_t        _unused_1c;
 519
 520         uint32_t        _unused_20;
 521         vuint32_t       cnt;
 522         vuint32_t       psc;
 523         vuint32_t       arr;
 524 };
 525
 526 extern struct stm_tim67 stm_tim6;
 527
 528 #define STM_TIM67_CR1_ARPE      (7)
 529 #define STM_TIM67_CR1_OPM       (3)
 530 #define STM_TIM67_CR1_URS       (2)
 531 #define STM_TIM67_CR1_UDIS      (1)
 532 #define STM_TIM67_CR1_CEN       (0)
 533
 534 #define STM_TIM67_CR2_MMS       (4)
 535 #define  STM_TIM67_CR2_MMS_RESET        0
 536 #define  STM_TIM67_CR2_MMS_ENABLE       1
 537 #define  STM_TIM67_CR2_MMS_UPDATE       2
 538 #define  STM_TIM67_CR2_MMS_MASK         7
 539
 540 #define STM_TIM67_DIER_UDE      (8)
 541 #define STM_TIM67_DIER_UIE      (0)
 542
 543 #define STM_TIM67_SR_UIF        (0)
 544
 545 #define STM_TIM67_EGR_UG        (0)
 546
 547 struct stm_lcd {
 548         vuint32_t       cr;
 549         vuint32_t       fcr;
 550         vuint32_t       sr;
 551         vuint32_t       clr;
 552         uint32_t        unused_0x10;
 553         vuint32_t       ram[8*2];
 554 };
 555
 556 extern struct stm_lcd stm_lcd;
 557
 558 #define STM_LCD_CR_MUX_SEG              (7)
 559
 560 #define STM_LCD_CR_BIAS                 (5)
 561 #define  STM_LCD_CR_BIAS_1_4            0
 562 #define  STM_LCD_CR_BIAS_1_2            1
 563 #define  STM_LCD_CR_BIAS_1_3            2
 564 #define  STM_LCD_CR_BIAS_MASK           3
 565
 566 #define STM_LCD_CR_DUTY                 (2)
 567 #define  STM_LCD_CR_DUTY_STATIC         0
 568 #define  STM_LCD_CR_DUTY_1_2            1
 569 #define  STM_LCD_CR_DUTY_1_3            2
 570 #define  STM_LCD_CR_DUTY_1_4            3
 571 #define  STM_LCD_CR_DUTY_1_8            4
 572 #define  STM_LCD_CR_DUTY_MASK           7
 573
 574 #define STM_LCD_CR_VSEL                 (1)
 575 #define STM_LCD_CR_LCDEN                (0)
 576
 577 #define STM_LCD_FCR_PS                  (22)
 578 #define  STM_LCD_FCR_PS_1               0x0
 579 #define  STM_LCD_FCR_PS_2               0x1
 580 #define  STM_LCD_FCR_PS_4               0x2
 581 #define  STM_LCD_FCR_PS_8               0x3
 582 #define  STM_LCD_FCR_PS_16              0x4
 583 #define  STM_LCD_FCR_PS_32              0x5
 584 #define  STM_LCD_FCR_PS_64              0x6
 585 #define  STM_LCD_FCR_PS_128             0x7
 586 #define  STM_LCD_FCR_PS_256             0x8
 587 #define  STM_LCD_FCR_PS_512             0x9
 588 #define  STM_LCD_FCR_PS_1024            0xa
 589 #define  STM_LCD_FCR_PS_2048            0xb
 590 #define  STM_LCD_FCR_PS_4096            0xc
 591 #define  STM_LCD_FCR_PS_8192            0xd
 592 #define  STM_LCD_FCR_PS_16384           0xe
 593 #define  STM_LCD_FCR_PS_32768           0xf
 594 #define  STM_LCD_FCR_PS_MASK            0xf
 595
 596 #define STM_LCD_FCR_DIV                 (18)
 597 #define STM_LCD_FCR_DIV_16              0x0
 598 #define STM_LCD_FCR_DIV_17              0x1
 599 #define STM_LCD_FCR_DIV_18              0x2
 600 #define STM_LCD_FCR_DIV_19              0x3
 601 #define STM_LCD_FCR_DIV_20              0x4
 602 #define STM_LCD_FCR_DIV_21              0x5
 603 #define STM_LCD_FCR_DIV_22              0x6
 604 #define STM_LCD_FCR_DIV_23              0x7
 605 #define STM_LCD_FCR_DIV_24              0x8
 606 #define STM_LCD_FCR_DIV_25              0x9
 607 #define STM_LCD_FCR_DIV_26              0xa
 608 #define STM_LCD_FCR_DIV_27              0xb
 609 #define STM_LCD_FCR_DIV_28              0xc
 610 #define STM_LCD_FCR_DIV_29              0xd
 611 #define STM_LCD_FCR_DIV_30              0xe
 612 #define STM_LCD_FCR_DIV_31              0xf
 613 #define STM_LCD_FCR_DIV_MASK            0xf
 614
 615 #define STM_LCD_FCR_BLINK               (16)
 616 #define  STM_LCD_FCR_BLINK_DISABLE              0
 617 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 618 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 619 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 620 #define  STM_LCD_FCR_BLINK_MASK                 3
 621
 622 #define STM_LCD_FCR_BLINKF              (13)
 623 #define  STM_LCD_FCR_BLINKF_8                   0
 624 #define  STM_LCD_FCR_BLINKF_16                  1
 625 #define  STM_LCD_FCR_BLINKF_32                  2
 626 #define  STM_LCD_FCR_BLINKF_64                  3
 627 #define  STM_LCD_FCR_BLINKF_128                 4
 628 #define  STM_LCD_FCR_BLINKF_256                 5
 629 #define  STM_LCD_FCR_BLINKF_512                 6
 630 #define  STM_LCD_FCR_BLINKF_1024                7
 631 #define  STM_LCD_FCR_BLINKF_MASK                7
 632
 633 #define STM_LCD_FCR_CC                  (10)
 634 #define  STM_LCD_FCR_CC_MASK                    7
 635
 636 #define STM_LCD_FCR_DEAD                (7)
 637 #define  STM_LCD_FCR_DEAD_MASK                  7
 638
 639 #define STM_LCD_FCR_PON                 (4)
 640 #define  STM_LCD_FCR_PON_MASK                   7
 641
 642 #define STM_LCD_FCR_UDDIE               (3)
 643 #define STM_LCD_FCR_SOFIE               (1)
 644 #define STM_LCD_FCR_HD                  (0)
 645
 646 #define STM_LCD_SR_FCRSF                (5)
 647 #define STM_LCD_SR_RDY                  (4)
 648 #define STM_LCD_SR_UDD                  (3)
 649 #define STM_LCD_SR_UDR                  (2)
 650 #define STM_LCD_SR_SOF                  (1)
 651 #define STM_LCD_SR_ENS                  (0)
 652
 653 #define STM_LCD_CLR_UDDC                (3)
 654 #define STM_LCD_CLR_SOFC                (1)
 655
 656 struct stm_nvic {
 657         vuint32_t       iser[3];        /* 0x000 */
 658
 659         uint8_t         _unused00c[0x080 - 0x00c];
 660
 661         vuint32_t       icer[3];        /* 0x080 */
 662
 663         uint8_t         _unused08c[0x100 - 0x08c];
 664
 665         vuint32_t       ispr[3];        /* 0x100 */
 666
 667         uint8_t         _unused10c[0x180 - 0x10c];
 668
 669         vuint32_t       icpr[3];        /* 0x180 */
 670
 671         uint8_t         _unused18c[0x200 - 0x18c];
 672
 673         vuint32_t       iabr[3];        /* 0x200 */
 674
 675         uint8_t         _unused20c[0x300 - 0x20c];
 676
 677         vuint32_t       ipr[21];        /* 0x300 */
 678
 679         uint8_t         _unused324[0xe00 - 0x324];
 680
 681         vuint32_t       stir;           /* 0xe00 */
 682 };
 683
 684 extern struct stm_nvic stm_nvic;
 685
 686 #define IRQ_REG(irq)    ((irq) >> 5)
 687 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 688 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 689 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 690
 691 static inline void
 692 stm_nvic_set_enable(int irq) {
 693         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 694 }
 695
 696 static inline void
 697 stm_nvic_clear_enable(int irq) {
 698         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 699 }
 700
 701 static inline int
 702 stm_nvic_enabled(int irq) {
 703         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 704 }
 705
 706 static inline void
 707 stm_nvic_set_pending(int irq) {
 708         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 709 }
 710
 711 static inline void
 712 stm_nvic_clear_pending(int irq) {
 713         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 714 }
 715
 716 static inline int
 717 stm_nvic_pending(int irq) {
 718         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 719 }
 720
 721 static inline int
 722 stm_nvic_active(int irq) {
 723         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 724 }
 725
 726 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 727 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 728 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 729
 730 static inline void
 731 stm_nvic_set_priority(int irq, uint8_t prio) {
 732         int             n = IRQ_PRIO_REG(irq);
 733         uint32_t        v;
 734
 735         v = stm_nvic.ipr[n];
 736         v &= ~IRQ_PRIO_MASK(irq);
 737         v |= (prio) << IRQ_PRIO_BIT(irq);
 738         stm_nvic.ipr[n] = v;
 739 }
 740
 741 static inline uint8_t
 742 stm_nvic_get_priority(int irq) {
 743         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 744 }
 745
 746 #define isr(name) void stm_ ## name ## _isr(void);
 747
 748 isr(nmi)
 749 isr(hardfault)
 750 isr(memmanage)
 751 isr(busfault)
 752 isr(usagefault)
 753 isr(svc)
 754 isr(debugmon)
 755 isr(pendsv)
 756 isr(systick)
 757 isr(wwdg)
 758 isr(pvd)
 759 isr(tamper_stamp)
 760 isr(rtc_wkup)
 761 isr(flash)
 762 isr(rcc)
 763 isr(exti0)
 764 isr(exti1)
 765 isr(exti2)
 766 isr(exti3)
 767 isr(exti4)
 768 isr(dma1_channel1)
 769 isr(dma1_channel2)
 770 isr(dma1_channel3)
 771 isr(dma1_channel4)
 772 isr(dma1_channel5)
 773 isr(dma1_channel6)
 774 isr(dma1_channel7)
 775 isr(adc1)
 776 isr(usb_hp)
 777 isr(usb_lp)
 778 isr(dac)
 779 isr(comp)
 780 isr(exti9_5)
 781 isr(lcd)
 782 isr(tim9)
 783 isr(tim10)
 784 isr(tim11)
 785 isr(tim2)
 786 isr(tim3)
 787 isr(tim4)
 788 isr(i2c1_ev)
 789 isr(i2c1_er)
 790 isr(i2c2_ev)
 791 isr(i2c2_er)
 792 isr(spi1)
 793 isr(spi2)
 794 isr(usart1)
 795 isr(usart2)
 796 isr(usart3)
 797 isr(exti15_10)
 798 isr(rtc_alarm)
 799 isr(usb_fs_wkup)
 800 isr(tim6)
 801 isr(tim7)
 802
 803 #undef isr
 804
 805 #define STM_ISR_WWDG_POS                0
 806 #define STM_ISR_PVD_POS                 1
 807 #define STM_ISR_TAMPER_STAMP_POS        2
 808 #define STM_ISR_RTC_WKUP_POS            3
 809 #define STM_ISR_FLASH_POS               4
 810 #define STM_ISR_RCC_POS                 5
 811 #define STM_ISR_EXTI0_POS               6
 812 #define STM_ISR_EXTI1_POS               7
 813 #define STM_ISR_EXTI2_POS               8
 814 #define STM_ISR_EXTI3_POS               9
 815 #define STM_ISR_EXTI4_POS               10
 816 #define STM_ISR_DMA1_CHANNEL1_POS       11
 817 #define STM_ISR_DMA2_CHANNEL1_POS       12
 818 #define STM_ISR_DMA3_CHANNEL1_POS       13
 819 #define STM_ISR_DMA4_CHANNEL1_POS       14
 820 #define STM_ISR_DMA5_CHANNEL1_POS       15
 821 #define STM_ISR_DMA6_CHANNEL1_POS       16
 822 #define STM_ISR_DMA7_CHANNEL1_POS       17
 823 #define STM_ISR_ADC1_POS                18
 824 #define STM_ISR_USB_HP_POS              19
 825 #define STM_ISR_USB_LP_POS              20
 826 #define STM_ISR_DAC_POS                 21
 827 #define STM_ISR_COMP_POS                22
 828 #define STM_ISR_EXTI9_5_POS             23
 829 #define STM_ISR_LCD_POS                 24
 830 #define STM_ISR_TIM9_POS                25
 831 #define STM_ISR_TIM10_POS               26
 832 #define STM_ISR_TIM11_POS               27
 833 #define STM_ISR_TIM2_POS                28
 834 #define STM_ISR_TIM3_POS                29
 835 #define STM_ISR_TIM4_POS                30
 836 #define STM_ISR_I2C1_EV_POS             31
 837 #define STM_ISR_I2C1_ER_POS             32
 838 #define STM_ISR_I2C2_EV_POS             33
 839 #define STM_ISR_I2C2_ER_POS             34
 840 #define STM_ISR_SPI1_POS                35
 841 #define STM_ISR_SPI2_POS                36
 842 #define STM_ISR_USART1_POS              37
 843 #define STM_ISR_USART2_POS              38
 844 #define STM_ISR_USART3_POS              39
 845 #define STM_ISR_EXTI15_10_POS           40
 846 #define STM_ISR_RTC_ALARM_POS           41
 847 #define STM_ISR_USB_FS_WKUP_POS         42
 848 #define STM_ISR_TIM6_POS                43
 849 #define STM_ISR_TIM7_POS                44
 850
 851 struct stm_dma_channel {
 852         vuint32_t       ccr;
 853         vuint32_t       cndtr;
 854         vuint32_t       cpar;
 855         vuint32_t       cmar;
 856         vuint32_t       reserved;
 857 };
 858
 859 #define STM_NUM_DMA     7
 860
 861 struct stm_dma {
 862         vuint32_t               isr;
 863         vuint32_t               ifcr;
 864         struct stm_dma_channel  channel[STM_NUM_DMA];
 865 };
 866
 867 extern struct stm_dma stm_dma;
 868
 869 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
 870  */
 871
 872 #define STM_DMA_INDEX(channel)          ((channel) - 1)
 873
 874 #define STM_DMA_ISR(index)              ((index) << 2)
 875 #define STM_DMA_ISR_MASK                        0xf
 876 #define STM_DMA_ISR_TEIF                        3
 877 #define STM_DMA_ISR_HTIF                        2
 878 #define STM_DMA_ISR_TCIF                        1
 879 #define STM_DMA_ISR_GIF                         0
 880
 881 #define STM_DMA_IFCR(index)             ((index) << 2)
 882 #define STM_DMA_IFCR_MASK                       0xf
 883 #define STM_DMA_IFCR_CTEIF                      3
 884 #define STM_DMA_IFCR_CHTIF                      2
 885 #define STM_DMA_IFCR_CTCIF                      1
 886 #define STM_DMA_IFCR_CGIF                       0
 887
 888 #define STM_DMA_CCR_MEM2MEM             (14)
 889
 890 #define STM_DMA_CCR_PL                  (12)
 891 #define  STM_DMA_CCR_PL_LOW                     (0)
 892 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
 893 #define  STM_DMA_CCR_PL_HIGH                    (2)
 894 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
 895 #define  STM_DMA_CCR_PL_MASK                    (3)
 896
 897 #define STM_DMA_CCR_MSIZE               (10)
 898 #define  STM_DMA_CCR_MSIZE_8                    (0)
 899 #define  STM_DMA_CCR_MSIZE_16                   (1)
 900 #define  STM_DMA_CCR_MSIZE_32                   (2)
 901 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
 902
 903 #define STM_DMA_CCR_PSIZE               (8)
 904 #define  STM_DMA_CCR_PSIZE_8                    (0)
 905 #define  STM_DMA_CCR_PSIZE_16                   (1)
 906 #define  STM_DMA_CCR_PSIZE_32                   (2)
 907 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
 908
 909 #define STM_DMA_CCR_MINC                (7)
 910 #define STM_DMA_CCR_PINC                (6)
 911 #define STM_DMA_CCR_CIRC                (5)
 912 #define STM_DMA_CCR_DIR                 (4)
 913 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
 914 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
 915 #define STM_DMA_CCR_TEIE                (3)
 916 #define STM_DMA_CCR_HTIE                (2)
 917 #define STM_DMA_CCR_TCIE                (1)
 918 #define STM_DMA_CCR_EN                  (0)
 919
 920 #define STM_DMA_CHANNEL_ADC1            1
 921 #define STM_DMA_CHANNEL_SPI1_RX         2
 922 #define STM_DMA_CHANNEL_SPI1_TX         3
 923 #define STM_DMA_CHANNEL_SPI2_RX         4
 924 #define STM_DMA_CHANNEL_SPI2_TX         5
 925 #define STM_DMA_CHANNEL_USART3_TX       2
 926 #define STM_DMA_CHANNEL_USART3_RX       3
 927 #define STM_DMA_CHANNEL_USART1_TX       4
 928 #define STM_DMA_CHANNEL_USART1_RX       5
 929 #define STM_DMA_CHANNEL_USART2_RX       6
 930 #define STM_DMA_CHANNEL_USART2_TX       7
 931 #define STM_DMA_CHANNEL_I2C2_TX         4
 932 #define STM_DMA_CHANNEL_I2C2_RX         5
 933 #define STM_DMA_CHANNEL_I2C1_RX         6
 934 #define STM_DMA_CHANNEL_I2C1_TX         7
 935 #define STM_DMA_CHANNEL_TIM2_CH3        1
 936 #define STM_DMA_CHANNEL_TIM2_UP         2
 937 #define STM_DMA_CHANNEL_TIM2_CH1        5
 938 #define STM_DMA_CHANNEL_TIM2_CH2        7
 939 #define STM_DMA_CHANNEL_TIM2_CH4        7
 940 #define STM_DMA_CHANNEL_TIM3_CH3        2
 941 #define STM_DMA_CHANNEL_TIM3_CH4        3
 942 #define STM_DMA_CHANNEL_TIM3_UP         3
 943 #define STM_DMA_CHANNEL_TIM3_CH1        6
 944 #define STM_DMA_CHANNEL_TIM3_TRIG       6
 945 #define STM_DMA_CHANNEL_TIM4_CH1        1
 946 #define STM_DMA_CHANNEL_TIM4_CH2        4
 947 #define STM_DMA_CHANNEL_TIM4_CH3        5
 948 #define STM_DMA_CHANNEL_TIM4_UP         7
 949 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
 950 #define STM_DMA_CHANNEL_C_CHANNEL1      2
 951 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
 952 #define STM_DMA_CHANNEL_C_CHANNEL2      3
 953
 954 /*
 955  * Only spi channel 1 and 2 can use DMA
 956  */
 957 #define STM_NUM_SPI     2
 958
 959 struct stm_spi {
 960         vuint32_t       cr1;
 961         vuint32_t       cr2;
 962         vuint32_t       sr;
 963         vuint32_t       dr;
 964         vuint32_t       crcpr;
 965         vuint32_t       rxcrcr;
 966         vuint32_t       txcrcr;
 967 };
 968
 969 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
 970
 971 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
 972  */
 973
 974 #define STM_SPI_INDEX(channel)          ((channel) - 1)
 975
 976 #define STM_SPI_CR1_BIDIMODE            15
 977 #define STM_SPI_CR1_BIDIOE              14
 978 #define STM_SPI_CR1_CRCEN               13
 979 #define STM_SPI_CR1_CRCNEXT             12
 980 #define STM_SPI_CR1_DFF                 11
 981 #define STM_SPI_CR1_RXONLY              10
 982 #define STM_SPI_CR1_SSM                 9
 983 #define STM_SPI_CR1_SSI                 8
 984 #define STM_SPI_CR1_LSBFIRST            7
 985 #define STM_SPI_CR1_SPE                 6
 986 #define STM_SPI_CR1_BR                  3
 987 #define  STM_SPI_CR1_BR_PCLK_2                  0
 988 #define  STM_SPI_CR1_BR_PCLK_4                  1
 989 #define  STM_SPI_CR1_BR_PCLK_8                  2
 990 #define  STM_SPI_CR1_BR_PCLK_16                 3
 991 #define  STM_SPI_CR1_BR_PCLK_32                 4
 992 #define  STM_SPI_CR1_BR_PCLK_64                 5
 993 #define  STM_SPI_CR1_BR_PCLK_128                6
 994 #define  STM_SPI_CR1_BR_PCLK_256                7
 995 #define  STM_SPI_CR1_BR_MASK                    7
 996
 997 #define STM_SPI_CR1_MSTR                2
 998 #define STM_SPI_CR1_CPOL                1
 999 #define STM_SPI_CR1_CPHA                0
1000
1001 #define STM_SPI_CR2_TXEIE       7
1002 #define STM_SPI_CR2_RXNEIE      6
1003 #define STM_SPI_CR2_ERRIE       5
1004 #define STM_SPI_CR2_SSOE        2
1005 #define STM_SPI_CR2_TXDMAEN     1
1006 #define STM_SPI_CR2_RXDMAEN     0
1007
1008 #define STM_SPI_SR_BSY          7
1009 #define STM_SPI_SR_OVR          6
1010 #define STM_SPI_SR_MODF         5
1011 #define STM_SPI_SR_CRCERR       4
1012 #define STM_SPI_SR_TXE          1
1013 #define STM_SPI_SR_RXNE         0
1014
1015 #endif /* _STM32L_H_ */