2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile void * vvoid_t;
42 #define STM_MODER_SHIFT(pin) ((pin) << 1)
43 #define STM_MODER_MASK 3
44 #define STM_MODER_INPUT 0
45 #define STM_MODER_OUTPUT 1
46 #define STM_MODER_ALTERNATE 2
47 #define STM_MODER_ANALOG 3
50 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
51 gpio->moder = ((gpio->moder &
52 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
53 value << STM_MODER_SHIFT(pin));
56 static inline uint32_t
57 stm_moder_get(struct stm_gpio *gpio, int pin) {
58 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
61 #define STM_OTYPER_SHIFT(pin) (pin)
62 #define STM_OTYPER_MASK 1
63 #define STM_OTYPER_PUSH_PULL 0
64 #define STM_OTYPER_OPEN_DRAIN 1
67 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
68 gpio->otyper = ((gpio->otyper &
69 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
70 value << STM_OTYPER_SHIFT(pin));
73 static inline uint32_t
74 stm_otyper_get(struct stm_gpio *gpio, int pin) {
75 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
78 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
79 #define STM_OSPEEDR_MASK 3
80 #define STM_OSPEEDR_400kHz 0
81 #define STM_OSPEEDR_2MHz 1
82 #define STM_OSPEEDR_10MHz 2
83 #define STM_OSPEEDR_40MHz 3
86 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
87 gpio->ospeedr = ((gpio->ospeedr &
88 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
89 value << STM_OSPEEDR_SHIFT(pin));
92 static inline uint32_t
93 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
94 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
97 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
98 #define STM_PUPDR_MASK 3
99 #define STM_PUPDR_NONE 0
100 #define STM_PUPDR_PULL_UP 1
101 #define STM_PUPDR_PULL_DOWN 2
102 #define STM_PUPDR_RESERVED 3
105 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
106 gpio->pupdr = ((gpio->pupdr &
107 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
108 value << STM_PUPDR_SHIFT(pin));
111 static inline uint32_t
112 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
113 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
116 #define STM_AFR_SHIFT(pin) ((pin) << 2)
117 #define STM_AFR_MASK 0xf
118 #define STM_AFR_NONE 0
119 #define STM_AFR_AF0 0x0
120 #define STM_AFR_AF1 0x1
121 #define STM_AFR_AF2 0x2
122 #define STM_AFR_AF3 0x3
123 #define STM_AFR_AF4 0x4
124 #define STM_AFR_AF5 0x5
125 #define STM_AFR_AF6 0x6
126 #define STM_AFR_AF7 0x7
127 #define STM_AFR_AF8 0x8
128 #define STM_AFR_AF9 0x9
129 #define STM_AFR_AF10 0xa
130 #define STM_AFR_AF11 0xb
131 #define STM_AFR_AF12 0xc
132 #define STM_AFR_AF13 0xd
133 #define STM_AFR_AF14 0xe
134 #define STM_AFR_AF15 0xf
137 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
139 * Set alternate pin mode too
141 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
143 gpio->afrl = ((gpio->afrl &
144 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
145 value << STM_AFR_SHIFT(pin));
148 gpio->afrh = ((gpio->afrh &
149 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
150 value << STM_AFR_SHIFT(pin));
154 static inline uint32_t
155 stm_afr_get(struct stm_gpio *gpio, int pin) {
157 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
160 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
165 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
166 /* Use the bit set/reset register to do this atomically */
167 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
171 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
172 /* Use the bit set/reset register to do this atomically */
173 gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
177 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
182 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
183 gpio->bsrr = ((uint32_t) bits) << 16;
186 static inline uint8_t
187 stm_gpio_get(struct stm_gpio *gpio, int pin) {
188 return (gpio->idr >> pin) & 1;
191 static inline uint16_t
192 stm_gpio_get_all(struct stm_gpio *gpio) {
197 * We can't define these in registers.ld or our fancy
198 * ao_enable_gpio macro will expand into a huge pile of code
199 * as the compiler won't do correct constant folding and
200 * dead-code elimination
202 extern struct stm_gpio stm_gpioa;
203 extern struct stm_gpio stm_gpiob;
204 extern struct stm_gpio stm_gpioc;
205 extern struct stm_gpio stm_gpiod;
206 extern struct stm_gpio stm_gpioe;
207 extern struct stm_gpio stm_gpioh;
211 #define stm_gpioh (*((struct stm_gpio *) 0x40021400))
212 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
213 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
214 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
215 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
216 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
219 vuint32_t sr; /* status register */
220 vuint32_t dr; /* data register */
221 vuint32_t brr; /* baud rate register */
222 vuint32_t cr1; /* control register 1 */
224 vuint32_t cr2; /* control register 2 */
225 vuint32_t cr3; /* control register 3 */
226 vuint32_t gtpr; /* guard time and prescaler */
229 extern struct stm_usart stm_usart1;
230 extern struct stm_usart stm_usart2;
231 extern struct stm_usart stm_usart3;
233 #define STM_USART_SR_CTS (9) /* CTS flag */
234 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
235 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
236 #define STM_USART_SR_TC (6) /* Transmission complete */
237 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
238 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
239 #define STM_USART_SR_ORE (3) /* Overrun error */
240 #define STM_USART_SR_NF (2) /* Noise detected flag */
241 #define STM_USART_SR_FE (1) /* Framing error */
242 #define STM_USART_SR_PE (0) /* Parity error */
244 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
245 #define STM_USART_CR1_UE (13) /* USART enable */
246 #define STM_USART_CR1_M (12) /* Word length */
247 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
248 #define STM_USART_CR1_PCE (10) /* Parity control enable */
249 #define STM_USART_CR1_PS (9) /* Parity selection */
250 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
251 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
252 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
253 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
254 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
255 #define STM_USART_CR1_TE (3) /* Transmitter enable */
256 #define STM_USART_CR1_RE (2) /* Receiver enable */
257 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
258 #define STM_USART_CR1_SBK (0) /* Send break */
260 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
261 #define STM_USART_CR2_STOP (12) /* STOP bits */
262 #define STM_USART_CR2_STOP_MASK 3
263 #define STM_USART_CR2_STOP_1 0
264 #define STM_USART_CR2_STOP_0_5 1
265 #define STM_USART_CR2_STOP_2 2
266 #define STM_USART_CR2_STOP_1_5 3
268 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
269 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
270 #define STM_USART_CR2_CPHA (9) /* Clock phase */
271 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
272 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
273 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
274 #define STM_USART_CR2_ADD (0)
275 #define STM_USART_CR2_ADD_MASK 0xf
277 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
278 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
279 #define STM_USART_CR3_CTSE (9) /* CTS enable */
280 #define STM_USART_CR3_RTSE (8) /* RTS enable */
281 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
282 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
283 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
284 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
285 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
286 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
287 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
288 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
293 extern struct stm_tim stm_tim9;
319 extern struct stm_tim1011 stm_tim10;
320 extern struct stm_tim1011 stm_tim11;
322 #define STM_TIM1011_CR1_CKD 8
323 #define STM_TIM1011_CR1_CKD_1 0
324 #define STM_TIM1011_CR1_CKD_2 1
325 #define STM_TIM1011_CR1_CKD_4 2
326 #define STM_TIM1011_CR1_CKD_MASK 3
327 #define STM_TIM1011_CR1_ARPE 7
328 #define STM_TIM1011_CR1_URS 2
329 #define STM_TIM1011_CR1_UDIS 1
330 #define STM_TIM1011_CR1_CEN 0
332 #define STM_TIM1011_SMCR_ETP 15
333 #define STM_TIM1011_SMCR_ECE 14
334 #define STM_TIM1011_SMCR_ETPS 12
335 #define STM_TIM1011_SMCR_ETPS_OFF 0
336 #define STM_TIM1011_SMCR_ETPS_2 1
337 #define STM_TIM1011_SMCR_ETPS_4 2
338 #define STM_TIM1011_SMCR_ETPS_8 3
339 #define STM_TIM1011_SMCR_ETPS_MASK 3
340 #define STM_TIM1011_SMCR_ETF 8
341 #define STM_TIM1011_SMCR_ETF_NONE 0
342 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1
343 #define STM_TIM1011_SMCR_ETF_CK_INT_4 2
344 #define STM_TIM1011_SMCR_ETF_CK_INT_8 3
345 #define STM_TIM1011_SMCR_ETF_DTS_2_6 4
346 #define STM_TIM1011_SMCR_ETF_DTS_2_8 5
347 #define STM_TIM1011_SMCR_ETF_DTS_4_6 6
348 #define STM_TIM1011_SMCR_ETF_DTS_4_8 7
349 #define STM_TIM1011_SMCR_ETF_DTS_8_6 8
350 #define STM_TIM1011_SMCR_ETF_DTS_8_8 9
351 #define STM_TIM1011_SMCR_ETF_DTS_16_5 10
352 #define STM_TIM1011_SMCR_ETF_DTS_16_6 11
353 #define STM_TIM1011_SMCR_ETF_DTS_16_8 12
354 #define STM_TIM1011_SMCR_ETF_DTS_32_5 13
355 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14
356 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15
357 #define STM_TIM1011_SMCR_ETF_MASK 15
359 #define STM_TIM1011_DIER_CC1E 1
360 #define STM_TIM1011_DIER_UIE 0
362 #define STM_TIM1011_SR_CC1OF 9
363 #define STM_TIM1011_SR_CC1IF 1
364 #define STM_TIM1011_SR_UIF 0
366 #define STM_TIM1011_EGR_CC1G 1
367 #define STM_TIM1011_EGR_UG 0
369 #define STM_TIM1011_CCMR1_OC1CE 7
370 #define STM_TIM1011_CCMR1_OC1M 4
371 #define STM_TIM1011_CCMR1_OC1M_FROZEN 0
372 #define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
373 #define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
374 #define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
375 #define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
376 #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
377 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
378 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
379 #define STM_TIM1011_CCMR1_OC1M_MASK 7
380 #define STM_TIM1011_CCMR1_OC1PE 3
381 #define STM_TIM1011_CCMR1_OC1FE 2
382 #define STM_TIM1011_CCMR1_CC1S 0
383 #define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
384 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
385 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
386 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
387 #define STM_TIM1011_CCMR1_CC1S_MASK 3
389 #define STM_TIM1011_CCMR1_IC1F_NONE 0
390 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
391 #define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
392 #define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
393 #define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
394 #define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
395 #define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
396 #define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
397 #define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
398 #define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
399 #define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
400 #define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
401 #define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
402 #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
403 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
404 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
405 #define STM_TIM1011_CCMR1_IC1F_MASK 15
406 #define STM_TIM1011_CCMR1_IC1PSC 2
407 #define STM_TIM1011_CCMR1_IC1PSC_1 0
408 #define STM_TIM1011_CCMR1_IC1PSC_2 1
409 #define STM_TIM1011_CCMR1_IC1PSC_4 2
410 #define STM_TIM1011_CCMR1_IC1PSC_8 3
411 #define STM_TIM1011_CCMR1_IC1PSC_MASK 3
412 #define STM_TIM1011_CCMR1_CC1S 0
414 #define STM_TIM1011_CCER_CC1NP 3
415 #define STM_TIM1011_CCER_CC1P 1
416 #define STM_TIM1011_CCER_CC1E 0
418 #define STM_TIM1011_OR_TI1_RMP_RI 3
419 #define STM_TIM1011_ETR_RMP 2
420 #define STM_TIM1011_TI1_RMP 0
421 #define STM_TIM1011_TI1_RMP_GPIO 0
422 #define STM_TIM1011_TI1_RMP_LSI 1
423 #define STM_TIM1011_TI1_RMP_LSE 2
424 #define STM_TIM1011_TI1_RMP_RTC 3
425 #define STM_TIM1011_TI1_RMP_MASK 3
427 /* Flash interface */
443 extern struct stm_flash stm_flash;
445 #define STM_FLASH_ACR_RUN_PD (4)
446 #define STM_FLASH_ACR_SLEEP_PD (3)
447 #define STM_FLASH_ACR_ACC64 (2)
448 #define STM_FLASH_ACR_PRFEN (1)
449 #define STM_FLASH_ACR_LATENCY (0)
451 #define STM_FLASH_PECR_OBL_LAUNCH 18
452 #define STM_FLASH_PECR_ERRIE 17
453 #define STM_FLASH_PECR_EOPIE 16
454 #define STM_FLASH_PECR_FPRG 10
455 #define STM_FLASH_PECR_ERASE 9
456 #define STM_FLASH_PECR_FTDW 8
457 #define STM_FLASH_PECR_DATA 4
458 #define STM_FLASH_PECR_PROG 3
459 #define STM_FLASH_PECR_OPTLOCK 2
460 #define STM_FLASH_PECR_PRGLOCK 1
461 #define STM_FLASH_PECR_PELOCK 0
463 #define STM_FLASH_SR_OPTVERR 11
464 #define STM_FLASH_SR_SIZERR 10
465 #define STM_FLASH_SR_PGAERR 9
466 #define STM_FLASH_SR_WRPERR 8
467 #define STM_FLASH_SR_READY 3
468 #define STM_FLASH_SR_ENDHV 2
469 #define STM_FLASH_SR_EOP 1
470 #define STM_FLASH_SR_BSY 0
472 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
473 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
475 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
476 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
498 extern struct stm_rcc stm_rcc;
500 /* Nominal high speed internal oscillator frequency is 16MHz */
501 #define STM_HSI_FREQ 16000000
503 #define STM_RCC_CR_RTCPRE (29)
504 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
505 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
506 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
507 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
508 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
510 #define STM_RCC_CR_CSSON (28)
511 #define STM_RCC_CR_PLLRDY (25)
512 #define STM_RCC_CR_PLLON (24)
513 #define STM_RCC_CR_HSEBYP (18)
514 #define STM_RCC_CR_HSERDY (17)
515 #define STM_RCC_CR_HSEON (16)
516 #define STM_RCC_CR_MSIRDY (9)
517 #define STM_RCC_CR_MSION (8)
518 #define STM_RCC_CR_HSIRDY (1)
519 #define STM_RCC_CR_HSION (0)
521 #define STM_RCC_CFGR_MCOPRE (28)
522 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
523 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
524 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
525 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
526 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
527 #define STM_RCC_CFGR_MCOPRE_MASK 7
529 #define STM_RCC_CFGR_MCOSEL (24)
530 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
531 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
532 #define STM_RCC_CFGR_MCOSEL_HSI 2
533 #define STM_RCC_CFGR_MCOSEL_MSI 3
534 #define STM_RCC_CFGR_MCOSEL_HSE 4
535 #define STM_RCC_CFGR_MCOSEL_PLL 5
536 #define STM_RCC_CFGR_MCOSEL_LSI 6
537 #define STM_RCC_CFGR_MCOSEL_LSE 7
538 #define STM_RCC_CFGR_MCOSEL_MASK 7
540 #define STM_RCC_CFGR_PLLDIV (22)
541 #define STM_RCC_CFGR_PLLDIV_2 1
542 #define STM_RCC_CFGR_PLLDIV_3 2
543 #define STM_RCC_CFGR_PLLDIV_4 3
544 #define STM_RCC_CFGR_PLLDIV_MASK 3
546 #define STM_RCC_CFGR_PLLMUL (18)
547 #define STM_RCC_CFGR_PLLMUL_3 0
548 #define STM_RCC_CFGR_PLLMUL_4 1
549 #define STM_RCC_CFGR_PLLMUL_6 2
550 #define STM_RCC_CFGR_PLLMUL_8 3
551 #define STM_RCC_CFGR_PLLMUL_12 4
552 #define STM_RCC_CFGR_PLLMUL_16 5
553 #define STM_RCC_CFGR_PLLMUL_24 6
554 #define STM_RCC_CFGR_PLLMUL_32 7
555 #define STM_RCC_CFGR_PLLMUL_48 8
556 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
558 #define STM_RCC_CFGR_PLLSRC (16)
560 #define STM_RCC_CFGR_PPRE2 (11)
561 #define STM_RCC_CFGR_PPRE2_DIV_1 0
562 #define STM_RCC_CFGR_PPRE2_DIV_2 4
563 #define STM_RCC_CFGR_PPRE2_DIV_4 5
564 #define STM_RCC_CFGR_PPRE2_DIV_8 6
565 #define STM_RCC_CFGR_PPRE2_DIV_16 7
566 #define STM_RCC_CFGR_PPRE2_MASK 7
568 #define STM_RCC_CFGR_PPRE1 (8)
569 #define STM_RCC_CFGR_PPRE1_DIV_1 0
570 #define STM_RCC_CFGR_PPRE1_DIV_2 4
571 #define STM_RCC_CFGR_PPRE1_DIV_4 5
572 #define STM_RCC_CFGR_PPRE1_DIV_8 6
573 #define STM_RCC_CFGR_PPRE1_DIV_16 7
574 #define STM_RCC_CFGR_PPRE1_MASK 7
576 #define STM_RCC_CFGR_HPRE (4)
577 #define STM_RCC_CFGR_HPRE_DIV_1 0
578 #define STM_RCC_CFGR_HPRE_DIV_2 8
579 #define STM_RCC_CFGR_HPRE_DIV_4 9
580 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
581 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
582 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
583 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
584 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
585 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
586 #define STM_RCC_CFGR_HPRE_MASK 0xf
588 #define STM_RCC_CFGR_SWS (2)
589 #define STM_RCC_CFGR_SWS_MSI 0
590 #define STM_RCC_CFGR_SWS_HSI 1
591 #define STM_RCC_CFGR_SWS_HSE 2
592 #define STM_RCC_CFGR_SWS_PLL 3
593 #define STM_RCC_CFGR_SWS_MASK 3
595 #define STM_RCC_CFGR_SW (0)
596 #define STM_RCC_CFGR_SW_MSI 0
597 #define STM_RCC_CFGR_SW_HSI 1
598 #define STM_RCC_CFGR_SW_HSE 2
599 #define STM_RCC_CFGR_SW_PLL 3
600 #define STM_RCC_CFGR_SW_MASK 3
602 #define STM_RCC_AHBENR_DMA1EN (24)
603 #define STM_RCC_AHBENR_FLITFEN (15)
604 #define STM_RCC_AHBENR_CRCEN (12)
605 #define STM_RCC_AHBENR_GPIOHEN (5)
606 #define STM_RCC_AHBENR_GPIOEEN (4)
607 #define STM_RCC_AHBENR_GPIODEN (3)
608 #define STM_RCC_AHBENR_GPIOCEN (2)
609 #define STM_RCC_AHBENR_GPIOBEN (1)
610 #define STM_RCC_AHBENR_GPIOAEN (0)
612 #define STM_RCC_APB2ENR_USART1EN (14)
613 #define STM_RCC_APB2ENR_SPI1EN (12)
614 #define STM_RCC_APB2ENR_ADC1EN (9)
615 #define STM_RCC_APB2ENR_TIM11EN (4)
616 #define STM_RCC_APB2ENR_TIM10EN (3)
617 #define STM_RCC_APB2ENR_TIM9EN (2)
618 #define STM_RCC_APB2ENR_SYSCFGEN (0)
620 #define STM_RCC_APB1ENR_COMPEN (31)
621 #define STM_RCC_APB1ENR_DACEN (29)
622 #define STM_RCC_APB1ENR_PWREN (28)
623 #define STM_RCC_APB1ENR_USBEN (23)
624 #define STM_RCC_APB1ENR_I2C2EN (22)
625 #define STM_RCC_APB1ENR_I2C1EN (21)
626 #define STM_RCC_APB1ENR_USART3EN (18)
627 #define STM_RCC_APB1ENR_USART2EN (17)
628 #define STM_RCC_APB1ENR_SPI2EN (14)
629 #define STM_RCC_APB1ENR_WWDGEN (11)
630 #define STM_RCC_APB1ENR_LCDEN (9)
631 #define STM_RCC_APB1ENR_TIM7EN (5)
632 #define STM_RCC_APB1ENR_TIM6EN (4)
633 #define STM_RCC_APB1ENR_TIM4EN (2)
634 #define STM_RCC_APB1ENR_TIM3EN (1)
635 #define STM_RCC_APB1ENR_TIM2EN (0)
637 #define STM_RCC_CSR_LPWRRSTF (31)
638 #define STM_RCC_CSR_WWDGRSTF (30)
639 #define STM_RCC_CSR_IWDGRSTF (29)
640 #define STM_RCC_CSR_SFTRSTF (28)
641 #define STM_RCC_CSR_PORRSTF (27)
642 #define STM_RCC_CSR_PINRSTF (26)
643 #define STM_RCC_CSR_OBLRSTF (25)
644 #define STM_RCC_CSR_RMVF (24)
645 #define STM_RCC_CSR_RTFRST (23)
646 #define STM_RCC_CSR_RTCEN (22)
647 #define STM_RCC_CSR_RTCSEL (16)
649 #define STM_RCC_CSR_RTCSEL_NONE 0
650 #define STM_RCC_CSR_RTCSEL_LSE 1
651 #define STM_RCC_CSR_RTCSEL_LSI 2
652 #define STM_RCC_CSR_RTCSEL_HSE 3
653 #define STM_RCC_CSR_RTCSEL_MASK 3
655 #define STM_RCC_CSR_LSEBYP (10)
656 #define STM_RCC_CSR_LSERDY (9)
657 #define STM_RCC_CSR_LSEON (8)
658 #define STM_RCC_CSR_LSIRDY (1)
659 #define STM_RCC_CSR_LSION (0)
666 extern struct stm_pwr stm_pwr;
668 #define STM_PWR_CR_LPRUN (14)
670 #define STM_PWR_CR_VOS (11)
671 #define STM_PWR_CR_VOS_1_8 1
672 #define STM_PWR_CR_VOS_1_5 2
673 #define STM_PWR_CR_VOS_1_2 3
674 #define STM_PWR_CR_VOS_MASK 3
676 #define STM_PWR_CR_FWU (10)
677 #define STM_PWR_CR_ULP (9)
678 #define STM_PWR_CR_DBP (8)
680 #define STM_PWR_CR_PLS (5)
681 #define STM_PWR_CR_PLS_1_9 0
682 #define STM_PWR_CR_PLS_2_1 1
683 #define STM_PWR_CR_PLS_2_3 2
684 #define STM_PWR_CR_PLS_2_5 3
685 #define STM_PWR_CR_PLS_2_7 4
686 #define STM_PWR_CR_PLS_2_9 5
687 #define STM_PWR_CR_PLS_3_1 6
688 #define STM_PWR_CR_PLS_EXT 7
689 #define STM_PWR_CR_PLS_MASK 7
691 #define STM_PWR_CR_PVDE (4)
692 #define STM_PWR_CR_CSBF (3)
693 #define STM_PWR_CR_CWUF (2)
694 #define STM_PWR_CR_PDDS (1)
695 #define STM_PWR_CR_LPSDSR (0)
697 #define STM_PWR_CSR_EWUP3 (10)
698 #define STM_PWR_CSR_EWUP2 (9)
699 #define STM_PWR_CSR_EWUP1 (8)
700 #define STM_PWR_CSR_REGLPF (5)
701 #define STM_PWR_CSR_VOSF (4)
702 #define STM_PWR_CSR_VREFINTRDYF (3)
703 #define STM_PWR_CSR_PVDO (2)
704 #define STM_PWR_CSR_SBF (1)
705 #define STM_PWR_CSR_WUF (0)
724 extern struct stm_tim67 stm_tim6;
726 #define STM_TIM67_CR1_ARPE (7)
727 #define STM_TIM67_CR1_OPM (3)
728 #define STM_TIM67_CR1_URS (2)
729 #define STM_TIM67_CR1_UDIS (1)
730 #define STM_TIM67_CR1_CEN (0)
732 #define STM_TIM67_CR2_MMS (4)
733 #define STM_TIM67_CR2_MMS_RESET 0
734 #define STM_TIM67_CR2_MMS_ENABLE 1
735 #define STM_TIM67_CR2_MMS_UPDATE 2
736 #define STM_TIM67_CR2_MMS_MASK 7
738 #define STM_TIM67_DIER_UDE (8)
739 #define STM_TIM67_DIER_UIE (0)
741 #define STM_TIM67_SR_UIF (0)
743 #define STM_TIM67_EGR_UG (0)
750 uint32_t unused_0x10;
754 extern struct stm_lcd stm_lcd;
756 #define STM_LCD_CR_MUX_SEG (7)
758 #define STM_LCD_CR_BIAS (5)
759 #define STM_LCD_CR_BIAS_1_4 0
760 #define STM_LCD_CR_BIAS_1_2 1
761 #define STM_LCD_CR_BIAS_1_3 2
762 #define STM_LCD_CR_BIAS_MASK 3
764 #define STM_LCD_CR_DUTY (2)
765 #define STM_LCD_CR_DUTY_STATIC 0
766 #define STM_LCD_CR_DUTY_1_2 1
767 #define STM_LCD_CR_DUTY_1_3 2
768 #define STM_LCD_CR_DUTY_1_4 3
769 #define STM_LCD_CR_DUTY_1_8 4
770 #define STM_LCD_CR_DUTY_MASK 7
772 #define STM_LCD_CR_VSEL (1)
773 #define STM_LCD_CR_LCDEN (0)
775 #define STM_LCD_FCR_PS (22)
776 #define STM_LCD_FCR_PS_1 0x0
777 #define STM_LCD_FCR_PS_2 0x1
778 #define STM_LCD_FCR_PS_4 0x2
779 #define STM_LCD_FCR_PS_8 0x3
780 #define STM_LCD_FCR_PS_16 0x4
781 #define STM_LCD_FCR_PS_32 0x5
782 #define STM_LCD_FCR_PS_64 0x6
783 #define STM_LCD_FCR_PS_128 0x7
784 #define STM_LCD_FCR_PS_256 0x8
785 #define STM_LCD_FCR_PS_512 0x9
786 #define STM_LCD_FCR_PS_1024 0xa
787 #define STM_LCD_FCR_PS_2048 0xb
788 #define STM_LCD_FCR_PS_4096 0xc
789 #define STM_LCD_FCR_PS_8192 0xd
790 #define STM_LCD_FCR_PS_16384 0xe
791 #define STM_LCD_FCR_PS_32768 0xf
792 #define STM_LCD_FCR_PS_MASK 0xf
794 #define STM_LCD_FCR_DIV (18)
795 #define STM_LCD_FCR_DIV_16 0x0
796 #define STM_LCD_FCR_DIV_17 0x1
797 #define STM_LCD_FCR_DIV_18 0x2
798 #define STM_LCD_FCR_DIV_19 0x3
799 #define STM_LCD_FCR_DIV_20 0x4
800 #define STM_LCD_FCR_DIV_21 0x5
801 #define STM_LCD_FCR_DIV_22 0x6
802 #define STM_LCD_FCR_DIV_23 0x7
803 #define STM_LCD_FCR_DIV_24 0x8
804 #define STM_LCD_FCR_DIV_25 0x9
805 #define STM_LCD_FCR_DIV_26 0xa
806 #define STM_LCD_FCR_DIV_27 0xb
807 #define STM_LCD_FCR_DIV_28 0xc
808 #define STM_LCD_FCR_DIV_29 0xd
809 #define STM_LCD_FCR_DIV_30 0xe
810 #define STM_LCD_FCR_DIV_31 0xf
811 #define STM_LCD_FCR_DIV_MASK 0xf
813 #define STM_LCD_FCR_BLINK (16)
814 #define STM_LCD_FCR_BLINK_DISABLE 0
815 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
816 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
817 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
818 #define STM_LCD_FCR_BLINK_MASK 3
820 #define STM_LCD_FCR_BLINKF (13)
821 #define STM_LCD_FCR_BLINKF_8 0
822 #define STM_LCD_FCR_BLINKF_16 1
823 #define STM_LCD_FCR_BLINKF_32 2
824 #define STM_LCD_FCR_BLINKF_64 3
825 #define STM_LCD_FCR_BLINKF_128 4
826 #define STM_LCD_FCR_BLINKF_256 5
827 #define STM_LCD_FCR_BLINKF_512 6
828 #define STM_LCD_FCR_BLINKF_1024 7
829 #define STM_LCD_FCR_BLINKF_MASK 7
831 #define STM_LCD_FCR_CC (10)
832 #define STM_LCD_FCR_CC_MASK 7
834 #define STM_LCD_FCR_DEAD (7)
835 #define STM_LCD_FCR_DEAD_MASK 7
837 #define STM_LCD_FCR_PON (4)
838 #define STM_LCD_FCR_PON_MASK 7
840 #define STM_LCD_FCR_UDDIE (3)
841 #define STM_LCD_FCR_SOFIE (1)
842 #define STM_LCD_FCR_HD (0)
844 #define STM_LCD_SR_FCRSF (5)
845 #define STM_LCD_SR_RDY (4)
846 #define STM_LCD_SR_UDD (3)
847 #define STM_LCD_SR_UDR (2)
848 #define STM_LCD_SR_SOF (1)
849 #define STM_LCD_SR_ENS (0)
851 #define STM_LCD_CLR_UDDC (3)
852 #define STM_LCD_CLR_SOFC (1)
854 /* The SYSTICK starts at 0xe000e010 */
863 extern struct stm_systick stm_systick;
865 #define STM_SYSTICK_CSR_ENABLE 0
866 #define STM_SYSTICK_CSR_TICKINT 1
867 #define STM_SYSTICK_CSR_CLKSOURCE 2
868 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0
869 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1
870 #define STM_SYSTICK_CSR_COUNTFLAG 16
872 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
875 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
877 uint8_t _unused020[0x080 - 0x020];
879 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
881 uint8_t _unused0a0[0x100 - 0x0a0];
883 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
885 uint8_t _unused120[0x180 - 0x120];
887 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
889 uint8_t _unused1a0[0x200 - 0x1a0];
891 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
893 uint8_t _unused220[0x300 - 0x220];
895 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
897 uint8_t _unused3f0[0xc00 - 0x3f0];
899 vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */
900 vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */
901 vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */
902 vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
903 vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
904 vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
906 vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */
907 vuint32_t shpr11_8; /* 0xc1c */
908 vuint32_t shpr15_12; /* 0xc20 */
910 uint8_t _unusedc18[0xe00 - 0xc24];
912 vuint32_t stir; /* 0xe00 */
915 extern struct stm_nvic stm_nvic;
917 #define IRQ_REG(irq) ((irq) >> 5)
918 #define IRQ_BIT(irq) ((irq) & 0x1f)
919 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
920 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
923 stm_nvic_set_enable(int irq) {
924 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
928 stm_nvic_clear_enable(int irq) {
929 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
933 stm_nvic_enabled(int irq) {
934 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
938 stm_nvic_set_pending(int irq) {
939 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
943 stm_nvic_clear_pending(int irq) {
944 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
948 stm_nvic_pending(int irq) {
949 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
953 stm_nvic_active(int irq) {
954 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
957 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
958 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
959 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
962 stm_nvic_set_priority(int irq, uint8_t prio) {
963 int n = IRQ_PRIO_REG(irq);
967 v &= ~IRQ_PRIO_MASK(irq);
968 v |= (prio) << IRQ_PRIO_BIT(irq);
972 static inline uint8_t
973 stm_nvic_get_priority(int irq) {
974 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
998 extern struct stm_scb stm_scb;
1000 #define STM_SCB_AIRCR_VECTKEY 16
1001 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
1002 #define STM_SCB_AIRCR_PRIGROUP 8
1003 #define STM_SCB_AIRCR_SYSRESETREQ 2
1004 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
1005 #define STM_SCB_AIRCR_VECTRESET 0
1022 extern struct stm_mpu stm_mpu;
1024 #define STM_MPU_TYPER_IREGION 16
1025 #define STM_MPU_TYPER_IREGION_MASK 0xff
1026 #define STM_MPU_TYPER_DREGION 8
1027 #define STM_MPU_TYPER_DREGION_MASK 0xff
1028 #define STM_MPU_TYPER_SEPARATE 0
1030 #define STM_MPU_CR_PRIVDEFENA 2
1031 #define STM_MPU_CR_HFNMIENA 1
1032 #define STM_MPU_CR_ENABLE 0
1034 #define STM_MPU_RNR_REGION 0
1035 #define STM_MPU_RNR_REGION_MASK 0xff
1037 #define STM_MPU_RBAR_ADDR 5
1038 #define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
1040 #define STM_MPU_RBAR_VALID 4
1041 #define STM_MPU_RBAR_REGION 0
1042 #define STM_MPU_RBAR_REGION_MASK 0xf
1044 #define STM_MPU_RASR_XN 28
1045 #define STM_MPU_RASR_AP 24
1046 #define STM_MPU_RASR_AP_NONE_NONE 0
1047 #define STM_MPU_RASR_AP_RW_NONE 1
1048 #define STM_MPU_RASR_AP_RW_RO 2
1049 #define STM_MPU_RASR_AP_RW_RW 3
1050 #define STM_MPU_RASR_AP_RO_NONE 5
1051 #define STM_MPU_RASR_AP_RO_RO 6
1052 #define STM_MPU_RASR_AP_MASK 7
1053 #define STM_MPU_RASR_TEX 19
1054 #define STM_MPU_RASR_TEX_MASK 7
1055 #define STM_MPU_RASR_S 18
1056 #define STM_MPU_RASR_C 17
1057 #define STM_MPU_RASR_B 16
1058 #define STM_MPU_RASR_SRD 8
1059 #define STM_MPU_RASR_SRD_MASK 0xff
1060 #define STM_MPU_RASR_SIZE 1
1061 #define STM_MPU_RASR_SIZE_MASK 0x1f
1062 #define STM_MPU_RASR_ENABLE 0
1064 #define isr(name) void stm_ ## name ## _isr(void);
1123 #define STM_ISR_WWDG_POS 0
1124 #define STM_ISR_PVD_POS 1
1125 #define STM_ISR_TAMPER_STAMP_POS 2
1126 #define STM_ISR_RTC_WKUP_POS 3
1127 #define STM_ISR_FLASH_POS 4
1128 #define STM_ISR_RCC_POS 5
1129 #define STM_ISR_EXTI0_POS 6
1130 #define STM_ISR_EXTI1_POS 7
1131 #define STM_ISR_EXTI2_POS 8
1132 #define STM_ISR_EXTI3_POS 9
1133 #define STM_ISR_EXTI4_POS 10
1134 #define STM_ISR_DMA1_CHANNEL1_POS 11
1135 #define STM_ISR_DMA2_CHANNEL1_POS 12
1136 #define STM_ISR_DMA3_CHANNEL1_POS 13
1137 #define STM_ISR_DMA4_CHANNEL1_POS 14
1138 #define STM_ISR_DMA5_CHANNEL1_POS 15
1139 #define STM_ISR_DMA6_CHANNEL1_POS 16
1140 #define STM_ISR_DMA7_CHANNEL1_POS 17
1141 #define STM_ISR_ADC1_POS 18
1142 #define STM_ISR_USB_HP_POS 19
1143 #define STM_ISR_USB_LP_POS 20
1144 #define STM_ISR_DAC_POS 21
1145 #define STM_ISR_COMP_POS 22
1146 #define STM_ISR_EXTI9_5_POS 23
1147 #define STM_ISR_LCD_POS 24
1148 #define STM_ISR_TIM9_POS 25
1149 #define STM_ISR_TIM10_POS 26
1150 #define STM_ISR_TIM11_POS 27
1151 #define STM_ISR_TIM2_POS 28
1152 #define STM_ISR_TIM3_POS 29
1153 #define STM_ISR_TIM4_POS 30
1154 #define STM_ISR_I2C1_EV_POS 31
1155 #define STM_ISR_I2C1_ER_POS 32
1156 #define STM_ISR_I2C2_EV_POS 33
1157 #define STM_ISR_I2C2_ER_POS 34
1158 #define STM_ISR_SPI1_POS 35
1159 #define STM_ISR_SPI2_POS 36
1160 #define STM_ISR_USART1_POS 37
1161 #define STM_ISR_USART2_POS 38
1162 #define STM_ISR_USART3_POS 39
1163 #define STM_ISR_EXTI15_10_POS 40
1164 #define STM_ISR_RTC_ALARM_POS 41
1165 #define STM_ISR_USB_FS_WKUP_POS 42
1166 #define STM_ISR_TIM6_POS 43
1167 #define STM_ISR_TIM7_POS 44
1172 vuint32_t exticr[4];
1175 extern struct stm_syscfg stm_syscfg;
1177 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
1178 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
1179 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
1180 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
1181 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
1183 #define STM_SYSCFG_PMC_USB_PU 0
1185 #define STM_SYSCFG_EXTICR_PA 0
1186 #define STM_SYSCFG_EXTICR_PB 1
1187 #define STM_SYSCFG_EXTICR_PC 2
1188 #define STM_SYSCFG_EXTICR_PD 3
1189 #define STM_SYSCFG_EXTICR_PE 4
1190 #define STM_SYSCFG_EXTICR_PH 5
1193 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1194 uint8_t reg = pin >> 2;
1195 uint8_t shift = (pin & 3) << 2;
1199 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1201 if (gpio == &stm_gpioa)
1202 val = STM_SYSCFG_EXTICR_PA;
1203 else if (gpio == &stm_gpiob)
1204 val = STM_SYSCFG_EXTICR_PB;
1205 else if (gpio == &stm_gpioc)
1206 val = STM_SYSCFG_EXTICR_PC;
1207 else if (gpio == &stm_gpiod)
1208 val = STM_SYSCFG_EXTICR_PD;
1209 else if (gpio == &stm_gpioe)
1210 val = STM_SYSCFG_EXTICR_PE;
1212 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1216 struct stm_dma_channel {
1224 #define STM_NUM_DMA 7
1229 struct stm_dma_channel channel[STM_NUM_DMA];
1232 extern struct stm_dma stm_dma;
1234 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1237 #define STM_DMA_INDEX(channel) ((channel) - 1)
1239 #define STM_DMA_ISR(index) ((index) << 2)
1240 #define STM_DMA_ISR_MASK 0xf
1241 #define STM_DMA_ISR_TEIF 3
1242 #define STM_DMA_ISR_HTIF 2
1243 #define STM_DMA_ISR_TCIF 1
1244 #define STM_DMA_ISR_GIF 0
1246 #define STM_DMA_IFCR(index) ((index) << 2)
1247 #define STM_DMA_IFCR_MASK 0xf
1248 #define STM_DMA_IFCR_CTEIF 3
1249 #define STM_DMA_IFCR_CHTIF 2
1250 #define STM_DMA_IFCR_CTCIF 1
1251 #define STM_DMA_IFCR_CGIF 0
1253 #define STM_DMA_CCR_MEM2MEM (14)
1255 #define STM_DMA_CCR_PL (12)
1256 #define STM_DMA_CCR_PL_LOW (0)
1257 #define STM_DMA_CCR_PL_MEDIUM (1)
1258 #define STM_DMA_CCR_PL_HIGH (2)
1259 #define STM_DMA_CCR_PL_VERY_HIGH (3)
1260 #define STM_DMA_CCR_PL_MASK (3)
1262 #define STM_DMA_CCR_MSIZE (10)
1263 #define STM_DMA_CCR_MSIZE_8 (0)
1264 #define STM_DMA_CCR_MSIZE_16 (1)
1265 #define STM_DMA_CCR_MSIZE_32 (2)
1266 #define STM_DMA_CCR_MSIZE_MASK (3)
1268 #define STM_DMA_CCR_PSIZE (8)
1269 #define STM_DMA_CCR_PSIZE_8 (0)
1270 #define STM_DMA_CCR_PSIZE_16 (1)
1271 #define STM_DMA_CCR_PSIZE_32 (2)
1272 #define STM_DMA_CCR_PSIZE_MASK (3)
1274 #define STM_DMA_CCR_MINC (7)
1275 #define STM_DMA_CCR_PINC (6)
1276 #define STM_DMA_CCR_CIRC (5)
1277 #define STM_DMA_CCR_DIR (4)
1278 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
1279 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
1280 #define STM_DMA_CCR_TEIE (3)
1281 #define STM_DMA_CCR_HTIE (2)
1282 #define STM_DMA_CCR_TCIE (1)
1283 #define STM_DMA_CCR_EN (0)
1285 #define STM_DMA_CHANNEL_ADC1 1
1286 #define STM_DMA_CHANNEL_SPI1_RX 2
1287 #define STM_DMA_CHANNEL_SPI1_TX 3
1288 #define STM_DMA_CHANNEL_SPI2_RX 4
1289 #define STM_DMA_CHANNEL_SPI2_TX 5
1290 #define STM_DMA_CHANNEL_USART3_TX 2
1291 #define STM_DMA_CHANNEL_USART3_RX 3
1292 #define STM_DMA_CHANNEL_USART1_TX 4
1293 #define STM_DMA_CHANNEL_USART1_RX 5
1294 #define STM_DMA_CHANNEL_USART2_RX 6
1295 #define STM_DMA_CHANNEL_USART2_TX 7
1296 #define STM_DMA_CHANNEL_I2C2_TX 4
1297 #define STM_DMA_CHANNEL_I2C2_RX 5
1298 #define STM_DMA_CHANNEL_I2C1_TX 6
1299 #define STM_DMA_CHANNEL_I2C1_RX 7
1300 #define STM_DMA_CHANNEL_TIM2_CH3 1
1301 #define STM_DMA_CHANNEL_TIM2_UP 2
1302 #define STM_DMA_CHANNEL_TIM2_CH1 5
1303 #define STM_DMA_CHANNEL_TIM2_CH2 7
1304 #define STM_DMA_CHANNEL_TIM2_CH4 7
1305 #define STM_DMA_CHANNEL_TIM3_CH3 2
1306 #define STM_DMA_CHANNEL_TIM3_CH4 3
1307 #define STM_DMA_CHANNEL_TIM3_UP 3
1308 #define STM_DMA_CHANNEL_TIM3_CH1 6
1309 #define STM_DMA_CHANNEL_TIM3_TRIG 6
1310 #define STM_DMA_CHANNEL_TIM4_CH1 1
1311 #define STM_DMA_CHANNEL_TIM4_CH2 4
1312 #define STM_DMA_CHANNEL_TIM4_CH3 5
1313 #define STM_DMA_CHANNEL_TIM4_UP 7
1314 #define STM_DMA_CHANNEL_TIM6_UP_DA 2
1315 #define STM_DMA_CHANNEL_C_CHANNEL1 2
1316 #define STM_DMA_CHANNEL_TIM7_UP_DA 3
1317 #define STM_DMA_CHANNEL_C_CHANNEL2 3
1320 * Only spi channel 1 and 2 can use DMA
1322 #define STM_NUM_SPI 2
1334 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1336 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1339 #define STM_SPI_INDEX(channel) ((channel) - 1)
1341 #define STM_SPI_CR1_BIDIMODE 15
1342 #define STM_SPI_CR1_BIDIOE 14
1343 #define STM_SPI_CR1_CRCEN 13
1344 #define STM_SPI_CR1_CRCNEXT 12
1345 #define STM_SPI_CR1_DFF 11
1346 #define STM_SPI_CR1_RXONLY 10
1347 #define STM_SPI_CR1_SSM 9
1348 #define STM_SPI_CR1_SSI 8
1349 #define STM_SPI_CR1_LSBFIRST 7
1350 #define STM_SPI_CR1_SPE 6
1351 #define STM_SPI_CR1_BR 3
1352 #define STM_SPI_CR1_BR_PCLK_2 0
1353 #define STM_SPI_CR1_BR_PCLK_4 1
1354 #define STM_SPI_CR1_BR_PCLK_8 2
1355 #define STM_SPI_CR1_BR_PCLK_16 3
1356 #define STM_SPI_CR1_BR_PCLK_32 4
1357 #define STM_SPI_CR1_BR_PCLK_64 5
1358 #define STM_SPI_CR1_BR_PCLK_128 6
1359 #define STM_SPI_CR1_BR_PCLK_256 7
1360 #define STM_SPI_CR1_BR_MASK 7
1362 #define STM_SPI_CR1_MSTR 2
1363 #define STM_SPI_CR1_CPOL 1
1364 #define STM_SPI_CR1_CPHA 0
1366 #define STM_SPI_CR2_TXEIE 7
1367 #define STM_SPI_CR2_RXNEIE 6
1368 #define STM_SPI_CR2_ERRIE 5
1369 #define STM_SPI_CR2_SSOE 2
1370 #define STM_SPI_CR2_TXDMAEN 1
1371 #define STM_SPI_CR2_RXDMAEN 0
1373 #define STM_SPI_SR_FRE 8
1374 #define STM_SPI_SR_BSY 7
1375 #define STM_SPI_SR_OVR 6
1376 #define STM_SPI_SR_MODF 5
1377 #define STM_SPI_SR_CRCERR 4
1378 #define STM_SPI_SR_UDR 3
1379 #define STM_SPI_SR_CHSIDE 2
1380 #define STM_SPI_SR_TXE 1
1381 #define STM_SPI_SR_RXNE 0
1407 uint8_t reserved[0x300 - 0x5c];
1412 extern struct stm_adc stm_adc;
1414 #define STM_ADC_SR_JCNR 9
1415 #define STM_ADC_SR_RCNR 8
1416 #define STM_ADC_SR_ADONS 6
1417 #define STM_ADC_SR_OVR 5
1418 #define STM_ADC_SR_STRT 4
1419 #define STM_ADC_SR_JSTRT 3
1420 #define STM_ADC_SR_JEOC 2
1421 #define STM_ADC_SR_EOC 1
1422 #define STM_ADC_SR_AWD 0
1424 #define STM_ADC_CR1_OVRIE 26
1425 #define STM_ADC_CR1_RES 24
1426 #define STM_ADC_CR1_RES_12 0
1427 #define STM_ADC_CR1_RES_10 1
1428 #define STM_ADC_CR1_RES_8 2
1429 #define STM_ADC_CR1_RES_6 3
1430 #define STM_ADC_CR1_RES_MASK 3
1431 #define STM_ADC_CR1_AWDEN 23
1432 #define STM_ADC_CR1_JAWDEN 22
1433 #define STM_ADC_CR1_PDI 17
1434 #define STM_ADC_CR1_PDD 16
1435 #define STM_ADC_CR1_DISCNUM 13
1436 #define STM_ADC_CR1_DISCNUM_1 0
1437 #define STM_ADC_CR1_DISCNUM_2 1
1438 #define STM_ADC_CR1_DISCNUM_3 2
1439 #define STM_ADC_CR1_DISCNUM_4 3
1440 #define STM_ADC_CR1_DISCNUM_5 4
1441 #define STM_ADC_CR1_DISCNUM_6 5
1442 #define STM_ADC_CR1_DISCNUM_7 6
1443 #define STM_ADC_CR1_DISCNUM_8 7
1444 #define STM_ADC_CR1_DISCNUM_MASK 7
1445 #define STM_ADC_CR1_JDISCEN 12
1446 #define STM_ADC_CR1_DISCEN 11
1447 #define STM_ADC_CR1_JAUTO 10
1448 #define STM_ADC_CR1_AWDSGL 9
1449 #define STM_ADC_CR1_SCAN 8
1450 #define STM_ADC_CR1_JEOCIE 7
1451 #define STM_ADC_CR1_AWDIE 6
1452 #define STM_ADC_CR1_EOCIE 5
1453 #define STM_ADC_CR1_AWDCH 0
1454 #define STM_ADC_CR1_AWDCH_MASK 0x1f
1456 #define STM_ADC_CR2_SWSTART 30
1457 #define STM_ADC_CR2_EXTEN 28
1458 #define STM_ADC_CR2_EXTEN_DISABLE 0
1459 #define STM_ADC_CR2_EXTEN_RISING 1
1460 #define STM_ADC_CR2_EXTEN_FALLING 2
1461 #define STM_ADC_CR2_EXTEN_BOTH 3
1462 #define STM_ADC_CR2_EXTEN_MASK 3
1463 #define STM_ADC_CR2_EXTSEL 24
1464 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
1465 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
1466 #define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
1467 #define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
1468 #define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
1469 #define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
1470 #define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
1471 #define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
1472 #define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
1473 #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
1474 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
1475 #define STM_ADC_CR2_EXTSEL_EXTI_11 15
1476 #define STM_ADC_CR2_EXTSEL_MASK 15
1477 #define STM_ADC_CR2_JWSTART 22
1478 #define STM_ADC_CR2_JEXTEN 20
1479 #define STM_ADC_CR2_JEXTEN_DISABLE 0
1480 #define STM_ADC_CR2_JEXTEN_RISING 1
1481 #define STM_ADC_CR2_JEXTEN_FALLING 2
1482 #define STM_ADC_CR2_JEXTEN_BOTH 3
1483 #define STM_ADC_CR2_JEXTEN_MASK 3
1484 #define STM_ADC_CR2_JEXTSEL 16
1485 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
1486 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
1487 #define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
1488 #define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
1489 #define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
1490 #define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
1491 #define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
1492 #define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
1493 #define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
1494 #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
1495 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
1496 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15
1497 #define STM_ADC_CR2_JEXTSEL_MASK 15
1498 #define STM_ADC_CR2_ALIGN 11
1499 #define STM_ADC_CR2_EOCS 10
1500 #define STM_ADC_CR2_DDS 9
1501 #define STM_ADC_CR2_DMA 8
1502 #define STM_ADC_CR2_DELS 4
1503 #define STM_ADC_CR2_DELS_NONE 0
1504 #define STM_ADC_CR2_DELS_UNTIL_READ 1
1505 #define STM_ADC_CR2_DELS_7 2
1506 #define STM_ADC_CR2_DELS_15 3
1507 #define STM_ADC_CR2_DELS_31 4
1508 #define STM_ADC_CR2_DELS_63 5
1509 #define STM_ADC_CR2_DELS_127 6
1510 #define STM_ADC_CR2_DELS_255 7
1511 #define STM_ADC_CR2_DELS_MASK 7
1512 #define STM_ADC_CR2_CONT 1
1513 #define STM_ADC_CR2_ADON 0
1515 #define STM_ADC_CCR_TSVREFE 23
1516 #define STM_ADC_CCR_ADCPRE 16
1517 #define STM_ADC_CCR_ADCPRE_HSI_1 0
1518 #define STM_ADC_CCR_ADCPRE_HSI_2 1
1519 #define STM_ADC_CCR_ADCPRE_HSI_4 2
1520 #define STM_ADC_CCR_ADCPRE_MASK 3
1522 struct stm_temp_cal {
1524 uint16_t ts_cal_cold;
1526 uint16_t ts_cal_hot;
1529 extern struct stm_temp_cal stm_temp_cal;
1531 #define stm_temp_cal_cold 25
1532 #define stm_temp_cal_hot 110
1534 struct stm_dbg_mcu {
1538 extern struct stm_dbg_mcu stm_dbg_mcu;
1540 static inline uint16_t
1542 return stm_dbg_mcu.idcode & 0xfff;
1545 struct stm_flash_size {
1549 extern struct stm_flash_size stm_flash_size_medium;
1550 extern struct stm_flash_size stm_flash_size_large;
1552 /* Returns flash size in bytes */
1554 stm_flash_size(void);
1556 struct stm_device_id {
1562 extern struct stm_device_id stm_device_id;
1564 #define STM_NUM_I2C 2
1566 #define STM_I2C_INDEX(channel) ((channel) - 1)
1580 extern struct stm_i2c stm_i2c1, stm_i2c2;
1582 #define STM_I2C_CR1_SWRST 15
1583 #define STM_I2C_CR1_ALERT 13
1584 #define STM_I2C_CR1_PEC 12
1585 #define STM_I2C_CR1_POS 11
1586 #define STM_I2C_CR1_ACK 10
1587 #define STM_I2C_CR1_STOP 9
1588 #define STM_I2C_CR1_START 8
1589 #define STM_I2C_CR1_NOSTRETCH 7
1590 #define STM_I2C_CR1_ENGC 6
1591 #define STM_I2C_CR1_ENPEC 5
1592 #define STM_I2C_CR1_ENARP 4
1593 #define STM_I2C_CR1_SMBTYPE 3
1594 #define STM_I2C_CR1_SMBUS 1
1595 #define STM_I2C_CR1_PE 0
1597 #define STM_I2C_CR2_LAST 12
1598 #define STM_I2C_CR2_DMAEN 11
1599 #define STM_I2C_CR2_ITBUFEN 10
1600 #define STM_I2C_CR2_ITEVTEN 9
1601 #define STM_I2C_CR2_ITERREN 8
1602 #define STM_I2C_CR2_FREQ 0
1603 #define STM_I2C_CR2_FREQ_2_MHZ 2
1604 #define STM_I2C_CR2_FREQ_4_MHZ 4
1605 #define STM_I2C_CR2_FREQ_8_MHZ 8
1606 #define STM_I2C_CR2_FREQ_16_MHZ 16
1607 #define STM_I2C_CR2_FREQ_24_MHZ 24
1608 #define STM_I2C_CR2_FREQ_32_MHZ 32
1609 #define STM_I2C_CR2_FREQ_MASK 0x3f
1611 #define STM_I2C_SR1_SMBALERT 15
1612 #define STM_I2C_SR1_TIMEOUT 14
1613 #define STM_I2C_SR1_PECERR 12
1614 #define STM_I2C_SR1_OVR 11
1615 #define STM_I2C_SR1_AF 10
1616 #define STM_I2C_SR1_ARLO 9
1617 #define STM_I2C_SR1_BERR 8
1618 #define STM_I2C_SR1_TXE 7
1619 #define STM_I2C_SR1_RXNE 6
1620 #define STM_I2C_SR1_STOPF 4
1621 #define STM_I2C_SR1_ADD10 3
1622 #define STM_I2C_SR1_BTF 2
1623 #define STM_I2C_SR1_ADDR 1
1624 #define STM_I2C_SR1_SB 0
1626 #define STM_I2C_SR2_PEC 8
1627 #define STM_I2C_SR2_PEC_MASK 0xff00
1628 #define STM_I2C_SR2_DUALF 7
1629 #define STM_I2C_SR2_SMBHOST 6
1630 #define STM_I2C_SR2_SMBDEFAULT 5
1631 #define STM_I2C_SR2_GENCALL 4
1632 #define STM_I2C_SR2_TRA 2
1633 #define STM_I2C_SR2_BUSY 1
1634 #define STM_I2C_SR2_MSL 0
1636 #define STM_I2C_CCR_FS 15
1637 #define STM_I2C_CCR_DUTY 14
1638 #define STM_I2C_CCR_CCR 0
1639 #define STM_I2C_CCR_MASK 0x7ff
1657 uint32_t reserved_30;
1663 uint32_t reserved_44;
1667 uint32_t reserved_50;
1670 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1672 #define STM_TIM234_CR1_CKD 8
1673 #define STM_TIM234_CR1_CKD_1 0
1674 #define STM_TIM234_CR1_CKD_2 1
1675 #define STM_TIM234_CR1_CKD_4 2
1676 #define STM_TIM234_CR1_CKD_MASK 3
1677 #define STM_TIM234_CR1_ARPE 7
1678 #define STM_TIM234_CR1_CMS 5
1679 #define STM_TIM234_CR1_CMS_EDGE 0
1680 #define STM_TIM234_CR1_CMS_CENTER_1 1
1681 #define STM_TIM234_CR1_CMS_CENTER_2 2
1682 #define STM_TIM234_CR1_CMS_CENTER_3 3
1683 #define STM_TIM234_CR1_CMS_MASK 3
1684 #define STM_TIM234_CR1_DIR 4
1685 #define STM_TIM234_CR1_DIR_UP 0
1686 #define STM_TIM234_CR1_DIR_DOWN 1
1687 #define STM_TIM234_CR1_OPM 3
1688 #define STM_TIM234_CR1_URS 2
1689 #define STM_TIM234_CR1_UDIS 1
1690 #define STM_TIM234_CR1_CEN 0
1692 #define STM_TIM234_CR2_TI1S 7
1693 #define STM_TIM234_CR2_MMS 4
1694 #define STM_TIM234_CR2_MMS_RESET 0
1695 #define STM_TIM234_CR2_MMS_ENABLE 1
1696 #define STM_TIM234_CR2_MMS_UPDATE 2
1697 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1698 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1699 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1700 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1701 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1702 #define STM_TIM234_CR2_MMS_MASK 7
1703 #define STM_TIM234_CR2_CCDS 3
1705 #define STM_TIM234_SMCR_ETP 15
1706 #define STM_TIM234_SMCR_ECE 14
1707 #define STM_TIM234_SMCR_ETPS 12
1708 #define STM_TIM234_SMCR_ETPS_OFF 0
1709 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1710 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1711 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1712 #define STM_TIM234_SMCR_ETPS_MASK 3
1713 #define STM_TIM234_SMCR_ETF 8
1714 #define STM_TIM234_SMCR_ETF_NONE 0
1715 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1716 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1717 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1718 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1719 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1720 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1721 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1722 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1723 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1724 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1725 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1726 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1727 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1728 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1729 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1730 #define STM_TIM234_SMCR_ETF_MASK 15
1731 #define STM_TIM234_SMCR_MSM 7
1732 #define STM_TIM234_SMCR_TS 4
1733 #define STM_TIM234_SMCR_TS_ITR0 0
1734 #define STM_TIM234_SMCR_TS_ITR1 1
1735 #define STM_TIM234_SMCR_TS_ITR2 2
1736 #define STM_TIM234_SMCR_TS_ITR3 3
1737 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1738 #define STM_TIM234_SMCR_TS_TI1FP1 5
1739 #define STM_TIM234_SMCR_TS_TI2FP2 6
1740 #define STM_TIM234_SMCR_TS_ETRF 7
1741 #define STM_TIM234_SMCR_TS_MASK 7
1742 #define STM_TIM234_SMCR_OCCS 3
1743 #define STM_TIM234_SMCR_SMS 0
1744 #define STM_TIM234_SMCR_SMS_DISABLE 0
1745 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1746 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1747 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1748 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1749 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1750 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1751 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1752 #define STM_TIM234_SMCR_SMS_MASK 7
1754 #define STM_TIM234_DIER_CC4IE 4
1755 #define STM_TIM234_DIER_CC3IE 3
1756 #define STM_TIM234_DIER_CC2IE 2
1757 #define STM_TIM234_DIER_CC1IE 1
1758 #define STM_TIM234_DIER_UIE 0
1760 #define STM_TIM234_SR_CC4OF 12
1761 #define STM_TIM234_SR_CC3OF 11
1762 #define STM_TIM234_SR_CC2OF 10
1763 #define STM_TIM234_SR_CC1OF 9
1764 #define STM_TIM234_SR_TIF 6
1765 #define STM_TIM234_SR_CC4IF 4
1766 #define STM_TIM234_SR_CC3IF 3
1767 #define STM_TIM234_SR_CC2IF 2
1768 #define STM_TIM234_SR_CC1IF 1
1769 #define STM_TIM234_SR_UIF 0
1771 #define STM_TIM234_EGR_TG 6
1772 #define STM_TIM234_EGR_CC4G 4
1773 #define STM_TIM234_EGR_CC3G 3
1774 #define STM_TIM234_EGR_CC2G 2
1775 #define STM_TIM234_EGR_CC1G 1
1776 #define STM_TIM234_EGR_UG 0
1778 #define STM_TIM234_CCMR1_OC2CE 15
1779 #define STM_TIM234_CCMR1_OC2M 12
1780 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1781 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1782 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1783 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1784 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1785 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1786 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1787 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1788 #define STM_TIM234_CCMR1_OC2M_MASK 7
1789 #define STM_TIM234_CCMR1_OC2PE 11
1790 #define STM_TIM234_CCMR1_OC2FE 10
1791 #define STM_TIM234_CCMR1_CC2S 8
1792 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1793 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1794 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1795 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1796 #define STM_TIM234_CCMR1_CC2S_MASK 3
1798 #define STM_TIM234_CCMR1_OC1CE 7
1799 #define STM_TIM234_CCMR1_OC1M 4
1800 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1801 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1802 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1803 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1804 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1805 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1806 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1807 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1808 #define STM_TIM234_CCMR1_OC1M_MASK 7
1809 #define STM_TIM234_CCMR1_OC1PE 3
1810 #define STM_TIM234_CCMR1_OC1FE 2
1811 #define STM_TIM234_CCMR1_CC1S 0
1812 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1813 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1814 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1815 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1816 #define STM_TIM234_CCMR1_CC1S_MASK 3
1818 #define STM_TIM234_CCMR2_OC4CE 15
1819 #define STM_TIM234_CCMR2_OC4M 12
1820 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1821 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1822 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1823 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1824 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1825 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1826 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1827 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1828 #define STM_TIM234_CCMR2_OC4M_MASK 7
1829 #define STM_TIM234_CCMR2_OC4PE 11
1830 #define STM_TIM234_CCMR2_OC4FE 10
1831 #define STM_TIM234_CCMR2_CC4S 8
1832 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1833 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1834 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1835 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1836 #define STM_TIM234_CCMR2_CC4S_MASK 3
1838 #define STM_TIM234_CCMR2_OC3CE 7
1839 #define STM_TIM234_CCMR2_OC3M 4
1840 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1841 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1842 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1843 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1844 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1845 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1846 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1847 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1848 #define STM_TIM234_CCMR2_OC3M_MASK 7
1849 #define STM_TIM234_CCMR2_OC3PE 3
1850 #define STM_TIM234_CCMR2_OC3FE 2
1851 #define STM_TIM234_CCMR2_CC3S 0
1852 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1853 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1854 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1855 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1856 #define STM_TIM234_CCMR2_CC3S_MASK 3
1858 #define STM_TIM234_CCER_CC4NP 15
1859 #define STM_TIM234_CCER_CC4P 13
1860 #define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
1861 #define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
1862 #define STM_TIM234_CCER_CC4E 12
1863 #define STM_TIM234_CCER_CC3NP 11
1864 #define STM_TIM234_CCER_CC3P 9
1865 #define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
1866 #define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
1867 #define STM_TIM234_CCER_CC3E 8
1868 #define STM_TIM234_CCER_CC2NP 7
1869 #define STM_TIM234_CCER_CC2P 5
1870 #define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
1871 #define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
1872 #define STM_TIM234_CCER_CC2E 4
1873 #define STM_TIM234_CCER_CC1NP 3
1874 #define STM_TIM234_CCER_CC1P 1
1875 #define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
1876 #define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
1877 #define STM_TIM234_CCER_CC1E 0
1881 uint8_t reserved_20[0x40 - 0x20];
1889 #define STM_USB_EPR_CTR_RX 15
1890 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
1891 #define STM_USB_EPR_DTOG_RX 14
1892 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
1893 #define STM_USB_EPR_STAT_RX 12
1894 #define STM_USB_EPR_STAT_RX_DISABLED 0
1895 #define STM_USB_EPR_STAT_RX_STALL 1
1896 #define STM_USB_EPR_STAT_RX_NAK 2
1897 #define STM_USB_EPR_STAT_RX_VALID 3
1898 #define STM_USB_EPR_STAT_RX_MASK 3
1899 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
1900 #define STM_USB_EPR_SETUP 11
1901 #define STM_USB_EPR_EP_TYPE 9
1902 #define STM_USB_EPR_EP_TYPE_BULK 0
1903 #define STM_USB_EPR_EP_TYPE_CONTROL 1
1904 #define STM_USB_EPR_EP_TYPE_ISO 2
1905 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
1906 #define STM_USB_EPR_EP_TYPE_MASK 3
1907 #define STM_USB_EPR_EP_KIND 8
1908 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
1909 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
1910 #define STM_USB_EPR_CTR_TX 7
1911 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
1912 #define STM_USB_EPR_DTOG_TX 6
1913 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
1914 #define STM_USB_EPR_STAT_TX 4
1915 #define STM_USB_EPR_STAT_TX_DISABLED 0
1916 #define STM_USB_EPR_STAT_TX_STALL 1
1917 #define STM_USB_EPR_STAT_TX_NAK 2
1918 #define STM_USB_EPR_STAT_TX_VALID 3
1919 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
1920 #define STM_USB_EPR_STAT_TX_MASK 3
1921 #define STM_USB_EPR_EA 0
1922 #define STM_USB_EPR_EA_MASK 0xf
1924 #define STM_USB_CNTR_CTRM 15
1925 #define STM_USB_CNTR_PMAOVRM 14
1926 #define STM_USB_CNTR_ERRM 13
1927 #define STM_USB_CNTR_WKUPM 12
1928 #define STM_USB_CNTR_SUSPM 11
1929 #define STM_USB_CNTR_RESETM 10
1930 #define STM_USB_CNTR_SOFM 9
1931 #define STM_USB_CNTR_ESOFM 8
1932 #define STM_USB_CNTR_RESUME 4
1933 #define STM_USB_CNTR_FSUSP 3
1934 #define STM_USB_CNTR_LP_MODE 2
1935 #define STM_USB_CNTR_PDWN 1
1936 #define STM_USB_CNTR_FRES 0
1938 #define STM_USB_ISTR_CTR 15
1939 #define STM_USB_ISTR_PMAOVR 14
1940 #define STM_USB_ISTR_ERR 13
1941 #define STM_USB_ISTR_WKUP 12
1942 #define STM_USB_ISTR_SUSP 11
1943 #define STM_USB_ISTR_RESET 10
1944 #define STM_USB_ISTR_SOF 9
1945 #define STM_USB_ISTR_ESOF 8
1946 #define STM_USB_ISTR_DIR 4
1947 #define STM_USB_ISTR_EP_ID 0
1948 #define STM_USB_ISTR_EP_ID_MASK 0xf
1950 #define STM_USB_FNR_RXDP 15
1951 #define STM_USB_FNR_RXDM 14
1952 #define STM_USB_FNR_LCK 13
1953 #define STM_USB_FNR_LSOF 11
1954 #define STM_USB_FNR_LSOF_MASK 0x3
1955 #define STM_USB_FNR_FN 0
1956 #define STM_USB_FNR_FN_MASK 0x7ff
1958 #define STM_USB_DADDR_EF 7
1959 #define STM_USB_DADDR_ADD 0
1960 #define STM_USB_DADDR_ADD_MASK 0x7f
1962 extern struct stm_usb stm_usb;
1981 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
1982 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
1983 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
1984 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
1985 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
1987 #define STM_USB_BDT_SIZE 8
1989 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
2001 extern struct stm_exti stm_exti;
2003 #endif /* _STM32L_H_ */