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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #ifndef _STM32L_H_
  20 #define _STM32L_H_
  21
  22 #include <stdint.h>
  23
  24 typedef volatile uint32_t       vuint32_t;
  25 typedef volatile void *         vvoid_t;
  26
  27 struct stm_gpio {
  28         vuint32_t       moder;
  29         vuint32_t       otyper;
  30         vuint32_t       ospeedr;
  31         vuint32_t       pupdr;
  32
  33         vuint32_t       idr;
  34         vuint32_t       odr;
  35         vuint32_t       bsrr;
  36         vuint32_t       lckr;
  37
  38         vuint32_t       afrl;
  39         vuint32_t       afrh;
  40 };
  41
  42 #define STM_MODER_SHIFT(pin)            ((pin) << 1)
  43 #define STM_MODER_MASK                  3
  44 #define STM_MODER_INPUT                 0
  45 #define STM_MODER_OUTPUT                1
  46 #define STM_MODER_ALTERNATE             2
  47 #define STM_MODER_ANALOG                3
  48
  49 static inline void
  50 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  51         gpio->moder = ((gpio->moder &
  52                         ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
  53                        value << STM_MODER_SHIFT(pin));
  54 }
  55
  56 static inline uint32_t
  57 stm_moder_get(struct stm_gpio *gpio, int pin) {
  58         return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
  59 }
  60
  61 #define STM_OTYPER_SHIFT(pin)           (pin)
  62 #define STM_OTYPER_MASK                 1
  63 #define STM_OTYPER_PUSH_PULL            0
  64 #define STM_OTYPER_OPEN_DRAIN           1
  65
  66 static inline void
  67 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  68         gpio->otyper = ((gpio->otyper &
  69                          ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
  70                         value << STM_OTYPER_SHIFT(pin));
  71 }
  72
  73 static inline uint32_t
  74 stm_otyper_get(struct stm_gpio *gpio, int pin) {
  75         return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
  76 }
  77
  78 #define STM_OSPEEDR_SHIFT(pin)          ((pin) << 1)
  79 #define STM_OSPEEDR_MASK                3
  80 #define STM_OSPEEDR_400kHz              0
  81 #define STM_OSPEEDR_2MHz                1
  82 #define STM_OSPEEDR_10MHz               2
  83 #define STM_OSPEEDR_40MHz               3
  84
  85 static inline void
  86 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
  87         gpio->ospeedr = ((gpio->ospeedr &
  88                         ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
  89                        value << STM_OSPEEDR_SHIFT(pin));
  90 }
  91
  92 static inline uint32_t
  93 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
  94         return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
  95 }
  96
  97 #define STM_PUPDR_SHIFT(pin)            ((pin) << 1)
  98 #define STM_PUPDR_MASK                  3
  99 #define STM_PUPDR_NONE                  0
 100 #define STM_PUPDR_PULL_UP               1
 101 #define STM_PUPDR_PULL_DOWN             2
 102 #define STM_PUPDR_RESERVED              3
 103
 104 static inline void
 105 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 106         gpio->pupdr = ((gpio->pupdr &
 107                         ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
 108                        value << STM_PUPDR_SHIFT(pin));
 109 }
 110
 111 static inline uint32_t
 112 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
 113         return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
 114 }
 115
 116 #define STM_AFR_SHIFT(pin)              ((pin) << 2)
 117 #define STM_AFR_MASK                    0xf
 118 #define STM_AFR_NONE                    0
 119 #define STM_AFR_AF0                     0x0
 120 #define STM_AFR_AF1                     0x1
 121 #define STM_AFR_AF2                     0x2
 122 #define STM_AFR_AF3                     0x3
 123 #define STM_AFR_AF4                     0x4
 124 #define STM_AFR_AF5                     0x5
 125 #define STM_AFR_AF6                     0x6
 126 #define STM_AFR_AF7                     0x7
 127 #define STM_AFR_AF8                     0x8
 128 #define STM_AFR_AF9                     0x9
 129 #define STM_AFR_AF10                    0xa
 130 #define STM_AFR_AF11                    0xb
 131 #define STM_AFR_AF12                    0xc
 132 #define STM_AFR_AF13                    0xd
 133 #define STM_AFR_AF14                    0xe
 134 #define STM_AFR_AF15                    0xf
 135
 136 static inline void
 137 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
 138         /*
 139          * Set alternate pin mode too
 140          */
 141         stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
 142         if (pin < 8)
 143                 gpio->afrl = ((gpio->afrl &
 144                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 145                               value << STM_AFR_SHIFT(pin));
 146         else {
 147                 pin -= 8;
 148                 gpio->afrh = ((gpio->afrh &
 149                                ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
 150                               value << STM_AFR_SHIFT(pin));
 151         }
 152 }
 153
 154 static inline uint32_t
 155 stm_afr_get(struct stm_gpio *gpio, int pin) {
 156         if (pin < 8)
 157                 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 158         else {
 159                 pin -= 8;
 160                 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
 161         }
 162 }
 163
 164 static inline void
 165 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
 166         /* Use the bit set/reset register to do this atomically */
 167         gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
 168 }
 169
 170 static inline void
 171 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
 172         gpio->bsrr = bits;
 173 }
 174
 175 static inline void
 176 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
 177         gpio->bsrr = ((uint32_t) bits) << 16;
 178 }
 179
 180 static inline uint8_t
 181 stm_gpio_get(struct stm_gpio *gpio, int pin) {
 182         return (gpio->idr >> pin) & 1;
 183 }
 184
 185 static inline uint16_t
 186 stm_gpio_get_all(struct stm_gpio *gpio) {
 187         return gpio->idr;
 188 }
 189
 190 /*
 191  * We can't define these in registers.ld or our fancy
 192  * ao_enable_gpio macro will expand into a huge pile of code
 193  * as the compiler won't do correct constant folding and
 194  * dead-code elimination
 195
 196  extern struct stm_gpio stm_gpioa;
 197  extern struct stm_gpio stm_gpiob;
 198  extern struct stm_gpio stm_gpioc;
 199  extern struct stm_gpio stm_gpiod;
 200  extern struct stm_gpio stm_gpioe;
 201  extern struct stm_gpio stm_gpioh;
 202
 203 */
 204
 205 #define stm_gpioh  (*((struct stm_gpio *) 0x40021400))
 206 #define stm_gpioe  (*((struct stm_gpio *) 0x40021000))
 207 #define stm_gpiod  (*((struct stm_gpio *) 0x40020c00))
 208 #define stm_gpioc  (*((struct stm_gpio *) 0x40020800))
 209 #define stm_gpiob  (*((struct stm_gpio *) 0x40020400))
 210 #define stm_gpioa  (*((struct stm_gpio *) 0x40020000))
 211
 212 struct stm_usart {
 213         vuint32_t       sr;     /* status register */
 214         vuint32_t       dr;     /* data register */
 215         vuint32_t       brr;    /* baud rate register */
 216         vuint32_t       cr1;    /* control register 1 */
 217
 218         vuint32_t       cr2;    /* control register 2 */
 219         vuint32_t       cr3;    /* control register 3 */
 220         vuint32_t       gtpr;   /* guard time and prescaler */
 221 };
 222
 223 extern struct stm_usart stm_usart1;
 224 extern struct stm_usart stm_usart2;
 225 extern struct stm_usart stm_usart3;
 226
 227 #define STM_USART_SR_CTS        (9)     /* CTS flag */
 228 #define STM_USART_SR_LBD        (8)     /* LIN break detection flag */
 229 #define STM_USART_SR_TXE        (7)     /* Transmit data register empty */
 230 #define STM_USART_SR_TC         (6)     /* Transmission complete */
 231 #define STM_USART_SR_RXNE       (5)     /* Read data register not empty */
 232 #define STM_USART_SR_IDLE       (4)     /* IDLE line detected */
 233 #define STM_USART_SR_ORE        (3)     /* Overrun error */
 234 #define STM_USART_SR_NF         (2)     /* Noise detected flag */
 235 #define STM_USART_SR_FE         (1)     /* Framing error */
 236 #define STM_USART_SR_PE         (0)     /* Parity error */
 237
 238 #define STM_USART_CR1_OVER8     (15)    /* Oversampling mode */
 239 #define STM_USART_CR1_UE        (13)    /* USART enable */
 240 #define STM_USART_CR1_M         (12)    /* Word length */
 241 #define STM_USART_CR1_WAKE      (11)    /* Wakeup method */
 242 #define STM_USART_CR1_PCE       (10)    /* Parity control enable */
 243 #define STM_USART_CR1_PS        (9)     /* Parity selection */
 244 #define STM_USART_CR1_PEIE      (8)     /* PE interrupt enable */
 245 #define STM_USART_CR1_TXEIE     (7)     /* TXE interrupt enable */
 246 #define STM_USART_CR1_TCIE      (6)     /* Transmission complete interrupt enable */
 247 #define STM_USART_CR1_RXNEIE    (5)     /* RXNE interrupt enable */
 248 #define STM_USART_CR1_IDLEIE    (4)     /* IDLE interrupt enable */
 249 #define STM_USART_CR1_TE        (3)     /* Transmitter enable */
 250 #define STM_USART_CR1_RE        (2)     /* Receiver enable */
 251 #define STM_USART_CR1_RWU       (1)     /* Receiver wakeup */
 252 #define STM_USART_CR1_SBK       (0)     /* Send break */
 253
 254 #define STM_USART_CR2_LINEN     (14)    /* LIN mode enable */
 255 #define STM_USART_CR2_STOP      (12)    /* STOP bits */
 256 #define STM_USART_CR2_STOP_MASK 3
 257 #define STM_USART_CR2_STOP_1    0
 258 #define STM_USART_CR2_STOP_0_5  1
 259 #define STM_USART_CR2_STOP_2    2
 260 #define STM_USART_CR2_STOP_1_5  3
 261
 262 #define STM_USART_CR2_CLKEN     (11)    /* Clock enable */
 263 #define STM_USART_CR2_CPOL      (10)    /* Clock polarity */
 264 #define STM_USART_CR2_CPHA      (9)     /* Clock phase */
 265 #define STM_USART_CR2_LBCL      (8)     /* Last bit clock pulse */
 266 #define STM_USART_CR2_LBDIE     (6)     /* LIN break detection interrupt enable */
 267 #define STM_USART_CR2_LBDL      (5)     /* lin break detection length */
 268 #define STM_USART_CR2_ADD       (0)
 269 #define STM_USART_CR2_ADD_MASK  0xf
 270
 271 #define STM_USART_CR3_ONEBITE   (11)    /* One sample bit method enable */
 272 #define STM_USART_CR3_CTSIE     (10)    /* CTS interrupt enable */
 273 #define STM_USART_CR3_CTSE      (9)     /* CTS enable */
 274 #define STM_USART_CR3_RTSE      (8)     /* RTS enable */
 275 #define STM_USART_CR3_DMAT      (7)     /* DMA enable transmitter */
 276 #define STM_USART_CR3_DMAR      (6)     /* DMA enable receiver */
 277 #define STM_USART_CR3_SCEN      (5)     /* Smartcard mode enable */
 278 #define STM_USART_CR3_NACK      (4)     /* Smartcard NACK enable */
 279 #define STM_USART_CR3_HDSEL     (3)     /* Half-duplex selection */
 280 #define STM_USART_CR3_IRLP      (2)     /* IrDA low-power */
 281 #define STM_USART_CR3_IREN      (1)     /* IrDA mode enable */
 282 #define STM_USART_CR3_EIE       (0)     /* Error interrupt enable */
 283
 284 struct stm_tim {
 285 };
 286
 287 extern struct stm_tim stm_tim9;
 288
 289 struct stm_tim1011 {
 290         vuint32_t       cr1;
 291         uint32_t        unused_4;
 292         vuint32_t       smcr;
 293         vuint32_t       dier;
 294         vuint32_t       sr;
 295         vuint32_t       egr;
 296         vuint32_t       ccmr1;
 297         uint32_t        unused_1c;
 298         vuint32_t       ccer;
 299         vuint32_t       cnt;
 300         vuint32_t       psc;
 301         vuint32_t       arr;
 302         uint32_t        unused_30;
 303         vuint32_t       ccr1;
 304         uint32_t        unused_38;
 305         uint32_t        unused_3c;
 306         uint32_t        unused_40;
 307         uint32_t        unused_44;
 308         uint32_t        unused_48;
 309         uint32_t        unused_4c;
 310         vuint32_t       or;
 311 };
 312
 313 extern struct stm_tim1011 stm_tim10;
 314 extern struct stm_tim1011 stm_tim11;
 315
 316 #define STM_TIM1011_CR1_CKD     8
 317 #define  STM_TIM1011_CR1_CKD_1          0
 318 #define  STM_TIM1011_CR1_CKD_2          1
 319 #define  STM_TIM1011_CR1_CKD_4          2
 320 #define  STM_TIM1011_CR1_CKD_MASK       3
 321 #define STM_TIM1011_CR1_ARPE    7
 322 #define STM_TIM1011_CR1_URS     2
 323 #define STM_TIM1011_CR1_UDIS    1
 324 #define STM_TIM1011_CR1_CEN     0
 325
 326 #define STM_TIM1011_SMCR_ETP    15
 327 #define STM_TIM1011_SMCR_ECE    14
 328 #define STM_TIM1011_SMCR_ETPS   12
 329 #define  STM_TIM1011_SMCR_ETPS_OFF      0
 330 #define  STM_TIM1011_SMCR_ETPS_2        1
 331 #define  STM_TIM1011_SMCR_ETPS_4        2
 332 #define  STM_TIM1011_SMCR_ETPS_8        3
 333 #define  STM_TIM1011_SMCR_ETPS_MASK     3
 334 #define STM_TIM1011_SMCR_ETF    8
 335 #define  STM_TIM1011_SMCR_ETF_NONE              0
 336 #define  STM_TIM1011_SMCR_ETF_CK_INT_2          1
 337 #define  STM_TIM1011_SMCR_ETF_CK_INT_4          2
 338 #define  STM_TIM1011_SMCR_ETF_CK_INT_8          3
 339 #define  STM_TIM1011_SMCR_ETF_DTS_2_6           4
 340 #define  STM_TIM1011_SMCR_ETF_DTS_2_8           5
 341 #define  STM_TIM1011_SMCR_ETF_DTS_4_6           6
 342 #define  STM_TIM1011_SMCR_ETF_DTS_4_8           7
 343 #define  STM_TIM1011_SMCR_ETF_DTS_8_6           8
 344 #define  STM_TIM1011_SMCR_ETF_DTS_8_8           9
 345 #define  STM_TIM1011_SMCR_ETF_DTS_16_5          10
 346 #define  STM_TIM1011_SMCR_ETF_DTS_16_6          11
 347 #define  STM_TIM1011_SMCR_ETF_DTS_16_8          12
 348 #define  STM_TIM1011_SMCR_ETF_DTS_32_5          13
 349 #define  STM_TIM1011_SMCR_ETF_DTS_32_6          14
 350 #define  STM_TIM1011_SMCR_ETF_DTS_32_8          15
 351 #define  STM_TIM1011_SMCR_ETF_MASK              15
 352
 353 #define STM_TIM1011_DIER_CC1E   1
 354 #define STM_TIM1011_DIER_UIE    0
 355
 356 #define STM_TIM1011_SR_CC1OF    9
 357 #define STM_TIM1011_SR_CC1IF    1
 358 #define STM_TIM1011_SR_UIF      0
 359
 360 #define STM_TIM1011_EGR_CC1G    1
 361 #define STM_TIM1011_EGR_UG      0
 362
 363 #define STM_TIM1011_CCMR1_OC1CE 7
 364 #define STM_TIM1011_CCMR1_OC1M  4
 365 #define  STM_TIM1011_CCMR1_OC1M_FROZEN                  0
 366 #define  STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH   1
 367 #define  STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
 368 #define  STM_TIM1011_CCMR1_OC1M_TOGGLE                  3
 369 #define  STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE          4
 370 #define  STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE            5
 371 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_1              6
 372 #define  STM_TIM1011_CCMR1_OC1M_PWM_MODE_2              7
 373 #define  STM_TIM1011_CCMR1_OC1M_MASK                    7
 374 #define STM_TIM1011_CCMR1_OC1PE 3
 375 #define STM_TIM1011_CCMR1_OC1FE 2
 376 #define STM_TIM1011_CCMR1_CC1S  0
 377 #define  STM_TIM1011_CCMR1_CC1S_OUTPUT                  0
 378 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI1               1
 379 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TI2               2
 380 #define  STM_TIM1011_CCMR1_CC1S_INPUT_TRC               3
 381 #define  STM_TIM1011_CCMR1_CC1S_MASK                    3
 382
 383 #define  STM_TIM1011_CCMR1_IC1F_NONE            0
 384 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_2        1
 385 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_4        2
 386 #define  STM_TIM1011_CCMR1_IC1F_CK_INT_8        3
 387 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_6         4
 388 #define  STM_TIM1011_CCMR1_IC1F_DTS_2_8         5
 389 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_6         6
 390 #define  STM_TIM1011_CCMR1_IC1F_DTS_4_8         7
 391 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_6         8
 392 #define  STM_TIM1011_CCMR1_IC1F_DTS_8_8         9
 393 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_5        10
 394 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_6        11
 395 #define  STM_TIM1011_CCMR1_IC1F_DTS_16_8        12
 396 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_5        13
 397 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_6        14
 398 #define  STM_TIM1011_CCMR1_IC1F_DTS_32_8        15
 399 #define  STM_TIM1011_CCMR1_IC1F_MASK            15
 400 #define STM_TIM1011_CCMR1_IC1PSC        2
 401 #define  STM_TIM1011_CCMR1_IC1PSC_1             0
 402 #define  STM_TIM1011_CCMR1_IC1PSC_2             1
 403 #define  STM_TIM1011_CCMR1_IC1PSC_4             2
 404 #define  STM_TIM1011_CCMR1_IC1PSC_8             3
 405 #define  STM_TIM1011_CCMR1_IC1PSC_MASK          3
 406 #define STM_TIM1011_CCMR1_CC1S          0
 407
 408 #define STM_TIM1011_CCER_CC1NP          3
 409 #define STM_TIM1011_CCER_CC1P           1
 410 #define STM_TIM1011_CCER_CC1E           0
 411
 412 #define STM_TIM1011_OR_TI1_RMP_RI       3
 413 #define STM_TIM1011_ETR_RMP             2
 414 #define STM_TIM1011_TI1_RMP             0
 415 #define  STM_TIM1011_TI1_RMP_GPIO               0
 416 #define  STM_TIM1011_TI1_RMP_LSI                1
 417 #define  STM_TIM1011_TI1_RMP_LSE                2
 418 #define  STM_TIM1011_TI1_RMP_RTC                3
 419 #define  STM_TIM1011_TI1_RMP_MASK               3
 420
 421 /* Flash interface */
 422
 423 struct stm_flash {
 424         vuint32_t       acr;
 425         vuint32_t       pecr;
 426         vuint32_t       pdkeyr;
 427         vuint32_t       pekeyr;
 428
 429         vuint32_t       prgkeyr;
 430         vuint32_t       optkeyr;
 431         vuint32_t       sr;
 432         vuint32_t       obr;
 433
 434         vuint32_t       wrpr;
 435 };
 436
 437 extern struct stm_flash stm_flash;
 438
 439 #define STM_FLASH_ACR_RUN_PD    (4)
 440 #define STM_FLASH_ACR_SLEEP_PD  (3)
 441 #define STM_FLASH_ACR_ACC64     (2)
 442 #define STM_FLASH_ACR_PRFEN     (1)
 443 #define STM_FLASH_ACR_LATENCY   (0)
 444
 445 #define STM_FLASH_PECR_OBL_LAUNCH       18
 446 #define STM_FLASH_PECR_ERRIE            17
 447 #define STM_FLASH_PECR_EOPIE            16
 448 #define STM_FLASH_PECR_FPRG             10
 449 #define STM_FLASH_PECR_ERASE            9
 450 #define STM_FLASH_PECR_FTDW             8
 451 #define STM_FLASH_PECR_DATA             4
 452 #define STM_FLASH_PECR_PROG             3
 453 #define STM_FLASH_PECR_OPTLOCK          2
 454 #define STM_FLASH_PECR_PRGLOCK          1
 455 #define STM_FLASH_PECR_PELOCK           0
 456
 457 #define STM_FLASH_SR_OPTVERR            11
 458 #define STM_FLASH_SR_SIZERR             10
 459 #define STM_FLASH_SR_PGAERR             9
 460 #define STM_FLASH_SR_WRPERR             8
 461 #define STM_FLASH_SR_READY              3
 462 #define STM_FLASH_SR_ENDHV              2
 463 #define STM_FLASH_SR_EOP                1
 464 #define STM_FLASH_SR_BSY                0
 465
 466 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
 467 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
 468
 469 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
 470 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
 471
 472 struct stm_rcc {
 473         vuint32_t       cr;
 474         vuint32_t       icscr;
 475         vuint32_t       cfgr;
 476         vuint32_t       cir;
 477
 478         vuint32_t       ahbrstr;
 479         vuint32_t       apb2rstr;
 480         vuint32_t       apb1rstr;
 481         vuint32_t       ahbenr;
 482
 483         vuint32_t       apb2enr;
 484         vuint32_t       apb1enr;
 485         vuint32_t       ahblenr;
 486         vuint32_t       apb2lpenr;
 487
 488         vuint32_t       apb1lpenr;
 489         vuint32_t       csr;
 490 };
 491
 492 extern struct stm_rcc stm_rcc;
 493
 494 /* Nominal high speed internal oscillator frequency is 16MHz */
 495 #define STM_HSI_FREQ            16000000
 496
 497 #define STM_RCC_CR_RTCPRE       (29)
 498 #define  STM_RCC_CR_RTCPRE_HSE_DIV_2    0
 499 #define  STM_RCC_CR_RTCPRE_HSE_DIV_4    1
 500 #define  STM_RCC_CR_RTCPRE_HSE_DIV_8    2
 501 #define  STM_RCC_CR_RTCPRE_HSE_DIV_16   3
 502 #define  STM_RCC_CR_RTCPRE_HSE_MASK     3
 503
 504 #define STM_RCC_CR_CSSON        (28)
 505 #define STM_RCC_CR_PLLRDY       (25)
 506 #define STM_RCC_CR_PLLON        (24)
 507 #define STM_RCC_CR_HSEBYP       (18)
 508 #define STM_RCC_CR_HSERDY       (17)
 509 #define STM_RCC_CR_HSEON        (16)
 510 #define STM_RCC_CR_MSIRDY       (9)
 511 #define STM_RCC_CR_MSION        (8)
 512 #define STM_RCC_CR_HSIRDY       (1)
 513 #define STM_RCC_CR_HSION        (0)
 514
 515 #define STM_RCC_CFGR_MCOPRE     (28)
 516 #define  STM_RCC_CFGR_MCOPRE_DIV_1      0
 517 #define  STM_RCC_CFGR_MCOPRE_DIV_2      1
 518 #define  STM_RCC_CFGR_MCOPRE_DIV_4      2
 519 #define  STM_RCC_CFGR_MCOPRE_DIV_8      3
 520 #define  STM_RCC_CFGR_MCOPRE_DIV_16     4
 521 #define  STM_RCC_CFGR_MCOPRE_DIV_MASK   7
 522
 523 #define STM_RCC_CFGR_MCOSEL     (24)
 524 #define  STM_RCC_CFGR_MCOSEL_DISABLE    0
 525 #define  STM_RCC_CFGR_MCOSEL_SYSCLK     1
 526 #define  STM_RCC_CFGR_MCOSEL_HSI        2
 527 #define  STM_RCC_CFGR_MCOSEL_MSI        3
 528 #define  STM_RCC_CFGR_MCOSEL_HSE        4
 529 #define  STM_RCC_CFGR_MCOSEL_PLL        5
 530 #define  STM_RCC_CFGR_MCOSEL_LSI        6
 531 #define  STM_RCC_CFGR_MCOSEL_LSE        7
 532 #define  STM_RCC_CFGR_MCOSEL_MASK       7
 533
 534 #define STM_RCC_CFGR_PLLDIV     (22)
 535 #define  STM_RCC_CFGR_PLLDIV_2          1
 536 #define  STM_RCC_CFGR_PLLDIV_3          2
 537 #define  STM_RCC_CFGR_PLLDIV_4          3
 538 #define  STM_RCC_CFGR_PLLDIV_MASK       3
 539
 540 #define STM_RCC_CFGR_PLLMUL     (18)
 541 #define  STM_RCC_CFGR_PLLMUL_3          0
 542 #define  STM_RCC_CFGR_PLLMUL_4          1
 543 #define  STM_RCC_CFGR_PLLMUL_6          2
 544 #define  STM_RCC_CFGR_PLLMUL_8          3
 545 #define  STM_RCC_CFGR_PLLMUL_12         4
 546 #define  STM_RCC_CFGR_PLLMUL_16         5
 547 #define  STM_RCC_CFGR_PLLMUL_24         6
 548 #define  STM_RCC_CFGR_PLLMUL_32         7
 549 #define  STM_RCC_CFGR_PLLMUL_48         8
 550 #define  STM_RCC_CFGR_PLLMUL_MASK       0xf
 551
 552 #define STM_RCC_CFGR_PLLSRC     (16)
 553
 554 #define STM_RCC_CFGR_PPRE2      (11)
 555 #define  STM_RCC_CFGR_PPRE2_DIV_1       0
 556 #define  STM_RCC_CFGR_PPRE2_DIV_2       4
 557 #define  STM_RCC_CFGR_PPRE2_DIV_4       5
 558 #define  STM_RCC_CFGR_PPRE2_DIV_8       6
 559 #define  STM_RCC_CFGR_PPRE2_DIV_16      7
 560 #define  STM_RCC_CFGR_PPRE2_MASK        7
 561
 562 #define STM_RCC_CFGR_PPRE1      (8)
 563 #define  STM_RCC_CFGR_PPRE1_DIV_1       0
 564 #define  STM_RCC_CFGR_PPRE1_DIV_2       4
 565 #define  STM_RCC_CFGR_PPRE1_DIV_4       5
 566 #define  STM_RCC_CFGR_PPRE1_DIV_8       6
 567 #define  STM_RCC_CFGR_PPRE1_DIV_16      7
 568 #define  STM_RCC_CFGR_PPRE1_MASK        7
 569
 570 #define STM_RCC_CFGR_HPRE       (4)
 571 #define  STM_RCC_CFGR_HPRE_DIV_1        0
 572 #define  STM_RCC_CFGR_HPRE_DIV_2        8
 573 #define  STM_RCC_CFGR_HPRE_DIV_4        9
 574 #define  STM_RCC_CFGR_HPRE_DIV_8        0xa
 575 #define  STM_RCC_CFGR_HPRE_DIV_16       0xb
 576 #define  STM_RCC_CFGR_HPRE_DIV_64       0xc
 577 #define  STM_RCC_CFGR_HPRE_DIV_128      0xd
 578 #define  STM_RCC_CFGR_HPRE_DIV_256      0xe
 579 #define  STM_RCC_CFGR_HPRE_DIV_512      0xf
 580 #define  STM_RCC_CFGR_HPRE_MASK         0xf
 581
 582 #define STM_RCC_CFGR_SWS        (2)
 583 #define  STM_RCC_CFGR_SWS_MSI           0
 584 #define  STM_RCC_CFGR_SWS_HSI           1
 585 #define  STM_RCC_CFGR_SWS_HSE           2
 586 #define  STM_RCC_CFGR_SWS_PLL           3
 587 #define  STM_RCC_CFGR_SWS_MASK          3
 588
 589 #define STM_RCC_CFGR_SW         (0)
 590 #define  STM_RCC_CFGR_SW_MSI            0
 591 #define  STM_RCC_CFGR_SW_HSI            1
 592 #define  STM_RCC_CFGR_SW_HSE            2
 593 #define  STM_RCC_CFGR_SW_PLL            3
 594 #define  STM_RCC_CFGR_SW_MASK           3
 595
 596 #define STM_RCC_AHBENR_DMA1EN           (24)
 597 #define STM_RCC_AHBENR_FLITFEN          (15)
 598 #define STM_RCC_AHBENR_CRCEN            (12)
 599 #define STM_RCC_AHBENR_GPIOHEN          (5)
 600 #define STM_RCC_AHBENR_GPIOEEN          (4)
 601 #define STM_RCC_AHBENR_GPIODEN          (3)
 602 #define STM_RCC_AHBENR_GPIOCEN          (2)
 603 #define STM_RCC_AHBENR_GPIOBEN          (1)
 604 #define STM_RCC_AHBENR_GPIOAEN          (0)
 605
 606 #define STM_RCC_APB2ENR_USART1EN        (14)
 607 #define STM_RCC_APB2ENR_SPI1EN          (12)
 608 #define STM_RCC_APB2ENR_ADC1EN          (9)
 609 #define STM_RCC_APB2ENR_TIM11EN         (4)
 610 #define STM_RCC_APB2ENR_TIM10EN         (3)
 611 #define STM_RCC_APB2ENR_TIM9EN          (2)
 612 #define STM_RCC_APB2ENR_SYSCFGEN        (0)
 613
 614 #define STM_RCC_APB1ENR_COMPEN          (31)
 615 #define STM_RCC_APB1ENR_DACEN           (29)
 616 #define STM_RCC_APB1ENR_PWREN           (28)
 617 #define STM_RCC_APB1ENR_USBEN           (23)
 618 #define STM_RCC_APB1ENR_I2C2EN          (22)
 619 #define STM_RCC_APB1ENR_I2C1EN          (21)
 620 #define STM_RCC_APB1ENR_USART3EN        (18)
 621 #define STM_RCC_APB1ENR_USART2EN        (17)
 622 #define STM_RCC_APB1ENR_SPI2EN          (14)
 623 #define STM_RCC_APB1ENR_WWDGEN          (11)
 624 #define STM_RCC_APB1ENR_LCDEN           (9)
 625 #define STM_RCC_APB1ENR_TIM7EN          (5)
 626 #define STM_RCC_APB1ENR_TIM6EN          (4)
 627 #define STM_RCC_APB1ENR_TIM4EN          (2)
 628 #define STM_RCC_APB1ENR_TIM3EN          (1)
 629 #define STM_RCC_APB1ENR_TIM2EN          (0)
 630
 631 #define STM_RCC_CSR_LPWRRSTF            (31)
 632 #define STM_RCC_CSR_WWDGRSTF            (30)
 633 #define STM_RCC_CSR_IWDGRSTF            (29)
 634 #define STM_RCC_CSR_SFTRSTF             (28)
 635 #define STM_RCC_CSR_PORRSTF             (27)
 636 #define STM_RCC_CSR_PINRSTF             (26)
 637 #define STM_RCC_CSR_OBLRSTF             (25)
 638 #define STM_RCC_CSR_RMVF                (24)
 639 #define STM_RCC_CSR_RTFRST              (23)
 640 #define STM_RCC_CSR_RTCEN               (22)
 641 #define STM_RCC_CSR_RTCSEL              (16)
 642
 643 #define  STM_RCC_CSR_RTCSEL_NONE                0
 644 #define  STM_RCC_CSR_RTCSEL_LSE                 1
 645 #define  STM_RCC_CSR_RTCSEL_LSI                 2
 646 #define  STM_RCC_CSR_RTCSEL_HSE                 3
 647 #define  STM_RCC_CSR_RTCSEL_MASK                3
 648
 649 #define STM_RCC_CSR_LSEBYP              (10)
 650 #define STM_RCC_CSR_LSERDY              (9)
 651 #define STM_RCC_CSR_LSEON               (8)
 652 #define STM_RCC_CSR_LSIRDY              (1)
 653 #define STM_RCC_CSR_LSION               (0)
 654
 655 struct stm_pwr {
 656         vuint32_t       cr;
 657         vuint32_t       csr;
 658 };
 659
 660 extern struct stm_pwr stm_pwr;
 661
 662 #define STM_PWR_CR_LPRUN        (14)
 663
 664 #define STM_PWR_CR_VOS          (11)
 665 #define  STM_PWR_CR_VOS_1_8             1
 666 #define  STM_PWR_CR_VOS_1_5             2
 667 #define  STM_PWR_CR_VOS_1_2             3
 668 #define  STM_PWR_CR_VOS_MASK            3
 669
 670 #define STM_PWR_CR_FWU          (10)
 671 #define STM_PWR_CR_ULP          (9)
 672 #define STM_PWR_CR_DBP          (8)
 673
 674 #define STM_PWR_CR_PLS          (5)
 675 #define  STM_PWR_CR_PLS_1_9     0
 676 #define  STM_PWR_CR_PLS_2_1     1
 677 #define  STM_PWR_CR_PLS_2_3     2
 678 #define  STM_PWR_CR_PLS_2_5     3
 679 #define  STM_PWR_CR_PLS_2_7     4
 680 #define  STM_PWR_CR_PLS_2_9     5
 681 #define  STM_PWR_CR_PLS_3_1     6
 682 #define  STM_PWR_CR_PLS_EXT     7
 683 #define  STM_PWR_CR_PLS_MASK    7
 684
 685 #define STM_PWR_CR_PVDE         (4)
 686 #define STM_PWR_CR_CSBF         (3)
 687 #define STM_PWR_CR_CWUF         (2)
 688 #define STM_PWR_CR_PDDS         (1)
 689 #define STM_PWR_CR_LPSDSR       (0)
 690
 691 #define STM_PWR_CSR_EWUP3       (10)
 692 #define STM_PWR_CSR_EWUP2       (9)
 693 #define STM_PWR_CSR_EWUP1       (8)
 694 #define STM_PWR_CSR_REGLPF      (5)
 695 #define STM_PWR_CSR_VOSF        (4)
 696 #define STM_PWR_CSR_VREFINTRDYF (3)
 697 #define STM_PWR_CSR_PVDO        (2)
 698 #define STM_PWR_CSR_SBF         (1)
 699 #define STM_PWR_CSR_WUF         (0)
 700
 701 struct stm_tim67 {
 702         vuint32_t       cr1;
 703         vuint32_t       cr2;
 704         uint32_t        _unused_08;
 705         vuint32_t       dier;
 706
 707         vuint32_t       sr;
 708         vuint32_t       egr;
 709         uint32_t        _unused_18;
 710         uint32_t        _unused_1c;
 711
 712         uint32_t        _unused_20;
 713         vuint32_t       cnt;
 714         vuint32_t       psc;
 715         vuint32_t       arr;
 716 };
 717
 718 extern struct stm_tim67 stm_tim6;
 719
 720 #define STM_TIM67_CR1_ARPE      (7)
 721 #define STM_TIM67_CR1_OPM       (3)
 722 #define STM_TIM67_CR1_URS       (2)
 723 #define STM_TIM67_CR1_UDIS      (1)
 724 #define STM_TIM67_CR1_CEN       (0)
 725
 726 #define STM_TIM67_CR2_MMS       (4)
 727 #define  STM_TIM67_CR2_MMS_RESET        0
 728 #define  STM_TIM67_CR2_MMS_ENABLE       1
 729 #define  STM_TIM67_CR2_MMS_UPDATE       2
 730 #define  STM_TIM67_CR2_MMS_MASK         7
 731
 732 #define STM_TIM67_DIER_UDE      (8)
 733 #define STM_TIM67_DIER_UIE      (0)
 734
 735 #define STM_TIM67_SR_UIF        (0)
 736
 737 #define STM_TIM67_EGR_UG        (0)
 738
 739 struct stm_lcd {
 740         vuint32_t       cr;
 741         vuint32_t       fcr;
 742         vuint32_t       sr;
 743         vuint32_t       clr;
 744         uint32_t        unused_0x10;
 745         vuint32_t       ram[8*2];
 746 };
 747
 748 extern struct stm_lcd stm_lcd;
 749
 750 #define STM_LCD_CR_MUX_SEG              (7)
 751
 752 #define STM_LCD_CR_BIAS                 (5)
 753 #define  STM_LCD_CR_BIAS_1_4            0
 754 #define  STM_LCD_CR_BIAS_1_2            1
 755 #define  STM_LCD_CR_BIAS_1_3            2
 756 #define  STM_LCD_CR_BIAS_MASK           3
 757
 758 #define STM_LCD_CR_DUTY                 (2)
 759 #define  STM_LCD_CR_DUTY_STATIC         0
 760 #define  STM_LCD_CR_DUTY_1_2            1
 761 #define  STM_LCD_CR_DUTY_1_3            2
 762 #define  STM_LCD_CR_DUTY_1_4            3
 763 #define  STM_LCD_CR_DUTY_1_8            4
 764 #define  STM_LCD_CR_DUTY_MASK           7
 765
 766 #define STM_LCD_CR_VSEL                 (1)
 767 #define STM_LCD_CR_LCDEN                (0)
 768
 769 #define STM_LCD_FCR_PS                  (22)
 770 #define  STM_LCD_FCR_PS_1               0x0
 771 #define  STM_LCD_FCR_PS_2               0x1
 772 #define  STM_LCD_FCR_PS_4               0x2
 773 #define  STM_LCD_FCR_PS_8               0x3
 774 #define  STM_LCD_FCR_PS_16              0x4
 775 #define  STM_LCD_FCR_PS_32              0x5
 776 #define  STM_LCD_FCR_PS_64              0x6
 777 #define  STM_LCD_FCR_PS_128             0x7
 778 #define  STM_LCD_FCR_PS_256             0x8
 779 #define  STM_LCD_FCR_PS_512             0x9
 780 #define  STM_LCD_FCR_PS_1024            0xa
 781 #define  STM_LCD_FCR_PS_2048            0xb
 782 #define  STM_LCD_FCR_PS_4096            0xc
 783 #define  STM_LCD_FCR_PS_8192            0xd
 784 #define  STM_LCD_FCR_PS_16384           0xe
 785 #define  STM_LCD_FCR_PS_32768           0xf
 786 #define  STM_LCD_FCR_PS_MASK            0xf
 787
 788 #define STM_LCD_FCR_DIV                 (18)
 789 #define STM_LCD_FCR_DIV_16              0x0
 790 #define STM_LCD_FCR_DIV_17              0x1
 791 #define STM_LCD_FCR_DIV_18              0x2
 792 #define STM_LCD_FCR_DIV_19              0x3
 793 #define STM_LCD_FCR_DIV_20              0x4
 794 #define STM_LCD_FCR_DIV_21              0x5
 795 #define STM_LCD_FCR_DIV_22              0x6
 796 #define STM_LCD_FCR_DIV_23              0x7
 797 #define STM_LCD_FCR_DIV_24              0x8
 798 #define STM_LCD_FCR_DIV_25              0x9
 799 #define STM_LCD_FCR_DIV_26              0xa
 800 #define STM_LCD_FCR_DIV_27              0xb
 801 #define STM_LCD_FCR_DIV_28              0xc
 802 #define STM_LCD_FCR_DIV_29              0xd
 803 #define STM_LCD_FCR_DIV_30              0xe
 804 #define STM_LCD_FCR_DIV_31              0xf
 805 #define STM_LCD_FCR_DIV_MASK            0xf
 806
 807 #define STM_LCD_FCR_BLINK               (16)
 808 #define  STM_LCD_FCR_BLINK_DISABLE              0
 809 #define  STM_LCD_FCR_BLINK_SEG0_COM0            1
 810 #define  STM_LCD_FCR_BLINK_SEG0_COMALL          2
 811 #define  STM_LCD_FCR_BLINK_SEGALL_COMALL        3
 812 #define  STM_LCD_FCR_BLINK_MASK                 3
 813
 814 #define STM_LCD_FCR_BLINKF              (13)
 815 #define  STM_LCD_FCR_BLINKF_8                   0
 816 #define  STM_LCD_FCR_BLINKF_16                  1
 817 #define  STM_LCD_FCR_BLINKF_32                  2
 818 #define  STM_LCD_FCR_BLINKF_64                  3
 819 #define  STM_LCD_FCR_BLINKF_128                 4
 820 #define  STM_LCD_FCR_BLINKF_256                 5
 821 #define  STM_LCD_FCR_BLINKF_512                 6
 822 #define  STM_LCD_FCR_BLINKF_1024                7
 823 #define  STM_LCD_FCR_BLINKF_MASK                7
 824
 825 #define STM_LCD_FCR_CC                  (10)
 826 #define  STM_LCD_FCR_CC_MASK                    7
 827
 828 #define STM_LCD_FCR_DEAD                (7)
 829 #define  STM_LCD_FCR_DEAD_MASK                  7
 830
 831 #define STM_LCD_FCR_PON                 (4)
 832 #define  STM_LCD_FCR_PON_MASK                   7
 833
 834 #define STM_LCD_FCR_UDDIE               (3)
 835 #define STM_LCD_FCR_SOFIE               (1)
 836 #define STM_LCD_FCR_HD                  (0)
 837
 838 #define STM_LCD_SR_FCRSF                (5)
 839 #define STM_LCD_SR_RDY                  (4)
 840 #define STM_LCD_SR_UDD                  (3)
 841 #define STM_LCD_SR_UDR                  (2)
 842 #define STM_LCD_SR_SOF                  (1)
 843 #define STM_LCD_SR_ENS                  (0)
 844
 845 #define STM_LCD_CLR_UDDC                (3)
 846 #define STM_LCD_CLR_SOFC                (1)
 847
 848 /* The SYSTICK starts at 0xe000e010 */
 849
 850 struct stm_systick {
 851         vuint32_t       csr;
 852         vuint32_t       rvr;
 853         vuint32_t       cvr;
 854         vuint32_t       calib;
 855 };
 856
 857 extern struct stm_systick stm_systick;
 858
 859 #define STM_SYSTICK_CSR_ENABLE          0
 860 #define STM_SYSTICK_CSR_TICKINT         1
 861 #define STM_SYSTICK_CSR_CLKSOURCE       2
 862 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK_8               0
 863 #define  STM_SYSTICK_CSR_CLKSOURCE_HCLK                 1
 864 #define STM_SYSTICK_CSR_COUNTFLAG       16
 865
 866 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
 867
 868 struct stm_nvic {
 869         vuint32_t       iser[8];        /* 0x000 0xe000e100 Set Enable Register */
 870
 871         uint8_t         _unused020[0x080 - 0x020];
 872
 873         vuint32_t       icer[8];        /* 0x080 0xe000e180 Clear Enable Register */
 874
 875         uint8_t         _unused0a0[0x100 - 0x0a0];
 876
 877         vuint32_t       ispr[8];        /* 0x100 0xe000e200 Set Pending Register */
 878
 879         uint8_t         _unused120[0x180 - 0x120];
 880
 881         vuint32_t       icpr[8];        /* 0x180 0xe000e280 Clear Pending Register */
 882
 883         uint8_t         _unused1a0[0x200 - 0x1a0];
 884
 885         vuint32_t       iabr[8];        /* 0x200 0xe000e300 Active Bit Register */
 886
 887         uint8_t         _unused220[0x300 - 0x220];
 888
 889         vuint32_t       ipr[60];        /* 0x300 0xe000e400 Priority Register */
 890
 891         uint8_t         _unused3f0[0xc00 - 0x3f0];
 892
 893         vuint32_t       cpuid_base;     /* 0xc00 0xe000ed00 CPUID Base Register */
 894         vuint32_t       ics;            /* 0xc04 0xe000ed04 Interrupt Control State Register */
 895         vuint32_t       vto;            /* 0xc08 0xe000ed08 Vector Table Offset Register */
 896         vuint32_t       ai_rc;          /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
 897         vuint32_t       sc;             /* 0xc10 0xe000ed10 System Control Register */
 898         vuint32_t       cc;             /* 0xc14 0xe000ed14 Configuration Control Register */
 899
 900         uint8_t         _unusedc18[0xe00 - 0xc18];
 901
 902         vuint32_t       stir;           /* 0xe00 */
 903 };
 904
 905 extern struct stm_nvic stm_nvic;
 906
 907 #define IRQ_REG(irq)    ((irq) >> 5)
 908 #define IRQ_BIT(irq)    ((irq) & 0x1f)
 909 #define IRQ_MASK(irq)   (1 << IRQ_BIT(irq))
 910 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
 911
 912 static inline void
 913 stm_nvic_set_enable(int irq) {
 914         stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
 915 }
 916
 917 static inline void
 918 stm_nvic_clear_enable(int irq) {
 919         stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
 920 }
 921
 922 static inline int
 923 stm_nvic_enabled(int irq) {
 924         return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
 925 }
 926
 927 static inline void
 928 stm_nvic_set_pending(int irq) {
 929         stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
 930 }
 931
 932 static inline void
 933 stm_nvic_clear_pending(int irq) {
 934         stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
 935 }
 936
 937 static inline int
 938 stm_nvic_pending(int irq) {
 939         return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
 940 }
 941
 942 static inline int
 943 stm_nvic_active(int irq) {
 944         return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
 945 }
 946
 947 #define IRQ_PRIO_REG(irq)       ((irq) >> 2)
 948 #define IRQ_PRIO_BIT(irq)       (((irq) & 3) << 3)
 949 #define IRQ_PRIO_MASK(irq)      (0xff << IRQ_PRIO_BIT(irq))
 950
 951 static inline void
 952 stm_nvic_set_priority(int irq, uint8_t prio) {
 953         int             n = IRQ_PRIO_REG(irq);
 954         uint32_t        v;
 955
 956         v = stm_nvic.ipr[n];
 957         v &= ~IRQ_PRIO_MASK(irq);
 958         v |= (prio) << IRQ_PRIO_BIT(irq);
 959         stm_nvic.ipr[n] = v;
 960 }
 961
 962 static inline uint8_t
 963 stm_nvic_get_priority(int irq) {
 964         return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
 965 }
 966
 967 struct stm_scb {
 968         vuint32_t       cpuid;
 969         vuint32_t       icsr;
 970         vuint32_t       vtor;
 971         vuint32_t       aircr;
 972
 973         vuint32_t       scr;
 974         vuint32_t       ccr;
 975         vuint32_t       shpr1;
 976         vuint32_t       shpr2;
 977
 978         vuint32_t       shpr3;
 979         vuint32_t       shcrs;
 980         vuint32_t       cfsr;
 981         vuint32_t       hfsr;
 982
 983         uint32_t        unused_30;
 984         vuint32_t       mmfar;
 985         vuint32_t       bfar;
 986 };
 987
 988 extern struct stm_scb stm_scb;
 989
 990 #define STM_SCB_AIRCR_VECTKEY           16
 991 #define  STM_SCB_AIRCR_VECTKEY_KEY              0x05fa
 992 #define STM_SCB_AIRCR_PRIGROUP          8
 993 #define STM_SCB_AIRCR_SYSRESETREQ       2
 994 #define STM_SCB_AIRCR_VECTCLRACTIVE     1
 995 #define STM_SCB_AIRCR_VECTRESET         0
 996
 997 struct stm_mpu {
 998         vuint32_t       typer;
 999         vuint32_t       cr;
1000         vuint32_t       rnr;
1001         vuint32_t       rbar;
1002
1003         vuint32_t       rasr;
1004         vuint32_t       rbar_a1;
1005         vuint32_t       rasr_a1;
1006         vuint32_t       rbar_a2;
1007         vuint32_t       rasr_a2;
1008         vuint32_t       rbar_a3;
1009         vuint32_t       rasr_a3;
1010 };
1011
1012 extern struct stm_mpu stm_mpu;
1013
1014 #define STM_MPU_TYPER_IREGION   16
1015 #define  STM_MPU_TYPER_IREGION_MASK     0xff
1016 #define STM_MPU_TYPER_DREGION   8
1017 #define  STM_MPU_TYPER_DREGION_MASK     0xff
1018 #define STM_MPU_TYPER_SEPARATE  0
1019
1020 #define STM_MPU_CR_PRIVDEFENA   2
1021 #define STM_MPU_CR_HFNMIENA     1
1022 #define STM_MPU_CR_ENABLE       0
1023
1024 #define STM_MPU_RNR_REGION      0
1025 #define STM_MPU_RNR_REGION_MASK         0xff
1026
1027 #define STM_MPU_RBAR_ADDR       5
1028 #define STM_MPU_RBAR_ADDR_MASK          0x7ffffff
1029
1030 #define STM_MPU_RBAR_VALID      4
1031 #define STM_MPU_RBAR_REGION     0
1032 #define STM_MPU_RBAR_REGION_MASK        0xf
1033
1034 #define STM_MPU_RASR_XN         28
1035 #define STM_MPU_RASR_AP         24
1036 #define  STM_MPU_RASR_AP_NONE_NONE      0
1037 #define  STM_MPU_RASR_AP_RW_NONE        1
1038 #define  STM_MPU_RASR_AP_RW_RO          2
1039 #define  STM_MPU_RASR_AP_RW_RW          3
1040 #define  STM_MPU_RASR_AP_RO_NONE        5
1041 #define  STM_MPU_RASR_AP_RO_RO          6
1042 #define  STM_MPU_RASR_AP_MASK           7
1043 #define STM_MPU_RASR_TEX        19
1044 #define  STM_MPU_RASR_TEX_MASK          7
1045 #define STM_MPU_RASR_S          18
1046 #define STM_MPU_RASR_C          17
1047 #define STM_MPU_RASR_B          16
1048 #define STM_MPU_RASR_SRD        8
1049 #define  STM_MPU_RASR_SRD_MASK          0xff
1050 #define STM_MPU_RASR_SIZE       1
1051 #define  STM_MPU_RASR_SIZE_MASK         0x1f
1052 #define STM_MPU_RASR_ENABLE     0
1053
1054 #define isr(name) void stm_ ## name ## _isr(void);
1055
1056 isr(nmi)
1057 isr(hardfault)
1058 isr(memmanage)
1059 isr(busfault)
1060 isr(usagefault)
1061 isr(svc)
1062 isr(debugmon)
1063 isr(pendsv)
1064 isr(systick)
1065 isr(wwdg)
1066 isr(pvd)
1067 isr(tamper_stamp)
1068 isr(rtc_wkup)
1069 isr(flash)
1070 isr(rcc)
1071 isr(exti0)
1072 isr(exti1)
1073 isr(exti2)
1074 isr(exti3)
1075 isr(exti4)
1076 isr(dma1_channel1)
1077 isr(dma1_channel2)
1078 isr(dma1_channel3)
1079 isr(dma1_channel4)
1080 isr(dma1_channel5)
1081 isr(dma1_channel6)
1082 isr(dma1_channel7)
1083 isr(adc1)
1084 isr(usb_hp)
1085 isr(usb_lp)
1086 isr(dac)
1087 isr(comp)
1088 isr(exti9_5)
1089 isr(lcd)
1090 isr(tim9)
1091 isr(tim10)
1092 isr(tim11)
1093 isr(tim2)
1094 isr(tim3)
1095 isr(tim4)
1096 isr(i2c1_ev)
1097 isr(i2c1_er)
1098 isr(i2c2_ev)
1099 isr(i2c2_er)
1100 isr(spi1)
1101 isr(spi2)
1102 isr(usart1)
1103 isr(usart2)
1104 isr(usart3)
1105 isr(exti15_10)
1106 isr(rtc_alarm)
1107 isr(usb_fs_wkup)
1108 isr(tim6)
1109 isr(tim7)
1110
1111 #undef isr
1112
1113 #define STM_ISR_WWDG_POS                0
1114 #define STM_ISR_PVD_POS                 1
1115 #define STM_ISR_TAMPER_STAMP_POS        2
1116 #define STM_ISR_RTC_WKUP_POS            3
1117 #define STM_ISR_FLASH_POS               4
1118 #define STM_ISR_RCC_POS                 5
1119 #define STM_ISR_EXTI0_POS               6
1120 #define STM_ISR_EXTI1_POS               7
1121 #define STM_ISR_EXTI2_POS               8
1122 #define STM_ISR_EXTI3_POS               9
1123 #define STM_ISR_EXTI4_POS               10
1124 #define STM_ISR_DMA1_CHANNEL1_POS       11
1125 #define STM_ISR_DMA2_CHANNEL1_POS       12
1126 #define STM_ISR_DMA3_CHANNEL1_POS       13
1127 #define STM_ISR_DMA4_CHANNEL1_POS       14
1128 #define STM_ISR_DMA5_CHANNEL1_POS       15
1129 #define STM_ISR_DMA6_CHANNEL1_POS       16
1130 #define STM_ISR_DMA7_CHANNEL1_POS       17
1131 #define STM_ISR_ADC1_POS                18
1132 #define STM_ISR_USB_HP_POS              19
1133 #define STM_ISR_USB_LP_POS              20
1134 #define STM_ISR_DAC_POS                 21
1135 #define STM_ISR_COMP_POS                22
1136 #define STM_ISR_EXTI9_5_POS             23
1137 #define STM_ISR_LCD_POS                 24
1138 #define STM_ISR_TIM9_POS                25
1139 #define STM_ISR_TIM10_POS               26
1140 #define STM_ISR_TIM11_POS               27
1141 #define STM_ISR_TIM2_POS                28
1142 #define STM_ISR_TIM3_POS                29
1143 #define STM_ISR_TIM4_POS                30
1144 #define STM_ISR_I2C1_EV_POS             31
1145 #define STM_ISR_I2C1_ER_POS             32
1146 #define STM_ISR_I2C2_EV_POS             33
1147 #define STM_ISR_I2C2_ER_POS             34
1148 #define STM_ISR_SPI1_POS                35
1149 #define STM_ISR_SPI2_POS                36
1150 #define STM_ISR_USART1_POS              37
1151 #define STM_ISR_USART2_POS              38
1152 #define STM_ISR_USART3_POS              39
1153 #define STM_ISR_EXTI15_10_POS           40
1154 #define STM_ISR_RTC_ALARM_POS           41
1155 #define STM_ISR_USB_FS_WKUP_POS         42
1156 #define STM_ISR_TIM6_POS                43
1157 #define STM_ISR_TIM7_POS                44
1158
1159 struct stm_syscfg {
1160         vuint32_t       memrmp;
1161         vuint32_t       pmc;
1162         vuint32_t       exticr[4];
1163 };
1164
1165 extern struct stm_syscfg stm_syscfg;
1166
1167 #define STM_SYSCFG_MEMRMP_MEM_MODE      0
1168 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH          0
1169 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH        1
1170 #define  STM_SYSCFG_MEMRMP_MEM_MODE_SRAM                3
1171 #define  STM_SYSCFG_MEMRMP_MEM_MODE_MASK                3
1172
1173 #define STM_SYSCFG_PMC_USB_PU           0
1174
1175 #define STM_SYSCFG_EXTICR_PA            0
1176 #define STM_SYSCFG_EXTICR_PB            1
1177 #define STM_SYSCFG_EXTICR_PC            2
1178 #define STM_SYSCFG_EXTICR_PD            3
1179 #define STM_SYSCFG_EXTICR_PE            4
1180 #define STM_SYSCFG_EXTICR_PH            5
1181
1182 static inline void
1183 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1184         uint8_t reg = pin >> 2;
1185         uint8_t shift = (pin & 3) << 2;
1186         uint8_t val = 0;
1187
1188         /* Enable SYSCFG */
1189         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1190
1191         if (gpio == &stm_gpioa)
1192                 val = STM_SYSCFG_EXTICR_PA;
1193         else if (gpio == &stm_gpiob)
1194                 val = STM_SYSCFG_EXTICR_PB;
1195         else if (gpio == &stm_gpioc)
1196                 val = STM_SYSCFG_EXTICR_PC;
1197         else if (gpio == &stm_gpiod)
1198                 val = STM_SYSCFG_EXTICR_PD;
1199         else if (gpio == &stm_gpioe)
1200                 val = STM_SYSCFG_EXTICR_PE;
1201
1202         stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1203 }
1204
1205
1206 struct stm_dma_channel {
1207         vuint32_t       ccr;
1208         vuint32_t       cndtr;
1209         vvoid_t         cpar;
1210         vvoid_t         cmar;
1211         vuint32_t       reserved;
1212 };
1213
1214 #define STM_NUM_DMA     7
1215
1216 struct stm_dma {
1217         vuint32_t               isr;
1218         vuint32_t               ifcr;
1219         struct stm_dma_channel  channel[STM_NUM_DMA];
1220 };
1221
1222 extern struct stm_dma stm_dma;
1223
1224 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1225  */
1226
1227 #define STM_DMA_INDEX(channel)          ((channel) - 1)
1228
1229 #define STM_DMA_ISR(index)              ((index) << 2)
1230 #define STM_DMA_ISR_MASK                        0xf
1231 #define STM_DMA_ISR_TEIF                        3
1232 #define STM_DMA_ISR_HTIF                        2
1233 #define STM_DMA_ISR_TCIF                        1
1234 #define STM_DMA_ISR_GIF                         0
1235
1236 #define STM_DMA_IFCR(index)             ((index) << 2)
1237 #define STM_DMA_IFCR_MASK                       0xf
1238 #define STM_DMA_IFCR_CTEIF                      3
1239 #define STM_DMA_IFCR_CHTIF                      2
1240 #define STM_DMA_IFCR_CTCIF                      1
1241 #define STM_DMA_IFCR_CGIF                       0
1242
1243 #define STM_DMA_CCR_MEM2MEM             (14)
1244
1245 #define STM_DMA_CCR_PL                  (12)
1246 #define  STM_DMA_CCR_PL_LOW                     (0)
1247 #define  STM_DMA_CCR_PL_MEDIUM                  (1)
1248 #define  STM_DMA_CCR_PL_HIGH                    (2)
1249 #define  STM_DMA_CCR_PL_VERY_HIGH               (3)
1250 #define  STM_DMA_CCR_PL_MASK                    (3)
1251
1252 #define STM_DMA_CCR_MSIZE               (10)
1253 #define  STM_DMA_CCR_MSIZE_8                    (0)
1254 #define  STM_DMA_CCR_MSIZE_16                   (1)
1255 #define  STM_DMA_CCR_MSIZE_32                   (2)
1256 #define  STM_DMA_CCR_MSIZE_MASK                 (3)
1257
1258 #define STM_DMA_CCR_PSIZE               (8)
1259 #define  STM_DMA_CCR_PSIZE_8                    (0)
1260 #define  STM_DMA_CCR_PSIZE_16                   (1)
1261 #define  STM_DMA_CCR_PSIZE_32                   (2)
1262 #define  STM_DMA_CCR_PSIZE_MASK                 (3)
1263
1264 #define STM_DMA_CCR_MINC                (7)
1265 #define STM_DMA_CCR_PINC                (6)
1266 #define STM_DMA_CCR_CIRC                (5)
1267 #define STM_DMA_CCR_DIR                 (4)
1268 #define  STM_DMA_CCR_DIR_PER_TO_MEM             0
1269 #define  STM_DMA_CCR_DIR_MEM_TO_PER             1
1270 #define STM_DMA_CCR_TEIE                (3)
1271 #define STM_DMA_CCR_HTIE                (2)
1272 #define STM_DMA_CCR_TCIE                (1)
1273 #define STM_DMA_CCR_EN                  (0)
1274
1275 #define STM_DMA_CHANNEL_ADC1            1
1276 #define STM_DMA_CHANNEL_SPI1_RX         2
1277 #define STM_DMA_CHANNEL_SPI1_TX         3
1278 #define STM_DMA_CHANNEL_SPI2_RX         4
1279 #define STM_DMA_CHANNEL_SPI2_TX         5
1280 #define STM_DMA_CHANNEL_USART3_TX       2
1281 #define STM_DMA_CHANNEL_USART3_RX       3
1282 #define STM_DMA_CHANNEL_USART1_TX       4
1283 #define STM_DMA_CHANNEL_USART1_RX       5
1284 #define STM_DMA_CHANNEL_USART2_RX       6
1285 #define STM_DMA_CHANNEL_USART2_TX       7
1286 #define STM_DMA_CHANNEL_I2C2_TX         4
1287 #define STM_DMA_CHANNEL_I2C2_RX         5
1288 #define STM_DMA_CHANNEL_I2C1_TX         6
1289 #define STM_DMA_CHANNEL_I2C1_RX         7
1290 #define STM_DMA_CHANNEL_TIM2_CH3        1
1291 #define STM_DMA_CHANNEL_TIM2_UP         2
1292 #define STM_DMA_CHANNEL_TIM2_CH1        5
1293 #define STM_DMA_CHANNEL_TIM2_CH2        7
1294 #define STM_DMA_CHANNEL_TIM2_CH4        7
1295 #define STM_DMA_CHANNEL_TIM3_CH3        2
1296 #define STM_DMA_CHANNEL_TIM3_CH4        3
1297 #define STM_DMA_CHANNEL_TIM3_UP         3
1298 #define STM_DMA_CHANNEL_TIM3_CH1        6
1299 #define STM_DMA_CHANNEL_TIM3_TRIG       6
1300 #define STM_DMA_CHANNEL_TIM4_CH1        1
1301 #define STM_DMA_CHANNEL_TIM4_CH2        4
1302 #define STM_DMA_CHANNEL_TIM4_CH3        5
1303 #define STM_DMA_CHANNEL_TIM4_UP         7
1304 #define STM_DMA_CHANNEL_TIM6_UP_DA      2
1305 #define STM_DMA_CHANNEL_C_CHANNEL1      2
1306 #define STM_DMA_CHANNEL_TIM7_UP_DA      3
1307 #define STM_DMA_CHANNEL_C_CHANNEL2      3
1308
1309 /*
1310  * Only spi channel 1 and 2 can use DMA
1311  */
1312 #define STM_NUM_SPI     2
1313
1314 struct stm_spi {
1315         vuint32_t       cr1;
1316         vuint32_t       cr2;
1317         vuint32_t       sr;
1318         vuint32_t       dr;
1319         vuint32_t       crcpr;
1320         vuint32_t       rxcrcr;
1321         vuint32_t       txcrcr;
1322 };
1323
1324 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1325
1326 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1327  */
1328
1329 #define STM_SPI_INDEX(channel)          ((channel) - 1)
1330
1331 #define STM_SPI_CR1_BIDIMODE            15
1332 #define STM_SPI_CR1_BIDIOE              14
1333 #define STM_SPI_CR1_CRCEN               13
1334 #define STM_SPI_CR1_CRCNEXT             12
1335 #define STM_SPI_CR1_DFF                 11
1336 #define STM_SPI_CR1_RXONLY              10
1337 #define STM_SPI_CR1_SSM                 9
1338 #define STM_SPI_CR1_SSI                 8
1339 #define STM_SPI_CR1_LSBFIRST            7
1340 #define STM_SPI_CR1_SPE                 6
1341 #define STM_SPI_CR1_BR                  3
1342 #define  STM_SPI_CR1_BR_PCLK_2                  0
1343 #define  STM_SPI_CR1_BR_PCLK_4                  1
1344 #define  STM_SPI_CR1_BR_PCLK_8                  2
1345 #define  STM_SPI_CR1_BR_PCLK_16                 3
1346 #define  STM_SPI_CR1_BR_PCLK_32                 4
1347 #define  STM_SPI_CR1_BR_PCLK_64                 5
1348 #define  STM_SPI_CR1_BR_PCLK_128                6
1349 #define  STM_SPI_CR1_BR_PCLK_256                7
1350 #define  STM_SPI_CR1_BR_MASK                    7
1351
1352 #define STM_SPI_CR1_MSTR                2
1353 #define STM_SPI_CR1_CPOL                1
1354 #define STM_SPI_CR1_CPHA                0
1355
1356 #define STM_SPI_CR2_TXEIE       7
1357 #define STM_SPI_CR2_RXNEIE      6
1358 #define STM_SPI_CR2_ERRIE       5
1359 #define STM_SPI_CR2_SSOE        2
1360 #define STM_SPI_CR2_TXDMAEN     1
1361 #define STM_SPI_CR2_RXDMAEN     0
1362
1363 #define STM_SPI_SR_FRE          8
1364 #define STM_SPI_SR_BSY          7
1365 #define STM_SPI_SR_OVR          6
1366 #define STM_SPI_SR_MODF         5
1367 #define STM_SPI_SR_CRCERR       4
1368 #define STM_SPI_SR_UDR          3
1369 #define STM_SPI_SR_CHSIDE       2
1370 #define STM_SPI_SR_TXE          1
1371 #define STM_SPI_SR_RXNE         0
1372
1373 struct stm_adc {
1374         vuint32_t       sr;
1375         vuint32_t       cr1;
1376         vuint32_t       cr2;
1377         vuint32_t       smpr1;
1378         vuint32_t       smpr2;
1379         vuint32_t       smpr3;
1380         vuint32_t       jofr1;
1381         vuint32_t       jofr2;
1382         vuint32_t       jofr3;
1383         vuint32_t       jofr4;
1384         vuint32_t       htr;
1385         vuint32_t       ltr;
1386         vuint32_t       sqr1;
1387         vuint32_t       sqr2;
1388         vuint32_t       sqr3;
1389         vuint32_t       sqr4;
1390         vuint32_t       sqr5;
1391         vuint32_t       jsqr;
1392         vuint32_t       jdr1;
1393         vuint32_t       jdr2;
1394         vuint32_t       jdr3;
1395         vuint32_t       jdr4;
1396         vuint32_t       dr;
1397         uint8_t         reserved[0x300 - 0x5c];
1398         vuint32_t       csr;
1399         vuint32_t       ccr;
1400 };
1401
1402 extern struct stm_adc stm_adc;
1403
1404 #define STM_ADC_SR_JCNR         9
1405 #define STM_ADC_SR_RCNR         8
1406 #define STM_ADC_SR_ADONS        6
1407 #define STM_ADC_SR_OVR          5
1408 #define STM_ADC_SR_STRT         4
1409 #define STM_ADC_SR_JSTRT        3
1410 #define STM_ADC_SR_JEOC         2
1411 #define STM_ADC_SR_EOC          1
1412 #define STM_ADC_SR_AWD          0
1413
1414 #define STM_ADC_CR1_OVRIE       26
1415 #define STM_ADC_CR1_RES         24
1416 #define  STM_ADC_CR1_RES_12             0
1417 #define  STM_ADC_CR1_RES_10             1
1418 #define  STM_ADC_CR1_RES_8              2
1419 #define  STM_ADC_CR1_RES_6              3
1420 #define  STM_ADC_CR1_RES_MASK           3
1421 #define STM_ADC_CR1_AWDEN       23
1422 #define STM_ADC_CR1_JAWDEN      22
1423 #define STM_ADC_CR1_PDI         17
1424 #define STM_ADC_CR1_PDD         16
1425 #define STM_ADC_CR1_DISCNUM     13
1426 #define  STM_ADC_CR1_DISCNUM_1          0
1427 #define  STM_ADC_CR1_DISCNUM_2          1
1428 #define  STM_ADC_CR1_DISCNUM_3          2
1429 #define  STM_ADC_CR1_DISCNUM_4          3
1430 #define  STM_ADC_CR1_DISCNUM_5          4
1431 #define  STM_ADC_CR1_DISCNUM_6          5
1432 #define  STM_ADC_CR1_DISCNUM_7          6
1433 #define  STM_ADC_CR1_DISCNUM_8          7
1434 #define  STM_ADC_CR1_DISCNUM_MASK       7
1435 #define STM_ADC_CR1_JDISCEN     12
1436 #define STM_ADC_CR1_DISCEN      11
1437 #define STM_ADC_CR1_JAUTO       10
1438 #define STM_ADC_CR1_AWDSGL      9
1439 #define STM_ADC_CR1_SCAN        8
1440 #define STM_ADC_CR1_JEOCIE      7
1441 #define STM_ADC_CR1_AWDIE       6
1442 #define STM_ADC_CR1_EOCIE       5
1443 #define STM_ADC_CR1_AWDCH       0
1444 #define  STM_ADC_CR1_AWDCH_MASK         0x1f
1445
1446 #define STM_ADC_CR2_SWSTART     30
1447 #define STM_ADC_CR2_EXTEN       28
1448 #define  STM_ADC_CR2_EXTEN_DISABLE      0
1449 #define  STM_ADC_CR2_EXTEN_RISING       1
1450 #define  STM_ADC_CR2_EXTEN_FALLING      2
1451 #define  STM_ADC_CR2_EXTEN_BOTH         3
1452 #define  STM_ADC_CR2_EXTEN_MASK         3
1453 #define STM_ADC_CR2_EXTSEL      24
1454 #define  STM_ADC_CR2_EXTSEL_TIM9_CC2    0
1455 #define  STM_ADC_CR2_EXTSEL_TIM9_TRGO   1
1456 #define  STM_ADC_CR2_EXTSEL_TIM2_CC3    2
1457 #define  STM_ADC_CR2_EXTSEL_TIM2_CC2    3
1458 #define  STM_ADC_CR2_EXTSEL_TIM3_TRGO   4
1459 #define  STM_ADC_CR2_EXTSEL_TIM4_CC4    5
1460 #define  STM_ADC_CR2_EXTSEL_TIM2_TRGO   6
1461 #define  STM_ADC_CR2_EXTSEL_TIM3_CC1    7
1462 #define  STM_ADC_CR2_EXTSEL_TIM3_CC3    8
1463 #define  STM_ADC_CR2_EXTSEL_TIM4_TRGO   9
1464 #define  STM_ADC_CR2_EXTSEL_TIM6_TRGO   10
1465 #define  STM_ADC_CR2_EXTSEL_EXTI_11     15
1466 #define  STM_ADC_CR2_EXTSEL_MASK        15
1467 #define STM_ADC_CR2_JWSTART     22
1468 #define STM_ADC_CR2_JEXTEN      20
1469 #define  STM_ADC_CR2_JEXTEN_DISABLE     0
1470 #define  STM_ADC_CR2_JEXTEN_RISING      1
1471 #define  STM_ADC_CR2_JEXTEN_FALLING     2
1472 #define  STM_ADC_CR2_JEXTEN_BOTH        3
1473 #define  STM_ADC_CR2_JEXTEN_MASK        3
1474 #define STM_ADC_CR2_JEXTSEL     16
1475 #define  STM_ADC_CR2_JEXTSEL_TIM9_CC1   0
1476 #define  STM_ADC_CR2_JEXTSEL_TIM9_TRGO  1
1477 #define  STM_ADC_CR2_JEXTSEL_TIM2_TRGO  2
1478 #define  STM_ADC_CR2_JEXTSEL_TIM2_CC1   3
1479 #define  STM_ADC_CR2_JEXTSEL_TIM3_CC4   4
1480 #define  STM_ADC_CR2_JEXTSEL_TIM4_TRGO  5
1481 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC1   6
1482 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC2   7
1483 #define  STM_ADC_CR2_JEXTSEL_TIM4_CC3   8
1484 #define  STM_ADC_CR2_JEXTSEL_TIM10_CC1  9
1485 #define  STM_ADC_CR2_JEXTSEL_TIM7_TRGO  10
1486 #define  STM_ADC_CR2_JEXTSEL_EXTI_15    15
1487 #define  STM_ADC_CR2_JEXTSEL_MASK       15
1488 #define STM_ADC_CR2_ALIGN       11
1489 #define STM_ADC_CR2_EOCS        10
1490 #define STM_ADC_CR2_DDS         9
1491 #define STM_ADC_CR2_DMA         8
1492 #define STM_ADC_CR2_DELS        4
1493 #define  STM_ADC_CR2_DELS_NONE          0
1494 #define  STM_ADC_CR2_DELS_UNTIL_READ    1
1495 #define  STM_ADC_CR2_DELS_7             2
1496 #define  STM_ADC_CR2_DELS_15            3
1497 #define  STM_ADC_CR2_DELS_31            4
1498 #define  STM_ADC_CR2_DELS_63            5
1499 #define  STM_ADC_CR2_DELS_127           6
1500 #define  STM_ADC_CR2_DELS_255           7
1501 #define  STM_ADC_CR2_DELS_MASK          7
1502 #define STM_ADC_CR2_CONT        1
1503 #define STM_ADC_CR2_ADON        0
1504
1505 #define STM_ADC_CCR_TSVREFE     23
1506 #define STM_ADC_CCR_ADCPRE      16
1507 #define  STM_ADC_CCR_ADCPRE_HSI_1       0
1508 #define  STM_ADC_CCR_ADCPRE_HSI_2       1
1509 #define  STM_ADC_CCR_ADCPRE_HSI_4       2
1510 #define  STM_ADC_CCR_ADCPRE_MASK        3
1511
1512 struct stm_temp_cal {
1513         uint16_t        vref;
1514         uint16_t        ts_cal_cold;
1515         uint16_t        reserved;
1516         uint16_t        ts_cal_hot;
1517 };
1518
1519 extern struct stm_temp_cal      stm_temp_cal;
1520
1521 #define stm_temp_cal_cold       25
1522 #define stm_temp_cal_hot        110
1523
1524 struct stm_dbg_mcu {
1525         uint32_t        idcode;
1526 };
1527
1528 extern struct stm_dbg_mcu       stm_dbg_mcu;
1529
1530 static inline uint16_t
1531 stm_dev_id(void) {
1532         return stm_dbg_mcu.idcode & 0xfff;
1533 }
1534
1535 struct stm_flash_size {
1536         uint16_t        f_size;
1537 };
1538
1539 extern struct stm_flash_size    stm_flash_size_medium;
1540 extern struct stm_flash_size    stm_flash_size_large;
1541
1542 /* Returns flash size in bytes */
1543 extern uint32_t
1544 stm_flash_size(void);
1545
1546 struct stm_device_id {
1547         uint32_t        u_id0;
1548         uint32_t        u_id1;
1549         uint32_t        u_id2;
1550 };
1551
1552 extern struct stm_device_id     stm_device_id;
1553
1554 #define STM_NUM_I2C     2
1555
1556 #define STM_I2C_INDEX(channel)  ((channel) - 1)
1557
1558 struct stm_i2c {
1559         vuint32_t       cr1;
1560         vuint32_t       cr2;
1561         vuint32_t       oar1;
1562         vuint32_t       oar2;
1563         vuint32_t       dr;
1564         vuint32_t       sr1;
1565         vuint32_t       sr2;
1566         vuint32_t       ccr;
1567         vuint32_t       trise;
1568 };
1569
1570 extern struct stm_i2c stm_i2c1, stm_i2c2;
1571
1572 #define STM_I2C_CR1_SWRST       15
1573 #define STM_I2C_CR1_ALERT       13
1574 #define STM_I2C_CR1_PEC         12
1575 #define STM_I2C_CR1_POS         11
1576 #define STM_I2C_CR1_ACK         10
1577 #define STM_I2C_CR1_STOP        9
1578 #define STM_I2C_CR1_START       8
1579 #define STM_I2C_CR1_NOSTRETCH   7
1580 #define STM_I2C_CR1_ENGC        6
1581 #define STM_I2C_CR1_ENPEC       5
1582 #define STM_I2C_CR1_ENARP       4
1583 #define STM_I2C_CR1_SMBTYPE     3
1584 #define STM_I2C_CR1_SMBUS       1
1585 #define STM_I2C_CR1_PE          0
1586
1587 #define STM_I2C_CR2_LAST        12
1588 #define STM_I2C_CR2_DMAEN       11
1589 #define STM_I2C_CR2_ITBUFEN     10
1590 #define STM_I2C_CR2_ITEVTEN     9
1591 #define STM_I2C_CR2_ITERREN     8
1592 #define STM_I2C_CR2_FREQ        0
1593 #define  STM_I2C_CR2_FREQ_2_MHZ         2
1594 #define  STM_I2C_CR2_FREQ_4_MHZ         4
1595 #define  STM_I2C_CR2_FREQ_8_MHZ         8
1596 #define  STM_I2C_CR2_FREQ_16_MHZ        16
1597 #define  STM_I2C_CR2_FREQ_32_MHZ        32
1598 #define  STM_I2C_CR2_FREQ_MASK          0x3f
1599
1600 #define STM_I2C_SR1_SMBALERT    15
1601 #define STM_I2C_SR1_TIMEOUT     14
1602 #define STM_I2C_SR1_PECERR      12
1603 #define STM_I2C_SR1_OVR         11
1604 #define STM_I2C_SR1_AF          10
1605 #define STM_I2C_SR1_ARLO        9
1606 #define STM_I2C_SR1_BERR        8
1607 #define STM_I2C_SR1_TXE         7
1608 #define STM_I2C_SR1_RXNE        6
1609 #define STM_I2C_SR1_STOPF       4
1610 #define STM_I2C_SR1_ADD10       3
1611 #define STM_I2C_SR1_BTF         2
1612 #define STM_I2C_SR1_ADDR        1
1613 #define STM_I2C_SR1_SB          0
1614
1615 #define STM_I2C_SR2_PEC         8
1616 #define  STM_I2C_SR2_PEC_MASK   0xff00
1617 #define STM_I2C_SR2_DUALF       7
1618 #define STM_I2C_SR2_SMBHOST     6
1619 #define STM_I2C_SR2_SMBDEFAULT  5
1620 #define STM_I2C_SR2_GENCALL     4
1621 #define STM_I2C_SR2_TRA         2
1622 #define STM_I2C_SR2_BUSY        1
1623 #define STM_I2C_SR2_MSL         0
1624
1625 #define STM_I2C_CCR_FS          15
1626 #define STM_I2C_CCR_DUTY        14
1627 #define STM_I2C_CCR_CCR         0
1628 #define  STM_I2C_CCR_MASK       0x7ff
1629
1630 struct stm_tim234 {
1631         vuint32_t       cr1;
1632         vuint32_t       cr2;
1633         vuint32_t       smcr;
1634         vuint32_t       dier;
1635
1636         vuint32_t       sr;
1637         vuint32_t       egr;
1638         vuint32_t       ccmr1;
1639         vuint32_t       ccmr2;
1640
1641         vuint32_t       ccer;
1642         vuint32_t       cnt;
1643         vuint32_t       psc;
1644         vuint32_t       arr;
1645
1646         uint32_t        reserved_30;
1647         vuint32_t       ccr1;
1648         vuint32_t       ccr2;
1649         vuint32_t       ccr3;
1650
1651         vuint32_t       ccr4;
1652         uint32_t        reserved_44;
1653         vuint32_t       dcr;
1654         vuint32_t       dmar;
1655
1656         uint32_t        reserved_50;
1657 };
1658
1659 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1660
1661 #define STM_TIM234_CR1_CKD      8
1662 #define  STM_TIM234_CR1_CKD_1           0
1663 #define  STM_TIM234_CR1_CKD_2           1
1664 #define  STM_TIM234_CR1_CKD_4           2
1665 #define  STM_TIM234_CR1_CKD_MASK        3
1666 #define STM_TIM234_CR1_ARPE     7
1667 #define STM_TIM234_CR1_CMS      5
1668 #define  STM_TIM234_CR1_CMS_EDGE        0
1669 #define  STM_TIM234_CR1_CMS_CENTER_1    1
1670 #define  STM_TIM234_CR1_CMS_CENTER_2    2
1671 #define  STM_TIM234_CR1_CMS_CENTER_3    3
1672 #define  STM_TIM234_CR1_CMS_MASK        3
1673 #define STM_TIM234_CR1_DIR      4
1674 #define  STM_TIM234_CR1_DIR_UP          0
1675 #define  STM_TIM234_CR1_DIR_DOWN        1
1676 #define STM_TIM234_CR1_OPM      3
1677 #define STM_TIM234_CR1_URS      2
1678 #define STM_TIM234_CR1_UDIS     1
1679 #define STM_TIM234_CR1_CEN      0
1680
1681 #define STM_TIM234_CR2_TI1S     7
1682 #define STM_TIM234_CR2_MMS      4
1683 #define  STM_TIM234_CR2_MMS_RESET               0
1684 #define  STM_TIM234_CR2_MMS_ENABLE              1
1685 #define  STM_TIM234_CR2_MMS_UPDATE              2
1686 #define  STM_TIM234_CR2_MMS_COMPARE_PULSE       3
1687 #define  STM_TIM234_CR2_MMS_COMPARE_OC1REF      4
1688 #define  STM_TIM234_CR2_MMS_COMPARE_OC2REF      5
1689 #define  STM_TIM234_CR2_MMS_COMPARE_OC3REF      6
1690 #define  STM_TIM234_CR2_MMS_COMPARE_OC4REF      7
1691 #define  STM_TIM234_CR2_MMS_MASK                7
1692 #define STM_TIM234_CR2_CCDS     3
1693
1694 #define STM_TIM234_SMCR_ETP     15
1695 #define STM_TIM234_SMCR_ECE     14
1696 #define STM_TIM234_SMCR_ETPS    12
1697 #define  STM_TIM234_SMCR_ETPS_OFF               0
1698 #define  STM_TIM234_SMCR_ETPS_DIV_2             1
1699 #define  STM_TIM234_SMCR_ETPS_DIV_4             2
1700 #define  STM_TIM234_SMCR_ETPS_DIV_8             3
1701 #define  STM_TIM234_SMCR_ETPS_MASK              3
1702 #define STM_TIM234_SMCR_ETF     8
1703 #define  STM_TIM234_SMCR_ETF_NONE               0
1704 #define  STM_TIM234_SMCR_ETF_INT_N_2            1
1705 #define  STM_TIM234_SMCR_ETF_INT_N_4            2
1706 #define  STM_TIM234_SMCR_ETF_INT_N_8            3
1707 #define  STM_TIM234_SMCR_ETF_DTS_2_N_6          4
1708 #define  STM_TIM234_SMCR_ETF_DTS_2_N_8          5
1709 #define  STM_TIM234_SMCR_ETF_DTS_4_N_6          6
1710 #define  STM_TIM234_SMCR_ETF_DTS_4_N_8          7
1711 #define  STM_TIM234_SMCR_ETF_DTS_8_N_6          8
1712 #define  STM_TIM234_SMCR_ETF_DTS_8_N_8          9
1713 #define  STM_TIM234_SMCR_ETF_DTS_16_N_5         10
1714 #define  STM_TIM234_SMCR_ETF_DTS_16_N_6         11
1715 #define  STM_TIM234_SMCR_ETF_DTS_16_N_8         12
1716 #define  STM_TIM234_SMCR_ETF_DTS_32_N_5         13
1717 #define  STM_TIM234_SMCR_ETF_DTS_32_N_6         14
1718 #define  STM_TIM234_SMCR_ETF_DTS_32_N_8         15
1719 #define  STM_TIM234_SMCR_ETF_MASK               15
1720 #define STM_TIM234_SMCR_MSM     7
1721 #define STM_TIM234_SMCR_TS      4
1722 #define  STM_TIM234_SMCR_TS_ITR0                0
1723 #define  STM_TIM234_SMCR_TS_ITR1                1
1724 #define  STM_TIM234_SMCR_TS_ITR2                2
1725 #define  STM_TIM234_SMCR_TS_ITR3                3
1726 #define  STM_TIM234_SMCR_TS_TI1F_ED             4
1727 #define  STM_TIM234_SMCR_TS_TI1FP1              5
1728 #define  STM_TIM234_SMCR_TS_TI2FP2              6
1729 #define  STM_TIM234_SMCR_TS_ETRF                7
1730 #define  STM_TIM234_SMCR_TS_MASK                7
1731 #define STM_TIM234_SMCR_OCCS    3
1732 #define STM_TIM234_SMCR_SMS     0
1733 #define  STM_TIM234_SMCR_SMS_DISABLE            0
1734 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_1     1
1735 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_2     2
1736 #define  STM_TIM234_SMCR_SMS_ENCODER_MODE_3     3
1737 #define  STM_TIM234_SMCR_SMS_RESET_MODE         4
1738 #define  STM_TIM234_SMCR_SMS_GATED_MODE         5
1739 #define  STM_TIM234_SMCR_SMS_TRIGGER_MODE       6
1740 #define  STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK     7
1741 #define  STM_TIM234_SMCR_SMS_MASK               7
1742
1743 #define STM_TIM234_SR_CC4OF     12
1744 #define STM_TIM234_SR_CC3OF     11
1745 #define STM_TIM234_SR_CC2OF     10
1746 #define STM_TIM234_SR_CC1OF     9
1747 #define STM_TIM234_SR_TIF       6
1748 #define STM_TIM234_SR_CC4IF     4
1749 #define STM_TIM234_SR_CC3IF     3
1750 #define STM_TIM234_SR_CC2IF     2
1751 #define STM_TIM234_SR_CC1IF     1
1752 #define STM_TIM234_SR_UIF       0
1753
1754 #define STM_TIM234_EGR_TG       6
1755 #define STM_TIM234_EGR_CC4G     4
1756 #define STM_TIM234_EGR_CC3G     3
1757 #define STM_TIM234_EGR_CC2G     2
1758 #define STM_TIM234_EGR_CC1G     1
1759 #define STM_TIM234_EGR_UG       0
1760
1761 #define STM_TIM234_CCMR1_OC2CE  15
1762 #define STM_TIM234_CCMR1_OC2M   12
1763 #define  STM_TIM234_CCMR1_OC2M_FROZEN                   0
1764 #define  STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH        1
1765 #define  STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH         2
1766 #define  STM_TIM234_CCMR1_OC2M_TOGGLE                   3
1767 #define  STM_TIM234_CCMR1_OC2M_FORCE_LOW                4
1768 #define  STM_TIM234_CCMR1_OC2M_FORCE_HIGH               5
1769 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_1               6
1770 #define  STM_TIM234_CCMR1_OC2M_PWM_MODE_2               7
1771 #define  STM_TIM234_CCMR1_OC2M_MASK                     7
1772 #define STM_TIM234_CCMR1_OC2PE  11
1773 #define STM_TIM234_CCMR1_OC2FE  10
1774 #define STM_TIM234_CCMR1_CC2S   8
1775 #define  STM_TIM234_CCMR1_CC2S_OUTPUT                   0
1776 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI2                1
1777 #define  STM_TIM234_CCMR1_CC2S_INPUT_TI1                2
1778 #define  STM_TIM234_CCMR1_CC2S_INPUT_TRC                3
1779 #define  STM_TIM234_CCMR1_CC2S_MASK                     3
1780
1781 #define STM_TIM234_CCMR1_OC1CE  7
1782 #define STM_TIM234_CCMR1_OC1M   4
1783 #define  STM_TIM234_CCMR1_OC1M_FROZEN                   0
1784 #define  STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH        1
1785 #define  STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH         2
1786 #define  STM_TIM234_CCMR1_OC1M_TOGGLE                   3
1787 #define  STM_TIM234_CCMR1_OC1M_FORCE_LOW                4
1788 #define  STM_TIM234_CCMR1_OC1M_FORCE_HIGH               5
1789 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_1               6
1790 #define  STM_TIM234_CCMR1_OC1M_PWM_MODE_2               7
1791 #define  STM_TIM234_CCMR1_OC1M_MASK                     7
1792 #define STM_TIM234_CCMR1_OC1PE  3
1793 #define STM_TIM234_CCMR1_OC1FE  2
1794 #define STM_TIM234_CCMR1_CC1S   0
1795 #define  STM_TIM234_CCMR1_CC1S_OUTPUT                   0
1796 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI1                1
1797 #define  STM_TIM234_CCMR1_CC1S_INPUT_TI2                2
1798 #define  STM_TIM234_CCMR1_CC1S_INPUT_TRC                3
1799 #define  STM_TIM234_CCMR1_CC1S_MASK                     3
1800
1801 #define STM_TIM234_CCMR2_OC4CE  15
1802 #define STM_TIM234_CCMR2_OC4M   12
1803 #define  STM_TIM234_CCMR2_OC4M_FROZEN                   0
1804 #define  STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH        1
1805 #define  STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH         2
1806 #define  STM_TIM234_CCMR2_OC4M_TOGGLE                   3
1807 #define  STM_TIM234_CCMR2_OC4M_FORCE_LOW                4
1808 #define  STM_TIM234_CCMR2_OC4M_FORCE_HIGH               5
1809 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_1               6
1810 #define  STM_TIM234_CCMR2_OC4M_PWM_MODE_2               7
1811 #define  STM_TIM234_CCMR2_OC4M_MASK                     7
1812 #define STM_TIM234_CCMR2_OC4PE  11
1813 #define STM_TIM234_CCMR2_OC4FE  10
1814 #define STM_TIM234_CCMR2_CC4S   8
1815 #define  STM_TIM234_CCMR2_CC4S_OUTPUT                   0
1816 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI4                1
1817 #define  STM_TIM234_CCMR2_CC4S_INPUT_TI3                2
1818 #define  STM_TIM234_CCMR2_CC4S_INPUT_TRC                3
1819 #define  STM_TIM234_CCMR2_CC4S_MASK                     3
1820
1821 #define STM_TIM234_CCMR2_OC3CE  7
1822 #define STM_TIM234_CCMR2_OC3M   4
1823 #define  STM_TIM234_CCMR2_OC3M_FROZEN                   0
1824 #define  STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH        1
1825 #define  STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH         2
1826 #define  STM_TIM234_CCMR2_OC3M_TOGGLE                   3
1827 #define  STM_TIM234_CCMR2_OC3M_FORCE_LOW                4
1828 #define  STM_TIM234_CCMR2_OC3M_FORCE_HIGH               5
1829 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_1               6
1830 #define  STM_TIM234_CCMR2_OC3M_PWM_MODE_2               7
1831 #define  STM_TIM234_CCMR2_OC3M_MASK                     7
1832 #define STM_TIM234_CCMR2_OC3PE  3
1833 #define STM_TIM234_CCMR2_OC3FE  2
1834 #define STM_TIM234_CCMR2_CC3S   0
1835 #define  STM_TIM234_CCMR2_CC3S_OUTPUT                   0
1836 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI3                1
1837 #define  STM_TIM234_CCMR2_CC3S_INPUT_TI4                2
1838 #define  STM_TIM234_CCMR2_CC3S_INPUT_TRC                3
1839 #define  STM_TIM234_CCMR2_CC3S_MASK                     3
1840
1841 #define STM_TIM234_CCER_CC4NP   15
1842 #define STM_TIM234_CCER_CC4P    13
1843 #define STM_TIM234_CCER_CC4E    12
1844 #define STM_TIM234_CCER_CC3NP   11
1845 #define STM_TIM234_CCER_CC3P    9
1846 #define STM_TIM234_CCER_CC3E    8
1847 #define STM_TIM234_CCER_CC2NP   7
1848 #define STM_TIM234_CCER_CC2P    5
1849 #define STM_TIM234_CCER_CC2E    4
1850 #define STM_TIM234_CCER_CC1NP   3
1851 #define STM_TIM234_CCER_CC1P    1
1852 #define STM_TIM234_CCER_CC1E    0
1853
1854 struct stm_usb {
1855         vuint32_t       epr[8];
1856         uint8_t         reserved_20[0x40 - 0x20];
1857         vuint32_t       cntr;
1858         vuint32_t       istr;
1859         vuint32_t       fnr;
1860         vuint32_t       daddr;
1861         vuint32_t       btable;
1862 };
1863
1864 #define STM_USB_EPR_CTR_RX      15
1865 #define  STM_USB_EPR_CTR_RX_WRITE_INVARIANT             1
1866 #define STM_USB_EPR_DTOG_RX     14
1867 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT             0
1868 #define STM_USB_EPR_STAT_RX     12
1869 #define  STM_USB_EPR_STAT_RX_DISABLED                   0
1870 #define  STM_USB_EPR_STAT_RX_STALL                      1
1871 #define  STM_USB_EPR_STAT_RX_NAK                        2
1872 #define  STM_USB_EPR_STAT_RX_VALID                      3
1873 #define  STM_USB_EPR_STAT_RX_MASK                       3
1874 #define  STM_USB_EPR_STAT_RX_WRITE_INVARIANT            0
1875 #define STM_USB_EPR_SETUP       11
1876 #define STM_USB_EPR_EP_TYPE     9
1877 #define  STM_USB_EPR_EP_TYPE_BULK                       0
1878 #define  STM_USB_EPR_EP_TYPE_CONTROL                    1
1879 #define  STM_USB_EPR_EP_TYPE_ISO                        2
1880 #define  STM_USB_EPR_EP_TYPE_INTERRUPT                  3
1881 #define  STM_USB_EPR_EP_TYPE_MASK                       3
1882 #define STM_USB_EPR_EP_KIND     8
1883 #define  STM_USB_EPR_EP_KIND_DBL_BUF                    1       /* Bulk */
1884 #define  STM_USB_EPR_EP_KIND_STATUS_OUT                 1       /* Control */
1885 #define STM_USB_EPR_CTR_TX      7
1886 #define  STM_USB_CTR_TX_WRITE_INVARIANT                 1
1887 #define STM_USB_EPR_DTOG_TX     6
1888 #define  STM_USB_EPR_DTOG_TX_WRITE_INVARIANT            0
1889 #define STM_USB_EPR_STAT_TX     4
1890 #define  STM_USB_EPR_STAT_TX_DISABLED                   0
1891 #define  STM_USB_EPR_STAT_TX_STALL                      1
1892 #define  STM_USB_EPR_STAT_TX_NAK                        2
1893 #define  STM_USB_EPR_STAT_TX_VALID                      3
1894 #define  STM_USB_EPR_STAT_TX_WRITE_INVARIANT            0
1895 #define  STM_USB_EPR_STAT_TX_MASK                       3
1896 #define STM_USB_EPR_EA          0
1897 #define  STM_USB_EPR_EA_MASK                            0xf
1898
1899 #define STM_USB_CNTR_CTRM       15
1900 #define STM_USB_CNTR_PMAOVRM    14
1901 #define STM_USB_CNTR_ERRM       13
1902 #define STM_USB_CNTR_WKUPM      12
1903 #define STM_USB_CNTR_SUSPM      11
1904 #define STM_USB_CNTR_RESETM     10
1905 #define STM_USB_CNTR_SOFM       9
1906 #define STM_USB_CNTR_ESOFM      8
1907 #define STM_USB_CNTR_RESUME     4
1908 #define STM_USB_CNTR_FSUSP      3
1909 #define STM_USB_CNTR_LP_MODE    2
1910 #define STM_USB_CNTR_PDWN       1
1911 #define STM_USB_CNTR_FRES       0
1912
1913 #define STM_USB_ISTR_CTR        15
1914 #define STM_USB_ISTR_PMAOVR     14
1915 #define STM_USB_ISTR_ERR        13
1916 #define STM_USB_ISTR_WKUP       12
1917 #define STM_USB_ISTR_SUSP       11
1918 #define STM_USB_ISTR_RESET      10
1919 #define STM_USB_ISTR_SOF        9
1920 #define STM_USB_ISTR_ESOF       8
1921 #define STM_USB_ISTR_DIR        4
1922 #define STM_USB_ISTR_EP_ID      0
1923 #define  STM_USB_ISTR_EP_ID_MASK                0xf
1924
1925 #define STM_USB_FNR_RXDP        15
1926 #define STM_USB_FNR_RXDM        14
1927 #define STM_USB_FNR_LCK         13
1928 #define STM_USB_FNR_LSOF        11
1929 #define  STM_USB_FNR_LSOF_MASK                  0x3
1930 #define STM_USB_FNR_FN          0
1931 #define  STM_USB_FNR_FN_MASK                    0x7ff
1932
1933 #define STM_USB_DADDR_EF        7
1934 #define STM_USB_DADDR_ADD       0
1935 #define  STM_USB_DADDR_ADD_MASK                 0x7f
1936
1937 extern struct stm_usb stm_usb;
1938
1939 union stm_usb_bdt {
1940         struct {
1941                 vuint32_t       addr_tx;
1942                 vuint32_t       count_tx;
1943                 vuint32_t       addr_rx;
1944                 vuint32_t       count_rx;
1945         } single;
1946         struct {
1947                 vuint32_t       addr;
1948                 vuint32_t       count;
1949         } double_tx[2];
1950         struct {
1951                 vuint32_t       addr;
1952                 vuint32_t       count;
1953         } double_rx[2];
1954 };
1955
1956 #define STM_USB_BDT_COUNT_RX_BL_SIZE    15
1957 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK  10
1958 #define  STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK    0x1f
1959 #define STM_USB_BDT_COUNT_RX_COUNT_RX   0
1960 #define  STM_USB_BDT_COUNT_RX_COUNT_RX_MASK     0x1ff
1961
1962 #define STM_USB_BDT_SIZE        8
1963
1964 extern uint8_t stm_usb_sram[];
1965
1966 struct stm_exti {
1967         vuint32_t       imr;
1968         vuint32_t       emr;
1969         vuint32_t       rtsr;
1970         vuint32_t       ftsr;
1971
1972         vuint32_t       swier;
1973         vuint32_t       pr;
1974 };
1975
1976 extern struct stm_exti stm_exti;
1977
1978 #endif /* _STM32L_H_ */