2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 volatile __data AO_TICK_TYPE ao_tick_count;
22 uint16_t ao_time(void)
31 static __xdata uint8_t ao_forever;
34 ao_delay(uint16_t ticks)
37 ao_sleep(&ao_forever);
41 volatile __data uint8_t ao_data_interval = 1;
42 volatile __data uint8_t ao_data_count;
49 void stm_tim6_isr(void)
51 if (stm_tim6.sr & (1 << STM_TIM67_SR_UIF)) {
55 if (++ao_data_count == ao_data_interval) {
58 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
59 ao_wakeup((void *) &ao_data_count);
68 ao_timer_set_adc_interval(uint8_t interval) __critical
70 ao_data_interval = interval;
76 * According to the STM clock-configuration, timers run
77 * twice as fast as the APB1 clock *if* the APB1 prescaler
81 #if AO_APB1_PRESCALER > 1
82 #define TIMER_23467_SCALER 2
84 #define TIMER_23467_SCALER 1
87 #define TIMER_10kHz ((AO_PCLK1 * TIMER_23467_SCALER) / 10000)
92 stm_nvic_set_enable(STM_ISR_TIM6_POS);
93 stm_nvic_set_priority(STM_ISR_TIM6_POS, AO_STM_NVIC_CLOCK_PRIORITY);
96 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_TIM6EN);
98 stm_tim6.psc = TIMER_10kHz;
102 /* Enable update interrupt */
103 stm_tim6.dier = (1 << STM_TIM67_DIER_UIE);
105 /* Poke timer to reload values */
106 stm_tim6.egr |= (1 << STM_TIM67_EGR_UG);
108 stm_tim6.cr2 = (STM_TIM67_CR2_MMS_RESET << STM_TIM67_CR2_MMS);
111 stm_tim6.cr1 = ((0 << STM_TIM67_CR1_ARPE) |
112 (0 << STM_TIM67_CR1_OPM) |
113 (1 << STM_TIM67_CR1_URS) |
114 (0 << STM_TIM67_CR1_UDIS) |
115 (1 << STM_TIM67_CR1_CEN));
124 /* Switch to MSI while messing about */
125 stm_rcc.cr |= (1 << STM_RCC_CR_MSION);
126 while (!(stm_rcc.cr & (1 << STM_RCC_CR_MSIRDY)))
129 /* reset SW, HPRE, PPRE1, PPRE2, MCOSEL and MCOPRE */
130 stm_rcc.cfgr &= (uint32_t)0x88FFC00C;
132 /* reset HSION, HSEON, CSSON and PLLON bits */
133 stm_rcc.cr &= 0xeefefffe;
135 /* reset PLLSRC, PLLMUL and PLLDIV bits */
136 stm_rcc.cfgr &= 0xff02ffff;
138 /* Disable all interrupts */
143 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
145 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
147 /* Enable HSE clock */
148 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
149 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
152 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSE << STM_RCC_CFGR_SWS)
153 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSE)
154 #define STM_PLLSRC AO_HSE
155 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (1 << STM_RCC_CFGR_PLLSRC)
157 #define STM_HSI 16000000
158 #define STM_RCC_CFGR_SWS_TARGET_CLOCK (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS)
159 #define STM_RCC_CFGR_SW_TARGET_CLOCK (STM_RCC_CFGR_SW_HSI)
160 #define STM_PLLSRC STM_HSI
161 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK (0 << STM_RCC_CFGR_PLLSRC)
164 #if !AO_HSE || HAS_ADC
165 /* Enable HSI RC clock 16MHz */
166 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
167 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
171 /* Set flash latency to tolerate 32MHz SYSCLK -> 1 wait state */
173 /* Enable 64-bit access and prefetch */
174 stm_flash.acr |= (1 << STM_FLASH_ACR_ACC64);
175 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFEN);
177 /* Enable 1 wait state so the CPU can run at 32MHz */
178 /* (haven't managed to run the CPU at 32MHz yet, it's at 16MHz) */
179 stm_flash.acr |= (1 << STM_FLASH_ACR_LATENCY);
181 /* Enable power interface clock */
182 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
184 /* Set voltage range to 1.8V */
186 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
187 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
190 /* Configure voltage scaling range */
192 cr &= ~(STM_PWR_CR_VOS_MASK << STM_PWR_CR_VOS);
193 cr |= (STM_PWR_CR_VOS_1_8 << STM_PWR_CR_VOS);
196 /* poll VOSF bit in PWR_CSR. Wait until it is reset to 0 */
197 while ((stm_pwr.csr & (1 << STM_PWR_CSR_VOSF)) != 0)
200 /* HCLK to 16MHz -> AHB prescaler = /1 */
202 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
203 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
205 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
206 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
209 /* APB1 Prescaler = AO_APB1_PRESCALER */
211 cfgr &= ~(STM_RCC_CFGR_PPRE1_MASK << STM_RCC_CFGR_PPRE1);
212 cfgr |= (AO_RCC_CFGR_PPRE1_DIV << STM_RCC_CFGR_PPRE1);
215 /* APB2 Prescaler = AO_APB2_PRESCALER */
217 cfgr &= ~(STM_RCC_CFGR_PPRE2_MASK << STM_RCC_CFGR_PPRE2);
218 cfgr |= (AO_RCC_CFGR_PPRE2_DIV << STM_RCC_CFGR_PPRE2);
221 /* Disable the PLL */
222 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
223 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
226 /* PLLVCO to 96MHz (for USB) -> PLLMUL = 6, PLLDIV = 4 */
228 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
229 cfgr &= ~(STM_RCC_CFGR_PLLDIV_MASK << STM_RCC_CFGR_PLLDIV);
231 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
232 cfgr |= (AO_RCC_CFGR_PLLDIV << STM_RCC_CFGR_PLLDIV);
235 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
236 cfgr |= STM_RCC_CFGR_PLLSRC_TARGET_CLOCK;
240 /* Enable the PLL and wait for it */
241 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
242 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
245 /* Switch to the PLL for the system clock */
248 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
249 cfgr |= (STM_RCC_CFGR_SW_PLL << STM_RCC_CFGR_SW);
252 uint32_t c, part, mask, val;
255 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
256 val = (STM_RCC_CFGR_SWS_PLL << STM_RCC_CFGR_SWS);
263 stm_rcc.apb2rstr = 0xffff;
264 stm_rcc.apb1rstr = 0xffff;
265 stm_rcc.ahbrstr = 0x3f;
266 stm_rcc.ahbenr = (1 << STM_RCC_AHBENR_FLITFEN);
270 stm_rcc.apb1rstr = 0;
271 stm_rcc.apb2rstr = 0;
274 /* Clear reset flags */
275 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
278 /* Output SYSCLK on PA8 for measurments */
280 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
282 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
283 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
284 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
286 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
287 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);