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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_spi_stm_info {
  21         uint8_t miso_dma_index;
  22         uint8_t mosi_dma_index;
  23         struct stm_spi *stm_spi;
  24 };
  25
  26 static uint8_t          ao_spi_mutex[STM_NUM_SPI];
  27 static uint8_t          ao_spi_index[STM_NUM_SPI];
  28
  29 static const struct ao_spi_stm_info ao_spi_stm_info[STM_NUM_SPI] = {
  30         {
  31                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_RX),
  32                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI1_TX),
  33                 &stm_spi1
  34         },
  35         {
  36                 .miso_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_RX),
  37                 .mosi_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_SPI2_TX),
  38                 &stm_spi2
  39         }
  40 };
  41
  42 static uint8_t  spi_dev_null;
  43
  44 #if DEBUG
  45 static struct {
  46         uint8_t task;
  47         uint8_t which;
  48         AO_TICK_TYPE tick;
  49         uint16_t len;
  50 } spi_tasks[64];
  51 static uint8_t  spi_task_index;
  52
  53 static void
  54 validate_spi(struct stm_spi *stm_spi, int which, uint16_t len)
  55 {
  56         uint32_t        sr = stm_spi->sr;
  57
  58         if (stm_spi != &stm_spi2)
  59                 return;
  60         spi_tasks[spi_task_index].task = ao_cur_task ? ao_cur_task->task_id : 0;
  61         spi_tasks[spi_task_index].which = which;
  62         spi_tasks[spi_task_index].tick = ao_time();
  63         spi_tasks[spi_task_index].len = len;
  64         spi_task_index = (spi_task_index + 1) & (63);
  65         if (sr & (1 << STM_SPI_SR_FRE))
  66                 ao_panic(0x40 | 1);
  67         if (sr & (1 << STM_SPI_SR_BSY))
  68                 ao_panic(0x40 | 2);
  69         if (sr & (1 << STM_SPI_SR_OVR))
  70                 ao_panic(0x40 | 3);
  71         if (sr & (1 << STM_SPI_SR_MODF))
  72                 ao_panic(0x40 | 4);
  73         if (sr & (1 << STM_SPI_SR_UDR))
  74                 ao_panic(0x40 | 5);
  75         if ((sr & (1 << STM_SPI_SR_TXE)) == 0)
  76                 ao_panic(0x40 | 6);
  77         if (sr & (1 << STM_SPI_SR_RXNE))
  78                 ao_panic(0x40 | 7);
  79         if (which != 5 && which != 6 && which != 13)
  80                 if (ao_cur_task->task_id != ao_spi_mutex[1])
  81                         ao_panic(0x40 | 8);
  82 }
  83 #else
  84 #define validate_spi(stm_spi, which, len) do { (void) (which); (void) (len); } while (0)
  85 #endif
  86
  87 static void
  88 ao_spi_run(uint8_t id, uint8_t which, uint16_t len)
  89 {
  90         struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
  91         uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
  92         uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
  93
  94         validate_spi(stm_spi, which, len);
  95
  96         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
  97                         (0 << STM_SPI_CR2_RXNEIE) |
  98                         (0 << STM_SPI_CR2_ERRIE) |
  99                         (0 << STM_SPI_CR2_SSOE) |
 100                         (1 << STM_SPI_CR2_TXDMAEN) |
 101                         (1 << STM_SPI_CR2_RXDMAEN));
 102
 103         ao_dma_start(miso_dma_index);
 104         ao_dma_start(mosi_dma_index);
 105
 106         ao_arch_critical(
 107                 while (!ao_dma_done[miso_dma_index])
 108                         ao_sleep(&ao_dma_done[miso_dma_index]);
 109                 );
 110
 111         while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0);
 112         while (stm_spi->sr & (1 << STM_SPI_SR_BSY));
 113
 114         validate_spi(stm_spi, which+1, len);
 115
 116         stm_spi->cr2 = 0;
 117
 118         ao_dma_done_transfer(mosi_dma_index);
 119         ao_dma_done_transfer(miso_dma_index);
 120 }
 121
 122 void
 123 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index)
 124 {
 125         uint8_t id = AO_SPI_INDEX(spi_index);
 126         struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
 127         uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
 128         uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 129
 130         /* Set up the transmit DMA to deliver data */
 131         ao_dma_set_transfer(mosi_dma_index,
 132                             &stm_spi->dr,
 133                             (void *) block,
 134                             len,
 135                             (0 << STM_DMA_CCR_MEM2MEM) |
 136                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 137                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 138                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 139                             (1 << STM_DMA_CCR_MINC) |
 140                             (0 << STM_DMA_CCR_PINC) |
 141                             (0 << STM_DMA_CCR_CIRC) |
 142                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 143
 144         /* Set up the receive DMA -- when this is done, we know the SPI unit
 145          * is idle. Without this, we'd have to poll waiting for the BSY bit to
 146          * be cleared
 147          */
 148         ao_dma_set_transfer(miso_dma_index,
 149                             &stm_spi->dr,
 150                             &spi_dev_null,
 151                             len,
 152                             (0 << STM_DMA_CCR_MEM2MEM) |
 153                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 154                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 155                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 156                             (0 << STM_DMA_CCR_MINC) |
 157                             (0 << STM_DMA_CCR_PINC) |
 158                             (0 << STM_DMA_CCR_CIRC) |
 159                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 160
 161         ao_spi_run(id, 1, len);
 162 }
 163
 164 void
 165 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index)
 166 {
 167         uint8_t id = AO_SPI_INDEX(spi_index);
 168         struct stm_spi *stm_spi = ao_spi_stm_info[id].stm_spi;
 169         uint8_t mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
 170         uint8_t miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 171
 172         /* Set up the transmit DMA to deliver data */
 173         ao_dma_set_transfer(mosi_dma_index,
 174                             &stm_spi->dr,
 175                             &value,
 176                             len,
 177                             (0 << STM_DMA_CCR_MEM2MEM) |
 178                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 179                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 180                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 181                             (0 << STM_DMA_CCR_MINC) |
 182                             (0 << STM_DMA_CCR_PINC) |
 183                             (0 << STM_DMA_CCR_CIRC) |
 184                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 185
 186         /* Set up the receive DMA -- when this is done, we know the SPI unit
 187          * is idle. Without this, we'd have to poll waiting for the BSY bit to
 188          * be cleared
 189          */
 190         ao_dma_set_transfer(miso_dma_index,
 191                             &stm_spi->dr,
 192                             &spi_dev_null,
 193                             len,
 194                             (0 << STM_DMA_CCR_MEM2MEM) |
 195                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 196                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 197                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 198                             (0 << STM_DMA_CCR_MINC) |
 199                             (0 << STM_DMA_CCR_PINC) |
 200                             (0 << STM_DMA_CCR_CIRC) |
 201                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 202
 203         ao_spi_run(id, 3, len);
 204 }
 205
 206 void
 207 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index)
 208 {
 209         uint8_t         id = AO_SPI_INDEX(spi_index);
 210         const uint8_t   *b = block;
 211         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 212
 213         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 214                         (0 << STM_SPI_CR2_RXNEIE) |
 215                         (0 << STM_SPI_CR2_ERRIE) |
 216                         (0 << STM_SPI_CR2_SSOE) |
 217                         (0 << STM_SPI_CR2_TXDMAEN) |
 218                         (0 << STM_SPI_CR2_RXDMAEN));
 219         validate_spi(stm_spi, 7, len);
 220         while (len--) {
 221                 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)));
 222                 stm_spi->dr = *b++;
 223         }
 224         while ((stm_spi->sr & (1 << STM_SPI_SR_TXE)) == 0)
 225                 ;
 226         while (stm_spi->sr & (1 << STM_SPI_SR_BSY))
 227                 ;
 228         /* Clear the OVR flag */
 229         (void) stm_spi->dr;
 230         (void) stm_spi->sr;
 231         validate_spi(stm_spi, 8, len);
 232 }
 233
 234 void
 235 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index)
 236 {
 237         uint8_t         id = AO_SPI_INDEX(spi_index);
 238         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 239         uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
 240         uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 241
 242         spi_dev_null = 0xff;
 243
 244         /* Set up transmit DMA to make the SPI hardware actually run */
 245         ao_dma_set_transfer(mosi_dma_index,
 246                             &stm_spi->dr,
 247                             &spi_dev_null,
 248                             len,
 249                             (0 << STM_DMA_CCR_MEM2MEM) |
 250                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 251                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 252                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 253                             (0 << STM_DMA_CCR_MINC) |
 254                             (0 << STM_DMA_CCR_PINC) |
 255                             (0 << STM_DMA_CCR_CIRC) |
 256                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 257
 258         /* Set up the receive DMA to capture data */
 259         ao_dma_set_transfer(miso_dma_index,
 260                             &stm_spi->dr,
 261                             block,
 262                             len,
 263                             (0 << STM_DMA_CCR_MEM2MEM) |
 264                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 265                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 266                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 267                             (1 << STM_DMA_CCR_MINC) |
 268                             (0 << STM_DMA_CCR_PINC) |
 269                             (0 << STM_DMA_CCR_CIRC) |
 270                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 271
 272         ao_spi_run(id, 9, len);
 273 }
 274
 275 void
 276 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index)
 277 {
 278         uint8_t         id = AO_SPI_INDEX(spi_index);
 279         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 280         uint8_t         mosi_dma_index = ao_spi_stm_info[id].mosi_dma_index;
 281         uint8_t         miso_dma_index = ao_spi_stm_info[id].miso_dma_index;
 282
 283         /* Set up transmit DMA to send data */
 284         ao_dma_set_transfer(mosi_dma_index,
 285                             &stm_spi->dr,
 286                             out,
 287                             len,
 288                             (0 << STM_DMA_CCR_MEM2MEM) |
 289                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 290                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 291                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 292                             (1 << STM_DMA_CCR_MINC) |
 293                             (0 << STM_DMA_CCR_PINC) |
 294                             (0 << STM_DMA_CCR_CIRC) |
 295                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 296
 297         /* Set up the receive DMA to capture data */
 298         ao_dma_set_transfer(miso_dma_index,
 299                             &stm_spi->dr,
 300                             in,
 301                             len,
 302                             (0 << STM_DMA_CCR_MEM2MEM) |
 303                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 304                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 305                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 306                             (1 << STM_DMA_CCR_MINC) |
 307                             (0 << STM_DMA_CCR_PINC) |
 308                             (0 << STM_DMA_CCR_CIRC) |
 309                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 310         ao_spi_run(id, 11, len);
 311 }
 312
 313 static void
 314 ao_spi_disable_index(uint8_t spi_index)
 315 {
 316         /* Disable current config
 317          */
 318         switch (AO_SPI_INDEX(spi_index)) {
 319         case STM_SPI_INDEX(1):
 320                 switch (spi_index) {
 321                 case AO_SPI_1_PA5_PA6_PA7:
 322                         stm_gpio_set(&stm_gpioa, 5, 1);
 323                         stm_moder_set(&stm_gpioa, 5, STM_MODER_OUTPUT);
 324                         stm_moder_set(&stm_gpioa, 6, STM_MODER_INPUT);
 325                         stm_moder_set(&stm_gpioa, 7, STM_MODER_OUTPUT);
 326                         break;
 327                 case AO_SPI_1_PB3_PB4_PB5:
 328                         stm_gpio_set(&stm_gpiob, 3, 1);
 329                         stm_moder_set(&stm_gpiob, 3, STM_MODER_OUTPUT);
 330                         stm_moder_set(&stm_gpiob, 4, STM_MODER_INPUT);
 331                         stm_moder_set(&stm_gpiob, 5, STM_MODER_OUTPUT);
 332                         break;
 333                 case AO_SPI_1_PE13_PE14_PE15:
 334                         stm_gpio_set(&stm_gpioe, 13, 1);
 335                         stm_moder_set(&stm_gpioe, 13, STM_MODER_OUTPUT);
 336                         stm_moder_set(&stm_gpioe, 14, STM_MODER_INPUT);
 337                         stm_moder_set(&stm_gpioe, 15, STM_MODER_OUTPUT);
 338                         break;
 339                 }
 340                 break;
 341         case STM_SPI_INDEX(2):
 342                 switch (spi_index) {
 343                 case AO_SPI_2_PB13_PB14_PB15:
 344                         stm_gpio_set(&stm_gpiob, 13, 1);
 345                         stm_moder_set(&stm_gpiob, 13, STM_MODER_OUTPUT);
 346                         stm_moder_set(&stm_gpiob, 14, STM_MODER_INPUT);
 347                         stm_moder_set(&stm_gpiob, 15, STM_MODER_OUTPUT);
 348                         break;
 349                 case AO_SPI_2_PD1_PD3_PD4:
 350                         stm_gpio_set(&stm_gpiod, 1, 1);
 351                         stm_moder_set(&stm_gpiod, 1, STM_MODER_OUTPUT);
 352                         stm_moder_set(&stm_gpiod, 3, STM_MODER_INPUT);
 353                         stm_moder_set(&stm_gpiod, 4, STM_MODER_OUTPUT);
 354                         break;
 355                 }
 356                 break;
 357         }
 358 }
 359
 360 static void
 361 ao_spi_enable_index(uint8_t spi_index)
 362 {
 363         switch (AO_SPI_INDEX(spi_index)) {
 364         case STM_SPI_INDEX(1):
 365                 switch (spi_index) {
 366                 case AO_SPI_1_PA5_PA6_PA7:
 367                         stm_afr_set(&stm_gpioa, 5, STM_AFR_AF5);
 368                         stm_afr_set(&stm_gpioa, 6, STM_AFR_AF5);
 369                         stm_afr_set(&stm_gpioa, 7, STM_AFR_AF5);
 370                         break;
 371                 case AO_SPI_1_PB3_PB4_PB5:
 372                         stm_afr_set(&stm_gpiob, 3, STM_AFR_AF5);
 373                         stm_afr_set(&stm_gpiob, 4, STM_AFR_AF5);
 374                         stm_afr_set(&stm_gpiob, 5, STM_AFR_AF5);
 375                         break;
 376                 case AO_SPI_1_PE13_PE14_PE15:
 377                         stm_afr_set(&stm_gpioe, 13, STM_AFR_AF5);
 378                         stm_afr_set(&stm_gpioe, 14, STM_AFR_AF5);
 379                         stm_afr_set(&stm_gpioe, 15, STM_AFR_AF5);
 380                         break;
 381                 }
 382                 break;
 383         case STM_SPI_INDEX(2):
 384                 switch (spi_index) {
 385                 case AO_SPI_2_PB13_PB14_PB15:
 386                         stm_afr_set(&stm_gpiob, 13, STM_AFR_AF5);
 387                         stm_afr_set(&stm_gpiob, 14, STM_AFR_AF5);
 388                         stm_afr_set(&stm_gpiob, 15, STM_AFR_AF5);
 389                         break;
 390                 case AO_SPI_2_PD1_PD3_PD4:
 391                         stm_afr_set(&stm_gpiod, 1, STM_AFR_AF5);
 392                         stm_afr_set(&stm_gpiod, 3, STM_AFR_AF5);
 393                         stm_afr_set(&stm_gpiod, 4, STM_AFR_AF5);
 394                         break;
 395                 }
 396                 break;
 397         }
 398 }
 399
 400 static void
 401 ao_spi_config(uint8_t spi_index, uint32_t speed)
 402 {
 403         uint8_t         id = AO_SPI_INDEX(spi_index);
 404         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 405
 406         if (spi_index != ao_spi_index[id]) {
 407
 408                 /* Disable old config
 409                  */
 410                 ao_spi_disable_index(ao_spi_index[id]);
 411
 412                 /* Enable new config
 413                  */
 414                 ao_spi_enable_index(spi_index);
 415
 416                 /* Remember current config
 417                  */
 418                 ao_spi_index[id] = spi_index;
 419         }
 420         stm_spi->cr1 = ((0 << STM_SPI_CR1_BIDIMODE) |           /* Three wire mode */
 421                         (0 << STM_SPI_CR1_BIDIOE) |
 422                         (0 << STM_SPI_CR1_CRCEN) |              /* CRC disabled */
 423                         (0 << STM_SPI_CR1_CRCNEXT) |
 424                         (0 << STM_SPI_CR1_DFF) |
 425                         (0 << STM_SPI_CR1_RXONLY) |
 426                         (1 << STM_SPI_CR1_SSM) |                /* Software SS handling */
 427                         (1 << STM_SPI_CR1_SSI) |                /*  ... */
 428                         (0 << STM_SPI_CR1_LSBFIRST) |           /* Big endian */
 429                         (1 << STM_SPI_CR1_SPE) |                /* Enable SPI unit */
 430                         (speed << STM_SPI_CR1_BR) |             /* baud rate to pclk/4 */
 431                         (1 << STM_SPI_CR1_MSTR) |
 432                         (0 << STM_SPI_CR1_CPOL) |               /* Format 0 */
 433                         (0 << STM_SPI_CR1_CPHA));
 434         validate_spi(stm_spi, 13, 0);
 435 }
 436
 437 uint8_t
 438 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id)
 439 {
 440         uint8_t         id = AO_SPI_INDEX(spi_index);
 441
 442         if (!ao_mutex_try(&ao_spi_mutex[id], task_id))
 443                 return 0;
 444         ao_spi_config(spi_index, speed);
 445         return 1;
 446 }
 447
 448 void
 449 ao_spi_get(uint8_t spi_index, uint32_t speed)
 450 {
 451         uint8_t         id = AO_SPI_INDEX(spi_index);
 452
 453         ao_mutex_get(&ao_spi_mutex[id]);
 454         ao_spi_config(spi_index, speed);
 455 }
 456
 457 void
 458 ao_spi_put(uint8_t spi_index)
 459 {
 460         uint8_t         id = AO_SPI_INDEX(spi_index);
 461         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 462
 463         stm_spi->cr1 = 0;
 464         ao_mutex_put(&ao_spi_mutex[id]);
 465 }
 466
 467 static void
 468 ao_spi_channel_init(uint8_t spi_index)
 469 {
 470         uint8_t         id = AO_SPI_INDEX(spi_index);
 471         struct stm_spi  *stm_spi = ao_spi_stm_info[id].stm_spi;
 472
 473         ao_spi_disable_index(spi_index);
 474
 475         stm_spi->cr1 = 0;
 476         stm_spi->cr2 = ((0 << STM_SPI_CR2_TXEIE) |
 477                         (0 << STM_SPI_CR2_RXNEIE) |
 478                         (0 << STM_SPI_CR2_ERRIE) |
 479                         (0 << STM_SPI_CR2_SSOE) |
 480                         (0 << STM_SPI_CR2_TXDMAEN) |
 481                         (0 << STM_SPI_CR2_RXDMAEN));
 482
 483         /* Clear any pending data and error flags */
 484         (void) stm_spi->dr;
 485         (void) stm_spi->sr;
 486 }
 487
 488 #if DEBUG
 489 void
 490 ao_spi_dump_cmd(void)
 491 {
 492         int s;
 493
 494         for (s = 0; s < 64; s++) {
 495                 int i = (spi_task_index + s) & 63;
 496                 if (spi_tasks[i].which) {
 497                         int t;
 498                         const char *name = "(none)";
 499                         for (t = 0; t < ao_num_tasks; t++)
 500                                 if (ao_tasks[t]->task_id == spi_tasks[i].task) {
 501                                         name = ao_tasks[t]->name;
 502                                         break;
 503                                 }
 504                         printf("%2d: %5d task %2d which %2d len %5d %s\n",
 505                                s,
 506                                spi_tasks[i].tick,
 507                                spi_tasks[i].task,
 508                                spi_tasks[i].which,
 509                                spi_tasks[i].len,
 510                                name);
 511                 }
 512         }
 513         for (s = 0; s < STM_NUM_SPI; s++) {
 514                 struct stm_spi *spi = ao_spi_stm_info[s].stm_spi;
 515
 516                 printf("%1d: mutex %2d index %3d miso dma %3d mosi dma %3d",
 517                        s, ao_spi_mutex[s], ao_spi_index[s],
 518                        ao_spi_stm_info[s].miso_dma_index,
 519                        ao_spi_stm_info[s].mosi_dma_index);
 520                 printf(" cr1 %04x cr2 %02x sr %03x\n",
 521                        spi->cr1, spi->cr2, spi->sr);
 522         }
 523
 524 }
 525
 526 static const struct ao_cmds ao_spi_cmds[] = {
 527         { ao_spi_dump_cmd,      "S\0Dump SPI status" },
 528         { 0, NULL }
 529 };
 530 #endif
 531
 532 void
 533 ao_spi_init(void)
 534 {
 535 #if HAS_SPI_1
 536 # if SPI_1_PA5_PA6_PA7
 537         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
 538         stm_ospeedr_set(&stm_gpioa, 5, SPI_1_OSPEEDR);
 539         stm_ospeedr_set(&stm_gpioa, 6, SPI_1_OSPEEDR);
 540         stm_ospeedr_set(&stm_gpioa, 7, SPI_1_OSPEEDR);
 541 # endif
 542 # if SPI_1_PB3_PB4_PB5
 543         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 544         stm_ospeedr_set(&stm_gpiob, 3, SPI_1_OSPEEDR);
 545         stm_ospeedr_set(&stm_gpiob, 4, SPI_1_OSPEEDR);
 546         stm_ospeedr_set(&stm_gpiob, 5, SPI_1_OSPEEDR);
 547 # endif
 548 # if SPI_1_PE13_PE14_PE15
 549         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN);
 550         stm_ospeedr_set(&stm_gpioe, 13, SPI_1_OSPEEDR);
 551         stm_ospeedr_set(&stm_gpioe, 14, SPI_1_OSPEEDR);
 552         stm_ospeedr_set(&stm_gpioe, 15, SPI_1_OSPEEDR);
 553 # endif
 554         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SPI1EN);
 555         ao_spi_index[0] = AO_SPI_CONFIG_NONE;
 556         ao_spi_channel_init(0);
 557 #endif
 558
 559 #if HAS_SPI_2
 560 # if SPI_2_PB13_PB14_PB15
 561         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 562         stm_ospeedr_set(&stm_gpiob, 13, SPI_2_OSPEEDR);
 563         stm_ospeedr_set(&stm_gpiob, 14, SPI_2_OSPEEDR);
 564         stm_ospeedr_set(&stm_gpiob, 15, SPI_2_OSPEEDR);
 565 # endif
 566 # if SPI_2_PD1_PD3_PD4
 567         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN);
 568         stm_ospeedr_set(&stm_gpiod, 1, SPI_2_OSPEEDR);
 569         stm_ospeedr_set(&stm_gpiod, 3, SPI_2_OSPEEDR);
 570         stm_ospeedr_set(&stm_gpiod, 4, SPI_2_OSPEEDR);
 571 # endif
 572         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_SPI2EN);
 573         ao_spi_index[1] = AO_SPI_CONFIG_NONE;
 574         ao_spi_channel_init(1);
 575 #endif
 576 #if DEBUG
 577         ao_cmd_register(&ao_spi_cmds[0]);
 578 #endif
 579 }