2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 static uint8_t pwm_running;
23 static uint16_t pwm_value[NUM_PWM];
28 if (pwm_running++ == 0) {
29 struct stm_tim234 *tim = &AO_PWM_TIMER;
34 tim->arr = PWM_MAX; /* turn on the timer */
41 if (--pwm_running == 0) {
42 struct stm_tim234 *tim = &AO_PWM_TIMER;
43 tim->arr = 0; /* turn off the timer */
48 ao_pwm_set(uint8_t pwm, uint16_t value)
50 struct stm_tim234 *tim = &AO_PWM_TIMER;
53 if (pwm_value[pwm] == 0)
56 if (pwm_value[pwm] != 0)
59 pwm_value[pwm] = value;
86 if (ao_cmd_status != ao_cmd_success)
89 printf("Set channel %d to %d\n", ch, val);
93 static const struct ao_cmds ao_pwm_cmds[] = {
94 { ao_pwm_cmd, "P <ch> <val>\0Set PWM ch to val" },
101 struct stm_tim234 *tim = &AO_PWM_TIMER;
103 stm_rcc.apb1enr |= AO_PWM_TIMER_ENABLE;
108 tim->arr = 0; /* turn off the timer */
111 tim->ccer = ((1 << STM_TIM234_CCER_CC1E) |
112 (0 << STM_TIM234_CCER_CC1P) |
113 (1 << STM_TIM234_CCER_CC2E) |
114 (0 << STM_TIM234_CCER_CC2P) |
115 (1 << STM_TIM234_CCER_CC3E) |
116 (0 << STM_TIM234_CCER_CC3P) |
117 (1 << STM_TIM234_CCER_CC4E) |
118 (0 << STM_TIM234_CCER_CC4P));
120 tim->ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
121 (STM_TIM234_CCMR1_OC2M_PWM_MODE_1 << STM_TIM234_CCMR1_OC2M) |
122 (1 << STM_TIM234_CCMR1_OC2PE) |
123 (0 << STM_TIM234_CCMR1_OC2FE) |
124 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
126 (0 << STM_TIM234_CCMR1_OC1CE) |
127 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
128 (1 << STM_TIM234_CCMR1_OC1PE) |
129 (0 << STM_TIM234_CCMR1_OC1FE) |
130 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
133 tim->ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
134 (STM_TIM234_CCMR2_OC4M_PWM_MODE_1 << STM_TIM234_CCMR2_OC4M) |
135 (1 << STM_TIM234_CCMR2_OC4PE) |
136 (0 << STM_TIM234_CCMR2_OC4FE) |
137 (STM_TIM234_CCMR2_CC4S_OUTPUT << STM_TIM234_CCMR2_CC4S) |
139 (0 << STM_TIM234_CCMR2_OC3CE) |
140 (STM_TIM234_CCMR2_OC3M_PWM_MODE_1 << STM_TIM234_CCMR2_OC3M) |
141 (1 << STM_TIM234_CCMR2_OC3PE) |
142 (0 << STM_TIM234_CCMR2_OC3FE) |
143 (STM_TIM234_CCMR2_CC3S_OUTPUT << STM_TIM234_CCMR2_CC3S));
149 tim->cr2 = ((0 << STM_TIM234_CR2_TI1S) |
150 (STM_TIM234_CR2_MMS_RESET<< STM_TIM234_CR2_MMS) |
151 (0 << STM_TIM234_CR2_CCDS));
153 tim->cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
154 (1 << STM_TIM234_CR1_ARPE) |
155 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
156 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
157 (0 << STM_TIM234_CR1_OPM) |
158 (0 << STM_TIM234_CR1_URS) |
159 (0 << STM_TIM234_CR1_UDIS) |
160 (1 << STM_TIM234_CR1_CEN));
162 stm_afr_set(&stm_gpiod, 12, STM_AFR_AF2);
164 stm_afr_set(&stm_gpiod, 13, STM_AFR_AF2);
167 stm_afr_set(&stm_gpiod, 14, STM_AFR_AF2);
170 stm_afr_set(&stm_gpiod, 15, STM_AFR_AF2);
173 ao_cmd_register(&ao_pwm_cmds[0]);