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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19 #include "ao_pwm.h"
  20
  21 static uint8_t  pwm_running;
  22
  23 static uint16_t pwm_value[NUM_PWM];
  24
  25 static void
  26 ao_pwm_up(void)
  27 {
  28         if (pwm_running++ == 0) {
  29                 struct stm_tim234       *tim = &AO_PWM_TIMER;
  30
  31                 tim->ccr1 = 0;
  32                 tim->ccr2 = 0;
  33                 tim->ccr3 = 0;
  34                 tim->ccr4 = 0;
  35                 tim->arr = PWM_MAX - 1; /* turn on the timer */
  36                 tim->cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
  37                             (0 << STM_TIM234_CR1_ARPE) |
  38                             (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
  39                             (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
  40                             (0 << STM_TIM234_CR1_OPM) |
  41                             (0 << STM_TIM234_CR1_URS) |
  42                             (0 << STM_TIM234_CR1_UDIS) |
  43                             (1 << STM_TIM234_CR1_CEN));
  44
  45                 /* Set the timer running */
  46                 tim->egr = (1 << STM_TIM234_EGR_UG);
  47         }
  48 }
  49
  50 static void
  51 ao_pwm_down(void)
  52 {
  53         if (--pwm_running == 0) {
  54                 struct stm_tim234       *tim = &AO_PWM_TIMER;
  55
  56                 tim->arr = 0;
  57                 tim->cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
  58                             (0 << STM_TIM234_CR1_ARPE) |
  59                             (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
  60                             (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
  61                             (0 << STM_TIM234_CR1_OPM) |
  62                             (0 << STM_TIM234_CR1_URS) |
  63                             (0 << STM_TIM234_CR1_UDIS) |
  64                             (0 << STM_TIM234_CR1_CEN));
  65
  66                 /* Stop the timer */
  67                 tim->egr = (1 << STM_TIM234_EGR_UG);
  68         }
  69 }
  70
  71 void
  72 ao_pwm_set(uint8_t pwm, uint16_t value)
  73 {
  74         struct stm_tim234       *tim = &AO_PWM_TIMER;
  75
  76         if (value > PWM_MAX)
  77                 value = PWM_MAX;
  78         if (value != 0) {
  79                 if (pwm_value[pwm] == 0)
  80                         ao_pwm_up();
  81         }
  82         switch (pwm) {
  83         case 0:
  84                 tim->ccr1 = value;
  85                 break;
  86         case 1:
  87                 tim->ccr2 = value;
  88                 break;
  89         case 2:
  90                 tim->ccr3 = value;
  91                 break;
  92         case 3:
  93                 tim->ccr4 = value;
  94                 break;
  95         }
  96         if (value == 0) {
  97                 if (pwm_value[pwm] != 0)
  98                         ao_pwm_down();
  99         }
 100         pwm_value[pwm] = value;
 101 }
 102
 103 static void
 104 ao_pwm_cmd(void)
 105 {
 106         uint8_t ch;
 107         uint16_t val;
 108
 109         ao_cmd_decimal();
 110         ch = ao_cmd_lex_u32;
 111         ao_cmd_decimal();
 112         val = ao_cmd_lex_u32;
 113         if (ao_cmd_status != ao_cmd_success)
 114                 return;
 115
 116         printf("Set channel %d to %d\n", ch, val);
 117         ao_pwm_set(ch, val);
 118 }
 119
 120 static const struct ao_cmds ao_pwm_cmds[] = {
 121         { ao_pwm_cmd,   "P <ch> <val>\0Set PWM ch to val" },
 122         { 0, NULL },
 123 };
 124
 125 void
 126 ao_pwm_init(void)
 127 {
 128         struct stm_tim234       *tim = &AO_PWM_TIMER;
 129
 130         stm_rcc.apb1enr |= (1 << AO_PWM_TIMER_ENABLE);
 131
 132         tim->cr1 = 0;
 133         tim->psc = AO_PWM_TIMER_SCALE - 1;
 134         tim->cnt = 0;
 135         tim->ccer = ((1 << STM_TIM234_CCER_CC1E) |
 136                      (0 << STM_TIM234_CCER_CC1P) |
 137                      (1 << STM_TIM234_CCER_CC2E) |
 138                      (0 << STM_TIM234_CCER_CC2P) |
 139                      (1 << STM_TIM234_CCER_CC3E) |
 140                      (0 << STM_TIM234_CCER_CC3P) |
 141                      (1 << STM_TIM234_CCER_CC4E) |
 142                      (0 << STM_TIM234_CCER_CC4P));
 143
 144         tim->ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
 145                       (STM_TIM234_CCMR1_OC2M_PWM_MODE_1 << STM_TIM234_CCMR1_OC2M) |
 146                       (0 << STM_TIM234_CCMR1_OC2PE) |
 147                       (0 << STM_TIM234_CCMR1_OC2FE) |
 148                       (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
 149
 150                       (0 << STM_TIM234_CCMR1_OC1CE) |
 151                       (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
 152                       (0 << STM_TIM234_CCMR1_OC1PE) |
 153                       (0 << STM_TIM234_CCMR1_OC1FE) |
 154                       (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
 155
 156
 157         tim->ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
 158                       (STM_TIM234_CCMR2_OC4M_PWM_MODE_1 << STM_TIM234_CCMR2_OC4M) |
 159                       (0 << STM_TIM234_CCMR2_OC4PE) |
 160                       (0 << STM_TIM234_CCMR2_OC4FE) |
 161                       (STM_TIM234_CCMR2_CC4S_OUTPUT << STM_TIM234_CCMR2_CC4S) |
 162
 163                       (0 << STM_TIM234_CCMR2_OC3CE) |
 164                       (STM_TIM234_CCMR2_OC3M_PWM_MODE_1 << STM_TIM234_CCMR2_OC3M) |
 165                       (0 << STM_TIM234_CCMR2_OC3PE) |
 166                       (0 << STM_TIM234_CCMR2_OC3FE) |
 167                       (STM_TIM234_CCMR2_CC3S_OUTPUT << STM_TIM234_CCMR2_CC3S));
 168         tim->egr = 0;
 169
 170         tim->sr = 0;
 171         tim->dier = 0;
 172         tim->smcr = 0;
 173         tim->cr2 = ((0 << STM_TIM234_CR2_TI1S) |
 174                     (STM_TIM234_CR2_MMS_RESET<< STM_TIM234_CR2_MMS) |
 175                     (0 << STM_TIM234_CR2_CCDS));
 176
 177         stm_afr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_AFR_AF2);
 178         stm_ospeedr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_OSPEEDR_40MHz);
 179 #if NUM_PWM > 1
 180         stm_afr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_AFR_AF2);
 181         stm_ospeedr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_OSPEEDR_40MHz);
 182 #endif
 183 #if NUM_PWM > 2
 184         stm_afr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_AFR_AF2);
 185         stm_ospeedr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_OSPEEDR_40MHz);
 186 #endif
 187 #if NUM_PWM > 3
 188         stm_afr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_AFR_AF2);
 189         stm_ospeedr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_OSPEEDR_40MHz);
 190 #endif
 191         ao_cmd_register(&ao_pwm_cmds[0]);
 192 }