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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_TIMEOUT     100
  27
  28 #define I2C_IDLE        0
  29 #define I2C_RUNNING     1
  30 #define I2C_ERROR       2
  31
  32 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  34 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  35
  36 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  37                         (0 << STM_I2C_CR1_ALERT) |      \
  38                         (0 << STM_I2C_CR1_PEC) |        \
  39                         (0 << STM_I2C_CR1_POS) |        \
  40                         (0 << STM_I2C_CR1_ACK) |        \
  41                         (0 << STM_I2C_CR1_STOP) |       \
  42                         (0 << STM_I2C_CR1_START) |      \
  43                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  44                         (0 << STM_I2C_CR1_ENGC) |       \
  45                         (0 << STM_I2C_CR1_ENPEC) |      \
  46                         (0 << STM_I2C_CR1_ENARP) |      \
  47                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  48                         (0 << STM_I2C_CR1_SMBUS) |      \
  49                         (1 << STM_I2C_CR1_PE))
  50
  51 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  52                          (0 << STM_I2C_CR2_DMAEN) |                     \
  53                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  54                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  55                          (0 << STM_I2C_CR2_ITERREN) |                   \
  56                          (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
  57
  58 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  59         {
  60                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  61                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  62                 .stm_i2c = &stm_i2c1
  63         },
  64         {
  65                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  66                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  67                 .stm_i2c = &stm_i2c2
  68         },
  69 };
  70
  71 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
  72 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
  73 static uint16_t ev_count;
  74
  75 static void
  76 ao_i2c_ev_isr(uint8_t index)
  77 {
  78         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
  79         uint32_t        sr1;
  80
  81         ++ev_count;
  82         sr1 = stm_i2c->sr1;
  83         if (sr1 & (1 << STM_I2C_SR1_SB))
  84                 stm_i2c->dr = ao_i2c_addr[index];
  85         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
  86                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  87                 ao_i2c_state[index] = I2C_RUNNING;
  88                 ao_wakeup(&ao_i2c_state[index]);
  89         }
  90         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
  91                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  92                 ao_wakeup(&ao_i2c_state[index]);
  93         }
  94         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
  95                 if (ao_i2c_recv_len[index]) {
  96                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
  97                         if (!--ao_i2c_recv_len[index])
  98                                 ao_wakeup(&ao_i2c_recv_len[index]);
  99                 }
 100         }
 101 }
 102
 103 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 104 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 105
 106 static void
 107 ao_i2c_er_isr(uint8_t index)
 108 {
 109         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 110         uint32_t        sr1;
 111
 112         sr1 = stm_i2c->sr1;
 113         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 114                 ao_i2c_state[index] = I2C_ERROR;
 115                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 116                 ao_wakeup(&ao_i2c_state[index]);
 117         }
 118 }
 119
 120 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 121 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 122
 123 void
 124 ao_i2c_get(uint8_t index)
 125 {
 126         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 127         ao_mutex_get(&ao_i2c_mutex[index]);
 128
 129         stm_i2c->sr1 = 0;
 130         stm_i2c->sr2 = 0;
 131 }
 132
 133 void
 134 ao_i2c_put(uint8_t index)
 135 {
 136         ao_mutex_put(&ao_i2c_mutex[index]);
 137 }
 138
 139 #define I2C_DEBUG       0
 140 #if I2C_DEBUG
 141 #define DBG(x...)       printf(x)
 142 #else
 143 #define DBG(x...)
 144 #endif
 145
 146 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
 147         uint32_t        sr1 = stm_i2c->sr1;
 148         DBG("%s: sr1: %x\n", where, sr1); flush();
 149         return sr1;
 150 }
 151
 152 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
 153         uint32_t        sr2 = stm_i2c->sr2;
 154         DBG("%s: sr2: %x\n", where, sr2); flush();
 155         return sr2;
 156 }
 157
 158 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
 159         DBG("%s: cr1: %x\n", where, cr1); flush();
 160         stm_i2c->cr1 = cr1;
 161 }
 162
 163 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
 164         uint32_t        cr1 = stm_i2c->cr1;
 165         DBG("%s: cr1: %x\n", where, cr1); flush();
 166         return cr1;
 167 }
 168
 169 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
 170         DBG("%s: cr2: %x\n", where, cr2); flush();
 171         stm_i2c->cr2 = cr2;
 172 }
 173
 174 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
 175         uint32_t        dr = stm_i2c->dr;
 176         DBG("%s: dr: %x\n", where, dr); flush();
 177         return dr;
 178 }
 179
 180 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
 181         DBG("%s: dr: %x\n", where, dr); flush();
 182         stm_i2c->dr = dr;
 183 }
 184
 185 uint8_t
 186 ao_i2c_start(uint8_t index, uint16_t addr)
 187 {
 188         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 189         uint32_t        sr1, sr2;
 190         int             t;
 191
 192         ao_i2c_state[index] = I2C_IDLE;
 193         ao_i2c_addr[index] = addr;
 194         printf ("start sr1: %x\n", stm_i2c->sr1);
 195         out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
 196         out_cr1("start", stm_i2c,
 197                 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
 198         out_cr2("start", stm_i2c,
 199                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 200         ao_alarm(1);
 201         cli();
 202         while (ao_i2c_state[index] == I2C_IDLE)
 203                 if (ao_sleep(&ao_i2c_state[index]))
 204                         break;
 205         sei();
 206         ao_clear_alarm();
 207         return ao_i2c_state[index] == I2C_RUNNING;
 208 }
 209
 210 static void
 211 ao_i2c_stop(uint8_t index)
 212 {
 213         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 214
 215         ao_i2c_state[index] = I2C_IDLE;
 216         out_cr2("enable isr", stm_i2c,
 217                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 218         ev_count = 0;
 219         out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 220
 221         /* XXX check to see if there is an interrupt here */
 222         while (in_cr1("stop", stm_i2c) & (1 << STM_I2C_CR1_STOP))
 223                 ao_yield();
 224         printf ("ev_count in stop: %d\n", ev_count);
 225 }
 226
 227 uint8_t
 228 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 229 {
 230         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 231         uint8_t         *b = block;
 232         uint32_t        sr1;
 233         int             t;
 234
 235         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 236
 237         /* Clear any pending ADDR bit */
 238         in_sr2("send clear addr", stm_i2c);
 239         out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
 240         ao_dma_set_transfer(tx_dma_index,
 241                             &stm_i2c->dr,
 242                             block,
 243                             len,
 244                             (0 << STM_DMA_CCR_MEM2MEM) |
 245                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 246                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 247                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 248                             (1 << STM_DMA_CCR_MINC) |
 249                             (0 << STM_DMA_CCR_PINC) |
 250                             (0 << STM_DMA_CCR_CIRC) |
 251                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 252
 253         ao_dma_start(tx_dma_index);
 254         ao_alarm(1 + len);
 255         cli();
 256         while (!ao_dma_done[tx_dma_index])
 257                 if (ao_sleep(&ao_dma_done[tx_dma_index])) {
 258                         printf ("send timeout\n");
 259                         break;
 260                 }
 261         ao_dma_done_transfer(tx_dma_index);
 262         out_cr2("send enable isr", stm_i2c,
 263                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 264         while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
 265                 if (ao_sleep(&ao_i2c_state[index]))
 266                         break;
 267         out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
 268         sei();
 269         if (stop)
 270                 ao_i2c_stop(index);
 271         return TRUE;
 272 }
 273
 274 void
 275 ao_i2c_recv_dma_isr(int index)
 276 {
 277         int             i;
 278         struct stm_i2c  *stm_i2c = NULL;
 279
 280         for (i = 0; i < STM_NUM_I2C; i++)
 281                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 282                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 283                         break;
 284                 }
 285         if (!stm_i2c)
 286                 return;
 287         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 288         ao_dma_done[index] = 1;
 289         ao_wakeup(&ao_dma_done[index]);
 290 }
 291
 292 uint8_t
 293 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 294 {
 295         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 296         uint8_t         *b = block;
 297         int             t;
 298         uint8_t         ret = TRUE;
 299
 300         if (len == 0)
 301                 return TRUE;
 302         if (len == 1) {
 303                 ao_i2c_recv_data[index] = block;
 304                 ao_i2c_recv_len[index] = 1;
 305                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
 306
 307                 /* Clear any pending ADDR bit */
 308                 in_sr2("clear addr", stm_i2c);
 309
 310                 /* Enable interrupts to transfer the byte */
 311                 out_cr2("setup recv 1", stm_i2c,
 312                         AO_STM_I2C_CR2 |
 313                         (1 << STM_I2C_CR2_ITEVTEN) |
 314                         (1 << STM_I2C_CR2_ITERREN) |
 315                         (1 << STM_I2C_CR2_ITBUFEN));
 316                 if (stop)
 317                         out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 318
 319                 ao_alarm(1);
 320                 cli();
 321                 while (ao_i2c_recv_len[index])
 322                         if (ao_sleep(&ao_i2c_recv_len[index]))
 323                                 break;
 324                 sei();
 325                 ret = ao_i2c_recv_len[index] == 0;
 326                 ao_clear_alarm();
 327         } else {
 328                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 329                 ao_dma_set_transfer(rx_dma_index,
 330                                     &stm_i2c->dr,
 331                                     block,
 332                                     len,
 333                                     (0 << STM_DMA_CCR_MEM2MEM) |
 334                                     (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 335                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 336                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 337                                     (1 << STM_DMA_CCR_MINC) |
 338                                     (0 << STM_DMA_CCR_PINC) |
 339                                     (0 << STM_DMA_CCR_CIRC) |
 340                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 341                 out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
 342                 out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
 343                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
 344                 /* Clear any pending ADDR bit */
 345                 in_sr2("clear addr", stm_i2c);
 346
 347                 ao_dma_start(rx_dma_index);
 348                 ao_alarm(len);
 349                 cli();
 350                 while (!ao_dma_done[rx_dma_index])
 351                         if (ao_sleep(&ao_dma_done[rx_dma_index]))
 352                                 break;
 353                 sei();
 354                 ao_clear_alarm();
 355                 ret = ao_dma_done[rx_dma_index];
 356                 ao_dma_done_transfer(rx_dma_index);
 357                 out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 358         }
 359         if (stop) {
 360                 for (t = 0; t < I2C_TIMEOUT; t++) {
 361                         if (!(in_cr1("recv stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
 362                                 break;
 363                         ao_yield();
 364                 }
 365                 if (t == I2C_TIMEOUT)
 366                         return FALSE;
 367         }
 368         return ret;
 369 }
 370
 371 void
 372 ao_i2c_channel_init(uint8_t index)
 373 {
 374         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 375
 376         /* Turn I2C off while configuring */
 377         stm_i2c->cr1 = 0;
 378         stm_i2c->cr2 = AO_STM_I2C_CR2;
 379
 380         (void) stm_i2c->sr1;
 381         (void) stm_i2c->sr2;
 382         (void) stm_i2c->dr;
 383
 384         stm_i2c->sr1 = 0;
 385         stm_i2c->sr2 = 0;
 386
 387         stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
 388                         (0 << STM_I2C_CCR_DUTY) |
 389                         (20 << STM_I2C_CCR_CCR));
 390
 391
 392         stm_i2c->cr1 = AO_STM_I2C_CR1;
 393 }
 394
 395 void
 396 ao_i2c_init(void)
 397 {
 398         /* All of the I2C configurations are on port B */
 399         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 400 #if HAS_I2C_1
 401 # if I2C_1_PB6_PB7
 402         stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
 403         stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
 404 # else
 405 #  if I2C_1_PB8_PB9
 406         stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
 407         stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
 408 #  else
 409 #   error "No I2C_1 port configuration specified"
 410 #  endif
 411 # endif
 412
 413         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 414         ao_i2c_channel_init(0);
 415
 416         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 417         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
 418         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 419         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
 420 #endif
 421
 422 #if HAS_I2C_2
 423 # if I2C_2_PB10_PB11
 424         stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
 425         stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
 426 # else
 427 #  error "No I2C_2 port configuration specified"
 428 # endif
 429         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 430         ao_i2c_channel_init(1);
 431
 432         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 433         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
 434         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 435         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);
 436 #endif
 437 }
 438