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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_TIMEOUT     100
  27
  28 #define I2C_IDLE        0
  29 #define I2C_RUNNING     1
  30 #define I2C_ERROR       2
  31
  32 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  34 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  35
  36 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  37                         (0 << STM_I2C_CR1_ALERT) |      \
  38                         (0 << STM_I2C_CR1_PEC) |        \
  39                         (0 << STM_I2C_CR1_POS) |        \
  40                         (0 << STM_I2C_CR1_ACK) |        \
  41                         (0 << STM_I2C_CR1_STOP) |       \
  42                         (0 << STM_I2C_CR1_START) |      \
  43                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  44                         (0 << STM_I2C_CR1_ENGC) |       \
  45                         (0 << STM_I2C_CR1_ENPEC) |      \
  46                         (0 << STM_I2C_CR1_ENARP) |      \
  47                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  48                         (0 << STM_I2C_CR1_SMBUS) |      \
  49                         (1 << STM_I2C_CR1_PE))
  50
  51 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  52                          (0 << STM_I2C_CR2_DMAEN) |                     \
  53                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  54                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  55                          (0 << STM_I2C_CR2_ITERREN) |                   \
  56                          (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
  57
  58 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  59         {
  60                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  61                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  62                 .stm_i2c = &stm_i2c1
  63         },
  64         {
  65                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  66                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  67                 .stm_i2c = &stm_i2c2
  68         },
  69 };
  70
  71 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
  72 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
  73 static uint16_t ev_count;
  74
  75 static void
  76 ao_i2c_ev_isr(uint8_t index)
  77 {
  78         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
  79         uint32_t        sr1;
  80
  81         ++ev_count;
  82         sr1 = stm_i2c->sr1;
  83         if (sr1 & (1 << STM_I2C_SR1_SB))
  84                 stm_i2c->dr = ao_i2c_addr[index];
  85         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
  86                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  87                 ao_i2c_state[index] = I2C_RUNNING;
  88                 ao_wakeup(&ao_i2c_state[index]);
  89         }
  90         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
  91                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  92                 ao_wakeup(&ao_i2c_state[index]);
  93         }
  94         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
  95                 if (ao_i2c_recv_len[index]) {
  96                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
  97                         if (!--ao_i2c_recv_len[index])
  98                                 ao_wakeup(&ao_i2c_recv_len[index]);
  99                 }
 100         }
 101 }
 102
 103 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 104 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 105
 106 static void
 107 ao_i2c_er_isr(uint8_t index)
 108 {
 109         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 110         uint32_t        sr1;
 111
 112         sr1 = stm_i2c->sr1;
 113         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 114                 ao_i2c_state[index] = I2C_ERROR;
 115                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 116                 ao_wakeup(&ao_i2c_state[index]);
 117         }
 118 }
 119
 120 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 121 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 122
 123 void
 124 ao_i2c_get(uint8_t index)
 125 {
 126         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 127         ao_mutex_get(&ao_i2c_mutex[index]);
 128
 129         stm_i2c->sr1 = 0;
 130         stm_i2c->sr2 = 0;
 131 }
 132
 133 void
 134 ao_i2c_put(uint8_t index)
 135 {
 136         ao_mutex_put(&ao_i2c_mutex[index]);
 137 }
 138
 139 #define I2C_DEBUG       0
 140 #if I2C_DEBUG
 141 #define DBG(x...)       printf(x)
 142 #else
 143 #define DBG(x...)
 144 #endif
 145
 146 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
 147         uint32_t        sr1 = stm_i2c->sr1;
 148         DBG("%s: sr1: %x\n", where, sr1); flush();
 149         return sr1;
 150 }
 151
 152 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
 153         uint32_t        sr2 = stm_i2c->sr2;
 154         DBG("%s: sr2: %x\n", where, sr2); flush();
 155         return sr2;
 156 }
 157
 158 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
 159         DBG("%s: cr1: %x\n", where, cr1); flush();
 160         stm_i2c->cr1 = cr1;
 161 }
 162
 163 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
 164         uint32_t        cr1 = stm_i2c->cr1;
 165         DBG("%s: cr1: %x\n", where, cr1); flush();
 166         return cr1;
 167 }
 168
 169 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
 170         DBG("%s: cr2: %x\n", where, cr2); flush();
 171         stm_i2c->cr2 = cr2;
 172 }
 173
 174 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
 175         uint32_t        dr = stm_i2c->dr;
 176         DBG("%s: dr: %x\n", where, dr); flush();
 177         return dr;
 178 }
 179
 180 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
 181         DBG("%s: dr: %x\n", where, dr); flush();
 182         stm_i2c->dr = dr;
 183 }
 184
 185 uint8_t
 186 ao_i2c_start(uint8_t index, uint16_t addr)
 187 {
 188         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 189         uint32_t        sr1, sr2;
 190         int             t;
 191
 192         ao_i2c_state[index] = I2C_IDLE;
 193         ao_i2c_addr[index] = addr;
 194         out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
 195         out_cr1("start", stm_i2c,
 196                 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
 197         out_cr2("start", stm_i2c,
 198                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 199         ao_alarm(1);
 200         cli();
 201         while (ao_i2c_state[index] == I2C_IDLE)
 202                 if (ao_sleep(&ao_i2c_state[index]))
 203                         break;
 204         sei();
 205         ao_clear_alarm();
 206         return ao_i2c_state[index] == I2C_RUNNING;
 207 }
 208
 209 static void
 210 ao_i2c_wait_stop(uint8_t index)
 211 {
 212         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 213         int     t;
 214
 215         for (t = 0; t < I2C_TIMEOUT; t++) {
 216                 if (!(in_cr1("wait stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
 217                         break;
 218                 ao_yield();
 219         }
 220         ao_i2c_state[index] = I2C_IDLE;
 221 }
 222
 223 uint8_t
 224 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 225 {
 226         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 227         uint8_t         *b = block;
 228         uint32_t        sr1;
 229         int             t;
 230
 231         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 232
 233         /* Clear any pending ADDR bit */
 234         in_sr2("send clear addr", stm_i2c);
 235         out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
 236         ao_dma_set_transfer(tx_dma_index,
 237                             &stm_i2c->dr,
 238                             block,
 239                             len,
 240                             (0 << STM_DMA_CCR_MEM2MEM) |
 241                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 242                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 243                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 244                             (1 << STM_DMA_CCR_MINC) |
 245                             (0 << STM_DMA_CCR_PINC) |
 246                             (0 << STM_DMA_CCR_CIRC) |
 247                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 248
 249         ao_dma_start(tx_dma_index);
 250         ao_alarm(1 + len);
 251         cli();
 252         while (!ao_dma_done[tx_dma_index])
 253                 if (ao_sleep(&ao_dma_done[tx_dma_index])) {
 254                         printf ("send timeout\n");
 255                         break;
 256                 }
 257         ao_dma_done_transfer(tx_dma_index);
 258         out_cr2("send enable isr", stm_i2c,
 259                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 260         while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
 261                 if (ao_sleep(&ao_i2c_state[index]))
 262                         break;
 263         out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
 264         sei();
 265         if (stop) {
 266                 out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 267                 ao_i2c_wait_stop(index);
 268         }
 269         return TRUE;
 270 }
 271
 272 void
 273 ao_i2c_recv_dma_isr(int index)
 274 {
 275         int             i;
 276         struct stm_i2c  *stm_i2c = NULL;
 277
 278         for (i = 0; i < STM_NUM_I2C; i++)
 279                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 280                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 281                         break;
 282                 }
 283         if (!stm_i2c)
 284                 return;
 285         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 286         ao_dma_done[index] = 1;
 287         ao_wakeup(&ao_dma_done[index]);
 288 }
 289
 290 uint8_t
 291 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 292 {
 293         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 294         uint8_t         *b = block;
 295         int             t;
 296         uint8_t         ret = TRUE;
 297
 298         if (len == 0)
 299                 return TRUE;
 300         if (len == 1) {
 301                 ao_i2c_recv_data[index] = block;
 302                 ao_i2c_recv_len[index] = 1;
 303                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
 304
 305                 /* Clear any pending ADDR bit */
 306                 in_sr2("clear addr", stm_i2c);
 307
 308                 /* Enable interrupts to transfer the byte */
 309                 out_cr2("setup recv 1", stm_i2c,
 310                         AO_STM_I2C_CR2 |
 311                         (1 << STM_I2C_CR2_ITEVTEN) |
 312                         (1 << STM_I2C_CR2_ITERREN) |
 313                         (1 << STM_I2C_CR2_ITBUFEN));
 314                 if (stop)
 315                         out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 316
 317                 ao_alarm(1);
 318                 cli();
 319                 while (ao_i2c_recv_len[index])
 320                         if (ao_sleep(&ao_i2c_recv_len[index]))
 321                                 break;
 322                 sei();
 323                 ret = ao_i2c_recv_len[index] == 0;
 324                 ao_clear_alarm();
 325         } else {
 326                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 327                 ao_dma_set_transfer(rx_dma_index,
 328                                     &stm_i2c->dr,
 329                                     block,
 330                                     len,
 331                                     (0 << STM_DMA_CCR_MEM2MEM) |
 332                                     (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 333                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 334                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 335                                     (1 << STM_DMA_CCR_MINC) |
 336                                     (0 << STM_DMA_CCR_PINC) |
 337                                     (0 << STM_DMA_CCR_CIRC) |
 338                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 339                 out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
 340                 out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
 341                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
 342                 /* Clear any pending ADDR bit */
 343                 in_sr2("clear addr", stm_i2c);
 344
 345                 ao_dma_start(rx_dma_index);
 346                 ao_alarm(len);
 347                 cli();
 348                 while (!ao_dma_done[rx_dma_index])
 349                         if (ao_sleep(&ao_dma_done[rx_dma_index]))
 350                                 break;
 351                 sei();
 352                 ao_clear_alarm();
 353                 ret = ao_dma_done[rx_dma_index];
 354                 ao_dma_done_transfer(rx_dma_index);
 355                 out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 356         }
 357         if (stop)
 358                 ao_i2c_wait_stop(index);
 359         return ret;
 360 }
 361
 362 void
 363 ao_i2c_channel_init(uint8_t index)
 364 {
 365         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 366
 367         /* Turn I2C off while configuring */
 368         stm_i2c->cr1 = 0;
 369         stm_i2c->cr2 = AO_STM_I2C_CR2;
 370
 371         (void) stm_i2c->sr1;
 372         (void) stm_i2c->sr2;
 373         (void) stm_i2c->dr;
 374
 375         stm_i2c->sr1 = 0;
 376         stm_i2c->sr2 = 0;
 377
 378         stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
 379                         (0 << STM_I2C_CCR_DUTY) |
 380                         (20 << STM_I2C_CCR_CCR));
 381
 382
 383         stm_i2c->cr1 = AO_STM_I2C_CR1;
 384 }
 385
 386 void
 387 ao_i2c_init(void)
 388 {
 389         /* All of the I2C configurations are on port B */
 390         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 391 #if HAS_I2C_1
 392 # if I2C_1_PB6_PB7
 393         stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
 394         stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
 395 # else
 396 #  if I2C_1_PB8_PB9
 397         stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
 398         stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
 399 #  else
 400 #   error "No I2C_1 port configuration specified"
 401 #  endif
 402 # endif
 403
 404         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 405         ao_i2c_channel_init(0);
 406
 407         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 408         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
 409         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 410         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
 411 #endif
 412
 413 #if HAS_I2C_2
 414 # if I2C_2_PB10_PB11
 415         stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
 416         stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
 417 # else
 418 #  error "No I2C_2 port configuration specified"
 419 # endif
 420         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 421         ao_i2c_channel_init(1);
 422
 423         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 424         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
 425         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 426         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);
 427 #endif
 428 }
 429