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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_TIMEOUT     100
  27
  28 #define I2C_IDLE        0
  29 #define I2C_RUNNING     1
  30 #define I2C_ERROR       2
  31
  32 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  34 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  35
  36 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  37                         (0 << STM_I2C_CR1_ALERT) |      \
  38                         (0 << STM_I2C_CR1_PEC) |        \
  39                         (0 << STM_I2C_CR1_POS) |        \
  40                         (0 << STM_I2C_CR1_ACK) |        \
  41                         (0 << STM_I2C_CR1_STOP) |       \
  42                         (0 << STM_I2C_CR1_START) |      \
  43                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  44                         (0 << STM_I2C_CR1_ENGC) |       \
  45                         (0 << STM_I2C_CR1_ENPEC) |      \
  46                         (0 << STM_I2C_CR1_ENARP) |      \
  47                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  48                         (0 << STM_I2C_CR1_SMBUS) |      \
  49                         (1 << STM_I2C_CR1_PE))
  50
  51 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  52                          (0 << STM_I2C_CR2_DMAEN) |                     \
  53                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  54                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  55                          (0 << STM_I2C_CR2_ITERREN) |                   \
  56                          (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
  57
  58 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  59         {
  60                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  61                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  62                 .stm_i2c = &stm_i2c1
  63         },
  64         {
  65                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  66                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  67                 .stm_i2c = &stm_i2c2
  68         },
  69 };
  70
  71 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
  72 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
  73 static uint16_t ev_count;
  74
  75 static void
  76 ao_i2c_ev_isr(uint8_t index)
  77 {
  78         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
  79         uint32_t        sr1;
  80
  81         ++ev_count;
  82         sr1 = stm_i2c->sr1;
  83         if (sr1 & (1 << STM_I2C_SR1_SB))
  84                 stm_i2c->dr = ao_i2c_addr[index];
  85         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
  86                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  87                 ao_i2c_state[index] = I2C_RUNNING;
  88                 ao_wakeup(&ao_i2c_state[index]);
  89         }
  90         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
  91                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  92                 ao_wakeup(&ao_i2c_state[index]);
  93         }
  94 #if 0
  95         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
  96                 if (ao_i2c_recv_len[index]) {
  97                         switch (--ao_i2c_recv_len[index]) {
  98                         case 0:
  99                                 ao_wakeup(&ao_i2c_recv_len[index]);
 100                                 break;
 101                         case 1:
 102                                 stm_i2c->cr1 &= ~(1 << STM_I2C_CR1_ACK);
 103                                 break;
 104                         }
 105                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
 106                 }
 107         }
 108 #endif
 109 }
 110
 111 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 112 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 113
 114 static void
 115 ao_i2c_er_isr(uint8_t index)
 116 {
 117         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 118         uint32_t        sr1;
 119
 120         sr1 = stm_i2c->sr1;
 121         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 122                 ao_i2c_state[index] = I2C_ERROR;
 123                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 124                 ao_wakeup(&ao_i2c_state[index]);
 125         }
 126 }
 127
 128 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 129 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 130
 131 void
 132 ao_i2c_get(uint8_t index)
 133 {
 134         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 135         ao_mutex_get(&ao_i2c_mutex[index]);
 136
 137         stm_i2c->sr1 = 0;
 138         stm_i2c->sr2 = 0;
 139 }
 140
 141 void
 142 ao_i2c_put(uint8_t index)
 143 {
 144         ao_mutex_put(&ao_i2c_mutex[index]);
 145 }
 146
 147 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
 148         uint32_t        sr1 = stm_i2c->sr1;
 149         printf("%s: sr1: %x\n", where, sr1); flush();
 150         return sr1;
 151 }
 152
 153 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
 154         uint32_t        sr2 = stm_i2c->sr2;
 155         printf("%s: sr2: %x\n", where, sr2); flush();
 156         return sr2;
 157 }
 158
 159 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
 160         printf("%s: cr1: %x\n", where, cr1); flush();
 161         stm_i2c->cr1 = cr1;
 162 }
 163
 164 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
 165         uint32_t        cr1 = stm_i2c->cr1;
 166         printf("%s: cr1: %x\n", where, cr1); flush();
 167         return cr1;
 168 }
 169
 170 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
 171         printf("%s: cr2: %x\n", where, cr2); flush();
 172         stm_i2c->cr2 = cr2;
 173 }
 174
 175 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
 176         uint32_t        dr = stm_i2c->dr;
 177         printf("%s: dr: %x\n", where, dr); flush();
 178         return dr;
 179 }
 180
 181 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
 182         printf("%s: dr: %x\n", where, dr); flush();
 183         stm_i2c->dr = dr;
 184 }
 185
 186 uint8_t
 187 ao_i2c_check_status(char *where, uint8_t index, uint32_t sr1_want, uint32_t sr2_want)
 188 {
 189         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 190         uint32_t        sr1_got, sr2_got;
 191
 192         if (sr1_want) {
 193                 sr1_got = in_sr1(where, stm_i2c);
 194                 if ((sr1_got & sr1_want) != sr1_want) {
 195                         printf ("%s: sr1 wanted %x got %x\n", where, sr1_want, sr1_got);
 196                         return FALSE;
 197                 }
 198         }
 199         if (sr2_want) {
 200                 sr2_got = in_sr2(where, stm_i2c);
 201                 if ((sr2_got & sr2_want) != sr2_want) {
 202                         printf ("%s: sr1 wanted %x got %x\n",
 203                                 where, sr2_want, sr2_got);
 204                         return FALSE;
 205                 }
 206         }
 207         printf ("%s: got sr1 %x and sr2 %x\n", where, sr1_want, sr2_want);
 208         return TRUE;
 209 }
 210
 211 static uint8_t
 212 ao_i2c_check_idle(uint8_t index)
 213 {
 214         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 215         uint32_t        s = 0;
 216         int             t;
 217
 218         for (t = 0; t < I2C_TIMEOUT; t++) {
 219                 if (!ao_i2c_check_status("check idle", index,
 220                                          0,
 221                                          (1 << STM_I2C_SR2_BUSY)))
 222                 {
 223                         break;
 224                 }
 225                 ao_yield();
 226         }
 227         if (t == I2C_TIMEOUT)
 228                 return FALSE;
 229         return TRUE;
 230 }
 231
 232 uint8_t
 233 ao_i2c_start(uint8_t index, uint16_t addr)
 234 {
 235         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 236         uint32_t        sr1, sr2;
 237         int             t;
 238
 239 #if 0
 240         if (!ao_i2c_check_idle(index)) {
 241                 printf ("i2c busy\n");
 242                 return FALSE;
 243         }
 244 #endif
 245
 246         ao_i2c_state[index] = I2C_IDLE;
 247         ao_i2c_addr[index] = addr;
 248 #if 0
 249         out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
 250         out_cr1("start", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
 251         for (t = 0; t < I2C_TIMEOUT; t++) {
 252                 if (ao_i2c_check_status("waiting for start",
 253                                         index,
 254                                         (1 << STM_I2C_SR1_SB),
 255                                         (1 << STM_I2C_SR2_BUSY) |
 256                                         (1 << STM_I2C_SR2_MSL)))
 257                         break;
 258                 ao_yield();
 259         }
 260         if (t == I2C_TIMEOUT) {
 261                 printf ("No start mode\n");
 262                 return FALSE;
 263         }
 264         out_dr("address", stm_i2c, addr);
 265         if (addr & 1) {
 266                 sr1 = (1 << STM_I2C_SR1_ADDR);
 267                 sr2 = (1 << STM_I2C_SR2_BUSY) | (1 << STM_I2C_SR2_MSL);
 268         } else {
 269                 sr1 = (1 << STM_I2C_SR1_TXE) | (1 << STM_I2C_SR1_ADDR);
 270                 sr2 = (1 << STM_I2C_SR2_TRA) | (1 << STM_I2C_SR2_BUSY) | (1 << STM_I2C_SR2_MSL);
 271         }
 272
 273         for (t = 0; t < I2C_TIMEOUT; t++) {
 274                 if (ao_i2c_check_status("waiting for addr",
 275                                         index,
 276                                         sr1, sr2))
 277                         break;
 278                 ao_yield();
 279         }
 280         if (t == I2C_TIMEOUT) {
 281                 printf ("Set addr failed\n");
 282                 return FALSE;
 283         }
 284         ao_i2c_state[index] = I2C_RUNNING;
 285 #else
 286         out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
 287         out_cr1("start", stm_i2c,
 288                 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
 289         out_cr2("start", stm_i2c,
 290                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 291         ao_alarm(1);
 292         cli();
 293         while (ao_i2c_state[index] == I2C_IDLE)
 294                 if (ao_sleep(&ao_i2c_state[index]))
 295                         break;
 296         sei();
 297         ao_clear_alarm();
 298 #endif
 299         return ao_i2c_state[index] == I2C_RUNNING;
 300 }
 301
 302 static void
 303 ao_i2c_stop(uint8_t index)
 304 {
 305         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 306
 307         ao_i2c_state[index] = I2C_IDLE;
 308         out_cr2("enable isr", stm_i2c,
 309                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 310         ev_count = 0;
 311         out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 312
 313         /* XXX check to see if there is an interrupt here */
 314         while (in_cr1("stop", stm_i2c) & (1 << STM_I2C_CR1_STOP))
 315                 ao_yield();
 316         printf ("ev_count in stop: %d\n", ev_count);
 317 }
 318
 319 uint8_t
 320 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 321 {
 322         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 323         uint8_t         *b = block;
 324         uint32_t        sr1;
 325         int             t;
 326
 327 #if 0
 328         while (len--) {
 329                 for (t = 0; t < I2C_TIMEOUT; t++) {
 330                         if (ao_i2c_check_status("send", index,
 331                                                 (1 << STM_I2C_SR1_TXE),
 332                                                 0))
 333                                 break;
 334                         ao_yield();
 335                 }
 336                 if (t == I2C_TIMEOUT)
 337                         return FALSE;
 338                 out_dr("send", stm_i2c, *b++);
 339         }
 340 #else
 341         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 342
 343         /* Clear any pending ADDR bit */
 344         in_sr2("send clear addr", stm_i2c);
 345         out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
 346         ao_dma_set_transfer(tx_dma_index,
 347                             &stm_i2c->dr,
 348                             block,
 349                             len,
 350                             (0 << STM_DMA_CCR_MEM2MEM) |
 351                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 352                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 353                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 354                             (1 << STM_DMA_CCR_MINC) |
 355                             (0 << STM_DMA_CCR_PINC) |
 356                             (0 << STM_DMA_CCR_CIRC) |
 357                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 358
 359         ao_dma_start(tx_dma_index);
 360         ao_alarm(1 + len);
 361         cli();
 362         while (!ao_dma_done[tx_dma_index])
 363                 if (ao_sleep(&ao_dma_done[tx_dma_index])) {
 364                         printf ("send timeout\n");
 365                         break;
 366                 }
 367         ao_dma_done_transfer(tx_dma_index);
 368         out_cr2("send enable isr", stm_i2c,
 369                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 370         while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
 371                 if (ao_sleep(&ao_i2c_state[index]))
 372                         break;
 373         out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
 374         sei();
 375 #endif
 376         if (stop)
 377                 ao_i2c_stop(index);
 378         return TRUE;
 379 }
 380
 381 void
 382 ao_i2c_recv_dma_isr(int index)
 383 {
 384         int             i;
 385         struct stm_i2c  *stm_i2c = NULL;
 386
 387         for (i = 0; i < STM_NUM_I2C; i++)
 388                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 389                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 390                         break;
 391                 }
 392         if (!stm_i2c)
 393                 return;
 394         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 395         ao_dma_done[index] = 1;
 396         ao_wakeup(&ao_dma_done[index]);
 397 }
 398
 399 uint8_t
 400 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 401 {
 402         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 403         uint8_t         *b = block;
 404         int             t;
 405
 406         switch (len) {
 407         case 0:
 408                 return TRUE;
 409         case 1:
 410                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
 411                 /* Clear any pending ADDR bit */
 412                 in_sr2("clear addr", stm_i2c);
 413                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 414                 break;
 415         case 2:
 416                 /* Clear any pending ADDR bit */
 417                 out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_POS));
 418                 if (in_sr1("clear addr", stm_i2c) & (1 << STM_I2C_SR1_ADDR))
 419                         in_sr2("clear addr", stm_i2c);
 420                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 421                 break;
 422         default:
 423 //              out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK) | (1 << STM_I2C_CR1_POS));
 424                 out_cr1("setup recv 2", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
 425                 /* Clear any pending ADDR bit */
 426                 if (in_sr1("clear addr", stm_i2c) & (1 << STM_I2C_SR1_ADDR))
 427                         in_sr2("clear addr", stm_i2c);
 428                 break;
 429         }
 430
 431         while (len--) {
 432                 for (t = 0; t < I2C_TIMEOUT; t++) {
 433                         if (in_sr1("recv", stm_i2c) & (1 << STM_I2C_SR1_RXNE))
 434                                 break;
 435                         ao_yield();
 436                 }
 437                 if (t == I2C_TIMEOUT)
 438                         return FALSE;
 439                 *b++ = in_dr("recv", stm_i2c);
 440                 if (len == 2 && stop) {
 441                         out_cr1("clear ack", stm_i2c,
 442 //                              AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP) | (1 << STM_I2C_CR1_POS));
 443                                 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 444                 }
 445         }
 446         if (stop) {
 447                 for (t = 0; t < I2C_TIMEOUT; t++) {
 448                         if (!(in_cr1("recv stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
 449                                 break;
 450                         ao_yield();
 451                 }
 452                 if (t == I2C_TIMEOUT)
 453                         return FALSE;
 454         }
 455
 456 #if 0
 457         uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 458         ao_dma_set_transfer(rx_dma_index,
 459                             &stm_i2c->dr,
 460                             block,
 461                             len,
 462                             (0 << STM_DMA_CCR_MEM2MEM) |
 463                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 464                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 465                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 466                             (1 << STM_DMA_CCR_MINC) |
 467                             (0 << STM_DMA_CCR_PINC) |
 468                             (0 << STM_DMA_CCR_CIRC) |
 469                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 470         if (len >= 2) {
 471                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK) | (1 << STM_I2C_CR1_POS);
 472                 stm_i2c->cr2 = AO_STM_I2C_CR2;
 473         } else {
 474                 stm_i2c->cr1 = AO_STM_I2C_CR1;
 475                 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 476         }
 477
 478         ao_dma_start(rx_dma_index);
 479         cli();
 480         while (!ao_dma_done[rx_dma_index])
 481                 ao_sleep(&ao_dma_done[rx_dma_index]);
 482         sei();
 483         ao_dma_done_transfer(rx_dma_index);
 484 #endif
 485 }
 486
 487 void
 488 ao_i2c_channel_init(uint8_t index)
 489 {
 490         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 491
 492         /* Turn I2C off while configuring */
 493         stm_i2c->cr1 = 0;
 494         stm_i2c->cr2 = AO_STM_I2C_CR2;
 495
 496         (void) stm_i2c->sr1;
 497         (void) stm_i2c->sr2;
 498         (void) stm_i2c->dr;
 499
 500         stm_i2c->sr1 = 0;
 501         stm_i2c->sr2 = 0;
 502
 503         stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
 504                         (0 << STM_I2C_CCR_DUTY) |
 505                         (20 << STM_I2C_CCR_CCR));
 506
 507
 508         stm_i2c->cr1 = AO_STM_I2C_CR1;
 509 }
 510
 511 void
 512 ao_i2c_init(void)
 513 {
 514         /* All of the I2C configurations are on port B */
 515         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 516 #if HAS_I2C_1
 517 # if I2C_1_PB6_PB7
 518         stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
 519         stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
 520 # else
 521 #  if I2C_1_PB8_PB9
 522         stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
 523         stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
 524 #  else
 525 #   error "No I2C_1 port configuration specified"
 526 #  endif
 527 # endif
 528
 529         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 530         ao_i2c_channel_init(0);
 531
 532         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 533         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
 534         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 535         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
 536 #endif
 537
 538 #if HAS_I2C_2
 539 # if I2C_2_PB10_PB11
 540         stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
 541         stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
 542 # else
 543 #  error "No I2C_2 port configuration specified"
 544 # endif
 545         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 546         ao_i2c_channel_init(1);
 547
 548         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 549         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
 550         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 551         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);
 552 #endif
 553 }
 554