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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19
  20 struct ao_i2c_stm_info {
  21         uint8_t tx_dma_index;
  22         uint8_t rx_dma_index;
  23         struct stm_i2c  *stm_i2c;
  24 };
  25
  26 #define I2C_TIMEOUT     100
  27
  28 #define I2C_IDLE        0
  29 #define I2C_RUNNING     1
  30 #define I2C_ERROR       2
  31
  32 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  34 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  35
  36 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  37                         (0 << STM_I2C_CR1_ALERT) |      \
  38                         (0 << STM_I2C_CR1_PEC) |        \
  39                         (0 << STM_I2C_CR1_POS) |        \
  40                         (0 << STM_I2C_CR1_ACK) |        \
  41                         (0 << STM_I2C_CR1_STOP) |       \
  42                         (0 << STM_I2C_CR1_START) |      \
  43                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  44                         (0 << STM_I2C_CR1_ENGC) |       \
  45                         (0 << STM_I2C_CR1_ENPEC) |      \
  46                         (0 << STM_I2C_CR1_ENARP) |      \
  47                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  48                         (0 << STM_I2C_CR1_SMBUS) |      \
  49                         (1 << STM_I2C_CR1_PE))
  50
  51 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
  52                          (0 << STM_I2C_CR2_DMAEN) |                     \
  53                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
  54                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
  55                          (0 << STM_I2C_CR2_ITERREN) |                   \
  56                          (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
  57
  58 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
  59         {
  60                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
  61                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
  62                 .stm_i2c = &stm_i2c1
  63         },
  64         {
  65                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
  66                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
  67                 .stm_i2c = &stm_i2c2
  68         },
  69 };
  70
  71 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
  72 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
  73 static uint16_t ev_count;
  74
  75 static void
  76 ao_i2c_ev_isr(uint8_t index)
  77 {
  78         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
  79         uint32_t        sr1;
  80
  81         ++ev_count;
  82         sr1 = stm_i2c->sr1;
  83         if (sr1 & (1 << STM_I2C_SR1_SB))
  84                 stm_i2c->dr = ao_i2c_addr[index];
  85         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
  86                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  87                 ao_i2c_state[index] = I2C_RUNNING;
  88                 ao_wakeup(&ao_i2c_state[index]);
  89         }
  90         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
  91                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
  92                 ao_wakeup(&ao_i2c_state[index]);
  93         }
  94         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
  95                 if (ao_i2c_recv_len[index]) {
  96                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
  97                         if (!--ao_i2c_recv_len[index])
  98                                 ao_wakeup(&ao_i2c_recv_len[index]);
  99                 }
 100         }
 101 }
 102
 103 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 104 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 105
 106 static void
 107 ao_i2c_er_isr(uint8_t index)
 108 {
 109         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 110         uint32_t        sr1;
 111
 112         sr1 = stm_i2c->sr1;
 113         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 114                 ao_i2c_state[index] = I2C_ERROR;
 115                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 116                 ao_wakeup(&ao_i2c_state[index]);
 117         }
 118 }
 119
 120 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 121 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 122
 123 void
 124 ao_i2c_get(uint8_t index)
 125 {
 126         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 127         ao_mutex_get(&ao_i2c_mutex[index]);
 128
 129         stm_i2c->sr1 = 0;
 130         stm_i2c->sr2 = 0;
 131 }
 132
 133 void
 134 ao_i2c_put(uint8_t index)
 135 {
 136         ao_mutex_put(&ao_i2c_mutex[index]);
 137 }
 138
 139 static inline void
 140 ao_i2c_delay(void)
 141 {
 142         uint8_t i;
 143
 144         for (i = 0; i < 10; i++)
 145                 ao_arch_nop();
 146 }
 147
 148 #define I2C_DEBUG       0
 149 #if I2C_DEBUG
 150 #define DBG(x...)       printf(x)
 151 #else
 152 #define DBG(x...)
 153 #endif
 154
 155 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
 156         uint32_t        sr1 = stm_i2c->sr1;
 157         DBG("%s: sr1: %x\n", where, sr1); flush();
 158         return sr1;
 159 }
 160
 161 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
 162         uint32_t        sr2 = stm_i2c->sr2;
 163         DBG("%s: sr2: %x\n", where, sr2); flush();
 164         return sr2;
 165 }
 166
 167 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
 168         DBG("%s: cr1: %x\n", where, cr1); flush();
 169         stm_i2c->cr1 = cr1;
 170 }
 171
 172 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
 173         uint32_t        cr1 = stm_i2c->cr1;
 174         DBG("%s: cr1: %x\n", where, cr1); flush();
 175         return cr1;
 176 }
 177
 178 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
 179         DBG("%s: cr2: %x\n", where, cr2); flush();
 180         stm_i2c->cr2 = cr2;
 181 }
 182
 183 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
 184         uint32_t        dr = stm_i2c->dr;
 185         DBG("%s: dr: %x\n", where, dr); flush();
 186         return dr;
 187 }
 188
 189 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
 190         DBG("%s: dr: %x\n", where, dr); flush();
 191         stm_i2c->dr = dr;
 192 }
 193
 194 uint8_t
 195 ao_i2c_start(uint8_t index, uint16_t addr)
 196 {
 197         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 198         uint32_t        sr1, sr2;
 199         int             t;
 200
 201         ao_i2c_state[index] = I2C_IDLE;
 202         ao_i2c_addr[index] = addr;
 203         out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
 204         out_cr1("start", stm_i2c,
 205                 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
 206         ao_i2c_delay();
 207         out_cr2("start", stm_i2c,
 208                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 209         ao_alarm(1);
 210         cli();
 211         while (ao_i2c_state[index] == I2C_IDLE)
 212                 if (ao_sleep(&ao_i2c_state[index]))
 213                         break;
 214         sei();
 215         ao_clear_alarm();
 216         return ao_i2c_state[index] == I2C_RUNNING;
 217 }
 218
 219 static void
 220 ao_i2c_wait_stop(uint8_t index)
 221 {
 222         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 223         int     t;
 224
 225         for (t = 0; t < I2C_TIMEOUT; t++) {
 226                 if (!(in_cr1("wait stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
 227                         break;
 228                 ao_yield();
 229         }
 230         ao_i2c_state[index] = I2C_IDLE;
 231 }
 232
 233 uint8_t
 234 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 235 {
 236         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 237         uint8_t         *b = block;
 238         uint32_t        sr1;
 239         int             t;
 240
 241         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 242
 243         /* Clear any pending ADDR bit */
 244         in_sr2("send clear addr", stm_i2c);
 245         out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
 246         ao_dma_set_transfer(tx_dma_index,
 247                             &stm_i2c->dr,
 248                             block,
 249                             len,
 250                             (0 << STM_DMA_CCR_MEM2MEM) |
 251                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 252                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 253                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 254                             (1 << STM_DMA_CCR_MINC) |
 255                             (0 << STM_DMA_CCR_PINC) |
 256                             (0 << STM_DMA_CCR_CIRC) |
 257                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 258
 259         ao_dma_start(tx_dma_index);
 260         ao_alarm(1 + len);
 261         cli();
 262         while (!ao_dma_done[tx_dma_index])
 263                 if (ao_sleep(&ao_dma_done[tx_dma_index]))
 264                         break;
 265         ao_clear_alarm();
 266         ao_dma_done_transfer(tx_dma_index);
 267         out_cr2("send enable isr", stm_i2c,
 268                 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
 269         while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
 270                 if (ao_sleep(&ao_i2c_state[index]))
 271                         break;
 272         out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
 273         sei();
 274         if (stop) {
 275                 out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 276                 ao_i2c_wait_stop(index);
 277         }
 278         return TRUE;
 279 }
 280
 281 void
 282 ao_i2c_recv_dma_isr(int index)
 283 {
 284         int             i;
 285         struct stm_i2c  *stm_i2c = NULL;
 286
 287         for (i = 0; i < STM_NUM_I2C; i++)
 288                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 289                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 290                         break;
 291                 }
 292         if (!stm_i2c)
 293                 return;
 294         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 295         ao_dma_done[index] = 1;
 296         ao_wakeup(&ao_dma_done[index]);
 297 }
 298
 299 uint8_t
 300 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 301 {
 302         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 303         uint8_t         *b = block;
 304         int             t;
 305         uint8_t         ret = TRUE;
 306
 307         if (len == 0)
 308                 return TRUE;
 309         if (len == 1) {
 310                 ao_i2c_recv_data[index] = block;
 311                 ao_i2c_recv_len[index] = 1;
 312                 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
 313
 314                 /* Clear any pending ADDR bit */
 315                 in_sr2("clear addr", stm_i2c);
 316
 317                 /* Enable interrupts to transfer the byte */
 318                 out_cr2("setup recv 1", stm_i2c,
 319                         AO_STM_I2C_CR2 |
 320                         (1 << STM_I2C_CR2_ITEVTEN) |
 321                         (1 << STM_I2C_CR2_ITERREN) |
 322                         (1 << STM_I2C_CR2_ITBUFEN));
 323                 if (stop)
 324                         out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 325
 326                 ao_alarm(1);
 327                 cli();
 328                 while (ao_i2c_recv_len[index])
 329                         if (ao_sleep(&ao_i2c_recv_len[index]))
 330                                 break;
 331                 sei();
 332                 ret = ao_i2c_recv_len[index] == 0;
 333                 ao_clear_alarm();
 334         } else {
 335                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 336                 ao_dma_set_transfer(rx_dma_index,
 337                                     &stm_i2c->dr,
 338                                     block,
 339                                     len,
 340                                     (0 << STM_DMA_CCR_MEM2MEM) |
 341                                     (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 342                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 343                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 344                                     (1 << STM_DMA_CCR_MINC) |
 345                                     (0 << STM_DMA_CCR_PINC) |
 346                                     (0 << STM_DMA_CCR_CIRC) |
 347                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 348                 out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
 349                 out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
 350                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
 351                 /* Clear any pending ADDR bit */
 352                 in_sr2("clear addr", stm_i2c);
 353
 354                 ao_dma_start(rx_dma_index);
 355                 ao_alarm(len);
 356                 cli();
 357                 while (!ao_dma_done[rx_dma_index])
 358                         if (ao_sleep(&ao_dma_done[rx_dma_index]))
 359                                 break;
 360                 sei();
 361                 ao_clear_alarm();
 362                 ret = ao_dma_done[rx_dma_index];
 363                 ao_dma_done_transfer(rx_dma_index);
 364                 out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
 365         }
 366         if (stop)
 367                 ao_i2c_wait_stop(index);
 368         return ret;
 369 }
 370
 371 void
 372 ao_i2c_channel_init(uint8_t index)
 373 {
 374         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 375         int i;
 376
 377         /* Turn I2C off while configuring */
 378         stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
 379         for (i = 0; i < 100; i++)
 380                 asm("nop");
 381         stm_i2c->cr1 = 0;
 382         stm_i2c->cr2 = AO_STM_I2C_CR2;
 383
 384         (void) stm_i2c->sr1;
 385         (void) stm_i2c->sr2;
 386         (void) stm_i2c->dr;
 387
 388         stm_i2c->sr1 = 0;
 389         stm_i2c->sr2 = 0;
 390
 391         stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
 392                         (0 << STM_I2C_CCR_DUTY) |
 393                         (20 << STM_I2C_CCR_CCR));
 394
 395
 396         stm_i2c->cr1 = AO_STM_I2C_CR1;
 397 }
 398
 399 void
 400 ao_i2c_init(void)
 401 {
 402         /* All of the I2C configurations are on port B */
 403         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 404 #if HAS_I2C_1
 405 # if I2C_1_PB6_PB7
 406         stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
 407         stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
 408 # else
 409 #  if I2C_1_PB8_PB9
 410         stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
 411         stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
 412 #  else
 413 #   error "No I2C_1 port configuration specified"
 414 #  endif
 415 # endif
 416
 417         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 418         ao_i2c_channel_init(0);
 419
 420         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 421         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
 422         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 423         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
 424 #endif
 425
 426 #if HAS_I2C_2
 427 # if I2C_2_PB10_PB11
 428         stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
 429         stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
 430 # else
 431 #  error "No I2C_2 port configuration specified"
 432 # endif
 433         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 434         ao_i2c_channel_init(1);
 435
 436         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 437         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
 438         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 439         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);
 440 #endif
 441 }