2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 struct ao_i2c_stm_info {
24 struct stm_i2c *stm_i2c;
29 #define I2C_TIMEOUT 100
35 static uint8_t ao_i2c_state[STM_NUM_I2C];
36 static uint16_t ao_i2c_addr[STM_NUM_I2C];
37 uint8_t ao_i2c_mutex[STM_NUM_I2C];
39 # define I2C_HIGH_SLOW 5000 /* ns, 100kHz clock */
41 # define I2C_HIGH_FAST 2000 /* ns, 167kHz clock */
43 # define I2C_HIGH_FAST 1000 /* ns, 333kHz clock */
46 # define I2C_RISE_SLOW 500 /* ns */
47 # define I2C_RISE_FAST 100 /* ns */
49 /* Clock period in ns */
50 #define CYCLES(period) (((period) * (AO_PCLK1 / 1000)) / 1000000)
52 #define max(a,b) ((a) > (b) ? (a) : (b))
53 #define I2C_CCR_HIGH_SLOW max(4,CYCLES(I2C_HIGH_SLOW))
54 #define I2C_CCR_HIGH_FAST max(4,CYCLES(I2C_HIGH_FAST))
55 #define I2C_TRISE_SLOW (CYCLES(I2C_RISE_SLOW) + 1)
56 #define I2C_TRISE_FAST (CYCLES(I2C_RISE_FAST) + 1)
59 #define I2C_TRISE I2C_TRISE_FAST
60 #define I2C_CCR_HIGH I2C_CCR_HIGH_FAST
62 #define I2C_TRISE I2C_TRISE_SLOW
63 #define I2C_CCR_HIGH I2C_CCR_HIGH_SLOW
66 #if AO_PCLK1 == 2000000
67 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_2_MHZ
69 #if AO_PCLK1 == 4000000
70 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_4_MHZ
72 #if AO_PCLK1 == 8000000
73 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_8_MHZ
75 #if AO_PCLK1 == 16000000
76 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_16_MHZ
78 #if AO_PCLK1 == 32000000
79 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_32_MHZ
82 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
83 (0 << STM_I2C_CR1_ALERT) | \
84 (0 << STM_I2C_CR1_PEC) | \
85 (0 << STM_I2C_CR1_POS) | \
86 (0 << STM_I2C_CR1_ACK) | \
87 (0 << STM_I2C_CR1_STOP) | \
88 (0 << STM_I2C_CR1_START) | \
89 (0 << STM_I2C_CR1_NOSTRETCH) | \
90 (0 << STM_I2C_CR1_ENGC) | \
91 (0 << STM_I2C_CR1_ENPEC) | \
92 (0 << STM_I2C_CR1_ENARP) | \
93 (0 << STM_I2C_CR1_SMBTYPE) | \
94 (0 << STM_I2C_CR1_SMBUS) | \
95 (1 << STM_I2C_CR1_PE))
97 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
98 (0 << STM_I2C_CR2_DMAEN) | \
99 (0 << STM_I2C_CR2_ITBUFEN) | \
100 (0 << STM_I2C_CR2_ITEVTEN) | \
101 (0 << STM_I2C_CR2_ITERREN) | \
102 (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
104 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
106 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
107 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
111 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
112 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
117 static uint8_t *ao_i2c_recv_data[STM_NUM_I2C];
118 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
119 static uint16_t ev_count;
122 ao_i2c_ev_isr(uint8_t index)
124 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
129 if (sr1 & (1 << STM_I2C_SR1_SB))
130 stm_i2c->dr = ao_i2c_addr[index];
131 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
132 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
133 ao_i2c_state[index] = I2C_RUNNING;
134 ao_wakeup(&ao_i2c_state[index]);
136 if (sr1 & (1 << STM_I2C_SR1_BTF)) {
137 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
138 ao_wakeup(&ao_i2c_state[index]);
140 if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
141 if (ao_i2c_recv_len[index]) {
142 *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
143 if (!--ao_i2c_recv_len[index])
144 ao_wakeup(&ao_i2c_recv_len[index]);
149 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
150 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
153 ao_i2c_er_isr(uint8_t index)
155 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
159 if (sr1 & (1 << STM_I2C_SR1_AF)) {
160 ao_i2c_state[index] = I2C_ERROR;
161 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
162 ao_wakeup(&ao_i2c_state[index]);
166 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
167 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
170 ao_i2c_get(uint8_t index)
172 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
173 ao_mutex_get(&ao_i2c_mutex[index]);
180 ao_i2c_put(uint8_t index)
182 ao_mutex_put(&ao_i2c_mutex[index]);
186 ao_i2c_start(uint8_t index, uint16_t addr)
188 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
191 ao_i2c_state[index] = I2C_IDLE;
192 ao_i2c_addr[index] = addr;
193 stm_i2c->cr2 = AO_STM_I2C_CR2;
194 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
195 for (t = 0; t < I2C_TIMEOUT; t++) {
196 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
199 ao_arch_block_interrupts();
200 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
201 ao_i2c_ev_isr(index);
202 while (ao_i2c_state[index] == I2C_IDLE)
203 if (ao_sleep_for(&ao_i2c_state[index], AO_MS_TO_TICKS(250)))
205 ao_arch_release_interrupts();
206 return ao_i2c_state[index] == I2C_RUNNING;
210 ao_i2c_wait_stop(uint8_t index)
212 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
215 for (t = 0; t < I2C_TIMEOUT; t++) {
216 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
220 ao_i2c_state[index] = I2C_IDLE;
224 ao_i2c_wait_addr(uint8_t index)
226 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
229 for (t = 0; t < I2C_TIMEOUT; t++)
230 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
233 printf ("wait_addr %d\n", t);
237 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
239 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
240 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
242 /* Clear any pending ADDR bit */
244 ao_i2c_wait_addr(index);
245 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
246 ao_dma_set_transfer(tx_dma_index,
250 (0 << STM_DMA_CCR_MEM2MEM) |
251 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
252 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
253 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
254 (1 << STM_DMA_CCR_MINC) |
255 (0 << STM_DMA_CCR_PINC) |
256 (0 << STM_DMA_CCR_CIRC) |
257 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
259 ao_dma_start(tx_dma_index);
260 ao_arch_block_interrupts();
261 while (!ao_dma_done[tx_dma_index])
262 if (ao_sleep_for(&ao_dma_done[tx_dma_index], 1 + len))
264 ao_dma_done_transfer(tx_dma_index);
265 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
266 while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
267 if (ao_sleep_for(&ao_i2c_state[index], 1 + len))
269 stm_i2c->cr2 = AO_STM_I2C_CR2;
270 ao_arch_release_interrupts();
272 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
273 ao_i2c_wait_stop(index);
279 ao_i2c_recv_dma_isr(int index)
282 struct stm_i2c *stm_i2c = NULL;
284 for (i = 0; i < STM_NUM_I2C; i++)
285 if (index == ao_i2c_stm_info[i].rx_dma_index) {
286 stm_i2c = ao_i2c_stm_info[i].stm_i2c;
291 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
292 ao_dma_done[index] = 1;
293 ao_wakeup(&ao_dma_done[index]);
297 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
299 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
305 ao_i2c_recv_data[index] = block;
306 ao_i2c_recv_len[index] = 1;
307 stm_i2c->cr1 = AO_STM_I2C_CR1;
309 /* Clear any pending ADDR bit */
311 ao_i2c_wait_addr(index);
313 /* Enable interrupts to transfer the byte */
314 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
315 (1 << STM_I2C_CR2_ITEVTEN) |
316 (1 << STM_I2C_CR2_ITERREN) |
317 (1 << STM_I2C_CR2_ITBUFEN));
319 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
321 ao_arch_block_interrupts();
322 while (ao_i2c_recv_len[index])
323 if (ao_sleep_for(&ao_i2c_recv_len[index], 1))
325 ao_arch_release_interrupts();
326 ret = ao_i2c_recv_len[index] == 0;
328 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
329 ao_dma_set_transfer(rx_dma_index,
333 (0 << STM_DMA_CCR_MEM2MEM) |
334 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
335 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
336 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
337 (1 << STM_DMA_CCR_MINC) |
338 (0 << STM_DMA_CCR_PINC) |
339 (0 << STM_DMA_CCR_CIRC) |
340 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
341 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
342 stm_i2c->cr2 = AO_STM_I2C_CR2 |
343 (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
344 /* Clear any pending ADDR bit */
346 ao_i2c_wait_addr(index);
348 ao_dma_start(rx_dma_index);
349 ao_arch_block_interrupts();
350 while (!ao_dma_done[rx_dma_index])
351 if (ao_sleep_for(&ao_dma_done[rx_dma_index], len))
353 ao_arch_release_interrupts();
354 ret = ao_dma_done[rx_dma_index];
355 ao_dma_done_transfer(rx_dma_index);
356 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
359 ao_i2c_wait_stop(index);
364 ao_i2c_channel_init(uint8_t index)
366 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
369 /* Turn I2C off while configuring */
370 stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
371 for (i = 0; i < 100; i++)
374 stm_i2c->cr2 = AO_STM_I2C_CR2;
383 stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
384 (0 << STM_I2C_CCR_DUTY) |
385 (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
387 stm_i2c->trise = I2C_TRISE;
389 stm_i2c->cr1 = AO_STM_I2C_CR1;
393 i2c_pin_set(struct stm_gpio *gpio, int pin)
395 stm_afr_set(gpio, pin, STM_AFR_AF4);
396 stm_ospeedr_set(gpio, pin, STM_OSPEEDR_400kHz);
397 stm_pupdr_set(gpio, pin, STM_PUPDR_PULL_UP);
403 /* All of the I2C configurations are on port B */
404 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
407 i2c_pin_set(&stm_gpiob, 6);
408 i2c_pin_set(&stm_gpiob, 7);
411 i2c_pin_set(&stm_gpiob, 8);
412 i2c_pin_set(&stm_gpiob, 9);
414 # error "No I2C_1 port configuration specified"
418 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
419 ao_i2c_channel_init(0);
421 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
422 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
423 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
424 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
429 i2c_pin_set(&stm_gpiob, 10);
430 i2c_pin_set(&stm_gpiob, 11);
432 # error "No I2C_2 port configuration specified"
434 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
435 ao_i2c_channel_init(1);
437 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
438 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
439 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
440 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);