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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include "ao.h"
  19
  20 #define NUM_DMA 7
  21
  22 struct ao_dma_config {
  23         uint32_t        isr;
  24 };
  25
  26 uint8_t ao_dma_done[NUM_DMA];
  27
  28 static struct ao_dma_config ao_dma_config[NUM_DMA];
  29 static uint8_t ao_dma_mutex[NUM_DMA];
  30 static uint8_t ao_dma_active;
  31
  32 static void
  33 ao_dma_isr(uint8_t index) {
  34         /* Get channel interrupt bits */
  35         uint32_t        isr = stm_dma.isr & (STM_DMA_ISR_MASK <<
  36                                              STM_DMA_ISR(index));
  37
  38         /* Ack them */
  39         stm_dma.ifcr = isr;
  40         isr >>= STM_DMA_ISR(index);
  41         ao_dma_config[index].isr |= isr;
  42         ao_dma_done[index] = 1;
  43         ao_wakeup(&ao_dma_done[index]);
  44 }
  45
  46 void stm_dma1_channel1_isr(void) { ao_dma_isr(STM_DMA_INDEX(1)); }
  47 void stm_dma1_channel2_isr(void) { ao_dma_isr(STM_DMA_INDEX(2)); }
  48 void stm_dma1_channel3_isr(void) { ao_dma_isr(STM_DMA_INDEX(3)); }
  49 void stm_dma1_channel4_isr(void) { ao_dma_isr(STM_DMA_INDEX(4)); }
  50 void stm_dma1_channel5_isr(void) { ao_dma_isr(STM_DMA_INDEX(5)); }
  51 void stm_dma1_channel6_isr(void) { ao_dma_isr(STM_DMA_INDEX(6)); }
  52 void stm_dma1_channel7_isr(void) { ao_dma_isr(STM_DMA_INDEX(7)); }
  53
  54 void
  55 ao_dma_set_transfer(uint8_t             index,
  56                     volatile void       *peripheral,
  57                     void                *memory,
  58                     uint16_t            count,
  59                     uint32_t            ccr)
  60 {
  61         ao_mutex_get(&ao_dma_mutex[index]);
  62         if (ao_dma_active++ == 0)
  63                 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMA1EN);
  64         stm_dma.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
  65         stm_dma.channel[index].cndtr = count;
  66         stm_dma.channel[index].cpar = peripheral;
  67         stm_dma.channel[index].cmar = memory;
  68 }
  69
  70 void
  71 ao_dma_start(uint8_t index)
  72 {
  73         ao_dma_done[index] = 0;
  74         stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
  75 }
  76
  77 void
  78 ao_dma_done_transfer(uint8_t index)
  79 {
  80         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
  81         if (--ao_dma_active == 0)
  82                 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMA1EN);
  83         ao_mutex_put(&ao_dma_mutex[index]);
  84 }
  85
  86 void
  87 ao_dma_abort(uint8_t index)
  88 {
  89         stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
  90 }
  91
  92 void
  93 ao_dma_init(void)
  94 {
  95         int     index;
  96
  97         for (index = 0; index < STM_NUM_DMA; index++) {
  98                 stm_nvic_set_enable(STM_ISR_DMA1_CHANNEL1_POS + index);
  99                 stm_nvic_set_priority(STM_ISR_DMA1_CHANNEL1_POS + index, 4);
 100         }
 101
 102 }