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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_data.h>
  20 #if HAS_MPU6000
  21 #include <ao_mpu6000.h>
  22 #endif
  23 #if HAS_MS5607
  24 #include <ao_ms5607.h>
  25 #endif
  26
  27 volatile __xdata struct ao_data ao_data_ring[AO_DATA_RING];
  28 volatile __data uint8_t         ao_data_head;
  29
  30 static uint8_t                  ao_adc_ready;
  31
  32 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  33                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  34                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  35                                  (0 << STM_ADC_CR2_JWSTART) |           \
  36                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  37                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  38                                  (0 << STM_ADC_CR2_ALIGN) |             \
  39                                  (0 << STM_ADC_CR2_EOCS) |              \
  40                                  (1 << STM_ADC_CR2_DDS) |               \
  41                                  (1 << STM_ADC_CR2_DMA) |               \
  42                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  43                                  (0 << STM_ADC_CR2_CONT) |              \
  44                                  (1 << STM_ADC_CR2_ADON))
  45
  46 /*
  47  * Callback from DMA ISR
  48  *
  49  * Mark time in ring, shut down DMA engine
  50  */
  51 static void ao_adc_done(int index)
  52 {
  53         uint8_t step = 1;
  54         ao_data_ring[ao_data_head].tick = ao_time();
  55 #if HAS_MPU6000
  56         if (!ao_mpu6000_valid)
  57                 step = 0;
  58         ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  59 #endif
  60 #if HAS_MS5607
  61         if (!ao_ms5607_valid)
  62                 step = 0;
  63         ao_data_ring[ao_data_head].ms5607 = ao_ms5607_current;
  64 #endif
  65         if (step) {
  66                 ao_data_head = ao_data_ring_next(ao_data_head);
  67                 ao_wakeup((void *) &ao_data_head);
  68         }
  69         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  70         ao_adc_ready = 1;
  71 }
  72
  73 /*
  74  * Start the ADC sequence using the DMA engine
  75  */
  76 void
  77 ao_adc_poll(void)
  78 {
  79         if (!ao_adc_ready)
  80                 return;
  81         ao_adc_ready = 0;
  82         stm_adc.sr = 0;
  83         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  84                             &stm_adc.dr,
  85                             (void *) (&ao_data_ring[ao_data_head].tick + 1),
  86                             AO_NUM_ADC,
  87                             (0 << STM_DMA_CCR_MEM2MEM) |
  88                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  89                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  90                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  91                             (1 << STM_DMA_CCR_MINC) |
  92                             (0 << STM_DMA_CCR_PINC) |
  93                             (0 << STM_DMA_CCR_CIRC) |
  94                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  95         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  96         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  97
  98         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  99 }
 100
 101 /*
 102  * Fetch a copy of the most recent ADC data
 103  */
 104 void
 105 ao_adc_get(__xdata struct ao_adc *packet)
 106 {
 107 #if HAS_FLIGHT
 108         uint8_t i = ao_data_ring_prev(ao_sample_data);
 109 #else
 110         uint8_t i = ao_data_ring_prev(ao_data_head);
 111 #endif
 112         memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
 113 }
 114
 115 void
 116 ao_data_get(__xdata struct ao_data *packet)
 117 {
 118 #if HAS_FLIGHT
 119         uint8_t i = ao_data_ring_prev(ao_sample_data);
 120 #else
 121         uint8_t i = ao_data_ring_prev(ao_data_head);
 122 #endif
 123         memcpy(packet, (void *) &ao_data_ring[i], sizeof (struct ao_data));
 124 }
 125
 126 static void
 127 ao_adc_dump(void) __reentrant
 128 {
 129         struct ao_data  packet;
 130         int16_t *d;
 131         uint8_t i;
 132
 133         ao_data_get(&packet);
 134         printf("tick: %5u",  packet.tick);
 135         d = (int16_t *) (&packet.adc);
 136         for (i = 0; i < AO_NUM_ADC; i++)
 137                 printf (" %2d: %5d", i, d[i]);
 138         printf("\n");
 139 }
 140
 141 __code struct ao_cmds ao_adc_cmds[] = {
 142         { ao_adc_dump,  "a\0Display current ADC values" },
 143         { 0, NULL },
 144 };
 145
 146 void
 147 ao_adc_init(void)
 148 {
 149 #ifdef AO_ADC_PIN0_PORT
 150         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 151 #endif
 152
 153 #ifdef AO_ADC_PIN0_PORT
 154         stm_moder_set(&AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 155 #endif
 156 #ifdef AO_ADC_PIN1_PORT
 157         stm_moder_set(&AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 158 #endif
 159 #ifdef AO_ADC_PIN2_PORT
 160         stm_moder_set(&AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 161 #endif
 162 #ifdef AO_ADC_PIN3_PORT
 163         stm_moder_set(&AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 164 #endif
 165 #ifdef AO_ADC_PIN4_PORT
 166         stm_moder_set(&AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 167 #endif
 168 #ifdef AO_ADC_PIN5_PORT
 169         stm_moder_set(&AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 170 #endif
 171 #ifdef AO_ADC_PIN6_PORT
 172         stm_moder_set(&AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 173 #endif
 174 #ifdef AO_ADC_PIN7_PORT
 175         stm_moder_set(&AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 176 #endif
 177 #ifdef AO_ADC_PIN8_PORT
 178         stm_moder_set(&AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 179 #endif
 180 #ifdef AO_ADC_PIN9_PORT
 181         stm_moder_set(&AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 182 #endif
 183
 184         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 185
 186         /* Turn off ADC during configuration */
 187         stm_adc.cr2 = 0;
 188
 189         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 190                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 191                        (0 << STM_ADC_CR1_AWDEN ) |
 192                        (0 << STM_ADC_CR1_JAWDEN ) |
 193                        (0 << STM_ADC_CR1_PDI ) |
 194                        (0 << STM_ADC_CR1_PDD ) |
 195                        (0 << STM_ADC_CR1_DISCNUM ) |
 196                        (0 << STM_ADC_CR1_JDISCEN ) |
 197                        (0 << STM_ADC_CR1_DISCEN ) |
 198                        (0 << STM_ADC_CR1_JAUTO ) |
 199                        (0 << STM_ADC_CR1_AWDSGL ) |
 200                        (1 << STM_ADC_CR1_SCAN ) |
 201                        (0 << STM_ADC_CR1_JEOCIE ) |
 202                        (0 << STM_ADC_CR1_AWDIE ) |
 203                        (0 << STM_ADC_CR1_EOCIE ) |
 204                        (0 << STM_ADC_CR1_AWDCH ));
 205
 206         /* 384 cycle sample time for everyone */
 207         stm_adc.smpr1 = 0x3ffff;
 208         stm_adc.smpr2 = 0x3fffffff;
 209         stm_adc.smpr3 = 0x3fffffff;
 210
 211         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 212         stm_adc.sqr2 = 0;
 213         stm_adc.sqr3 = 0;
 214         stm_adc.sqr4 = 0;
 215         stm_adc.sqr5 = 0;
 216 #if AO_NUM_ADC > 0
 217         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 218 #endif
 219 #if AO_NUM_ADC > 1
 220         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 221 #endif
 222 #if AO_NUM_ADC > 2
 223         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 224 #endif
 225 #if AO_NUM_ADC > 3
 226         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 227 #endif
 228 #if AO_NUM_ADC > 4
 229         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 230 #endif
 231 #if AO_NUM_ADC > 5
 232         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 233 #endif
 234 #if AO_NUM_ADC > 6
 235         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 236 #endif
 237 #if AO_NUM_ADC > 7
 238         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 239 #endif
 240 #if AO_NUM_ADC > 8
 241         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 242 #endif
 243
 244         /* Turn ADC on */
 245         stm_adc.cr2 = AO_ADC_CR2_VAL;
 246
 247         /* Wait for ADC to be ready */
 248         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 249                 ;
 250
 251 #if HAS_ADC_TEMP
 252         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 253 #else
 254         stm_adc.ccr = 0;
 255 #endif
 256         /* Clear any stale status bits */
 257         stm_adc.sr = 0;
 258         ao_adc_ready = 1;
 259
 260         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 261         ao_cmd_register(&ao_adc_cmds[0]);
 262 }