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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21 #include <ao_adc_single.h>
  22
  23 static uint8_t                  ao_adc_ready;
  24
  25 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  26                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  27                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  28                                  (0 << STM_ADC_CR2_JWSTART) |           \
  29                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  30                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  31                                  (0 << STM_ADC_CR2_ALIGN) |             \
  32                                  (0 << STM_ADC_CR2_EOCS) |              \
  33                                  (1 << STM_ADC_CR2_DDS) |               \
  34                                  (1 << STM_ADC_CR2_DMA) |               \
  35                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  36                                  (0 << STM_ADC_CR2_CONT) |              \
  37                                  (1 << STM_ADC_CR2_ADON))
  38
  39 /*
  40  * Callback from DMA ISR
  41  *
  42  * Shut down DMA engine, signal anyone waiting
  43  */
  44 static void ao_adc_done(int index)
  45 {
  46         (void) index;
  47         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  48         ao_adc_ready = 1;
  49         ao_wakeup((void *) &ao_adc_ready);
  50 }
  51
  52 /*
  53  * Start the ADC sequence using the DMA engine
  54  */
  55 static void
  56 ao_adc_poll(struct ao_adc *packet)
  57 {
  58         ao_adc_ready = 0;
  59         stm_adc.sr = 0;
  60         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  61                             &stm_adc.dr,
  62                             (void *) packet,
  63                             AO_NUM_ADC,
  64                             (0 << STM_DMA_CCR_MEM2MEM) |
  65                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  66                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  67                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  68                             (1 << STM_DMA_CCR_MINC) |
  69                             (0 << STM_DMA_CCR_PINC) |
  70                             (0 << STM_DMA_CCR_CIRC) |
  71                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  72         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  73         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  74
  75         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  76 }
  77
  78 /*
  79  * Fetch a copy of the most recent ADC data
  80  */
  81 void
  82 ao_adc_single_get(struct ao_adc *packet)
  83 {
  84         ao_adc_poll(packet);
  85         ao_arch_block_interrupts();
  86         while (!ao_adc_ready)
  87                 ao_sleep(&ao_adc_ready);
  88         ao_arch_release_interrupts();
  89 }
  90
  91 static void
  92 ao_adc_dump(void)
  93 {
  94         struct ao_adc   packet;
  95         ao_adc_single_get(&packet);
  96         AO_ADC_DUMP(&packet);
  97 }
  98
  99 const struct ao_cmds ao_adc_cmds[] = {
 100         { ao_adc_dump,  "a\0Display current ADC values" },
 101         { 0, NULL },
 102 };
 103
 104 void
 105 ao_adc_single_init(void)
 106 {
 107 #ifdef AO_ADC_PIN0_PORT
 108         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 109 #endif
 110
 111 #ifdef AO_ADC_PIN0_PORT
 112         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 113 #endif
 114 #ifdef AO_ADC_PIN1_PORT
 115         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 116 #endif
 117 #ifdef AO_ADC_PIN2_PORT
 118         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 119 #endif
 120 #ifdef AO_ADC_PIN3_PORT
 121         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 122 #endif
 123 #ifdef AO_ADC_PIN4_PORT
 124         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 125 #endif
 126 #ifdef AO_ADC_PIN5_PORT
 127         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 128 #endif
 129 #ifdef AO_ADC_PIN6_PORT
 130         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 131 #endif
 132 #ifdef AO_ADC_PIN7_PORT
 133         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 134 #endif
 135 #ifdef AO_ADC_PIN8_PORT
 136         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 137 #endif
 138 #ifdef AO_ADC_PIN9_PORT
 139         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 140 #endif
 141 #ifdef AO_ADC_PIN10_PORT
 142         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 143 #endif
 144 #ifdef AO_ADC_PIN11_PORT
 145         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 146 #endif
 147 #ifdef AO_ADC_PIN12_PORT
 148         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 149 #endif
 150 #ifdef AO_ADC_PIN13_PORT
 151         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 152 #endif
 153 #ifdef AO_ADC_PIN14_PORT
 154         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 155 #endif
 156 #ifdef AO_ADC_PIN15_PORT
 157         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 158 #endif
 159 #ifdef AO_ADC_PIN16_PORT
 160         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 161 #endif
 162 #ifdef AO_ADC_PIN17_PORT
 163         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 164 #endif
 165 #ifdef AO_ADC_PIN18_PORT
 166         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 167 #endif
 168 #ifdef AO_ADC_PIN19_PORT
 169         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 170 #endif
 171 #ifdef AO_ADC_PIN20_PORT
 172         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 173 #endif
 174 #ifdef AO_ADC_PIN21_PORT
 175         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 176 #endif
 177 #ifdef AO_ADC_PIN22_PORT
 178         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 179 #endif
 180 #ifdef AO_ADC_PIN23_PORT
 181         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 182 #endif
 183 #ifdef AO_ADC_PIN24_PORT
 184         #error "Too many ADC ports"
 185 #endif
 186
 187         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 188
 189         /* Turn off ADC during configuration */
 190         stm_adc.cr2 = 0;
 191
 192         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 193                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 194                        (0 << STM_ADC_CR1_AWDEN ) |
 195                        (0 << STM_ADC_CR1_JAWDEN ) |
 196                        (0 << STM_ADC_CR1_PDI ) |
 197                        (0 << STM_ADC_CR1_PDD ) |
 198                        (0 << STM_ADC_CR1_DISCNUM ) |
 199                        (0 << STM_ADC_CR1_JDISCEN ) |
 200                        (0 << STM_ADC_CR1_DISCEN ) |
 201                        (0 << STM_ADC_CR1_JAUTO ) |
 202                        (0 << STM_ADC_CR1_AWDSGL ) |
 203                        (1 << STM_ADC_CR1_SCAN ) |
 204                        (0 << STM_ADC_CR1_JEOCIE ) |
 205                        (0 << STM_ADC_CR1_AWDIE ) |
 206                        (0 << STM_ADC_CR1_EOCIE ) |
 207                        (0 << STM_ADC_CR1_AWDCH ));
 208
 209         /* 384 cycle sample time for everyone */
 210         stm_adc.smpr1 = 0x3ffff;
 211         stm_adc.smpr2 = 0x3fffffff;
 212         stm_adc.smpr3 = 0x3fffffff;
 213
 214         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 215         stm_adc.sqr2 = 0;
 216         stm_adc.sqr3 = 0;
 217         stm_adc.sqr4 = 0;
 218         stm_adc.sqr5 = 0;
 219 #if AO_NUM_ADC > 0
 220         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 221 #endif
 222 #if AO_NUM_ADC > 1
 223         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 224 #endif
 225 #if AO_NUM_ADC > 2
 226         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 227 #endif
 228 #if AO_NUM_ADC > 3
 229         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 230 #endif
 231 #if AO_NUM_ADC > 4
 232         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 233 #endif
 234 #if AO_NUM_ADC > 5
 235         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 236 #endif
 237 #if AO_NUM_ADC > 6
 238         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 239 #endif
 240 #if AO_NUM_ADC > 7
 241         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 242 #endif
 243 #if AO_NUM_ADC > 8
 244         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 245 #endif
 246 #if AO_NUM_ADC > 9
 247         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 248 #endif
 249 #if AO_NUM_ADC > 10
 250         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 251 #endif
 252 #if AO_NUM_ADC > 11
 253         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 254 #endif
 255 #if AO_NUM_ADC > 12
 256         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 257 #endif
 258 #if AO_NUM_ADC > 13
 259         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 260 #endif
 261 #if AO_NUM_ADC > 14
 262         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 263 #endif
 264 #if AO_NUM_ADC > 15
 265         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 266 #endif
 267 #if AO_NUM_ADC > 16
 268         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 269 #endif
 270 #if AO_NUM_ADC > 17
 271         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 272 #endif
 273 #if AO_NUM_ADC > 18
 274 #error "need to finish stm_adc.sqr settings"
 275 #endif
 276
 277         /* Turn ADC on */
 278         stm_adc.cr2 = AO_ADC_CR2_VAL;
 279
 280         /* Wait for ADC to be ready */
 281         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 282                 ;
 283
 284 #ifndef HAS_ADC_TEMP
 285 #error Please define HAS_ADC_TEMP
 286 #endif
 287 #if HAS_ADC_TEMP
 288         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 289 #else
 290         stm_adc.ccr = 0;
 291 #endif
 292         /* Clear any stale status bits */
 293         stm_adc.sr = 0;
 294
 295         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 296
 297         ao_cmd_register(&ao_adc_cmds[0]);
 298 }