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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20 #include <ao_data.h>
  21
  22 static uint8_t                  ao_adc_ready;
  23
  24 #define AO_ADC_CR2_VAL          ((0 << STM_ADC_CR2_SWSTART) |           \
  25                                  (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
  26                                  (0 << STM_ADC_CR2_EXTSEL) |            \
  27                                  (0 << STM_ADC_CR2_JWSTART) |           \
  28                                  (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
  29                                  (0 << STM_ADC_CR2_JEXTSEL) |           \
  30                                  (0 << STM_ADC_CR2_ALIGN) |             \
  31                                  (0 << STM_ADC_CR2_EOCS) |              \
  32                                  (1 << STM_ADC_CR2_DDS) |               \
  33                                  (1 << STM_ADC_CR2_DMA) |               \
  34                                  (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
  35                                  (0 << STM_ADC_CR2_CONT) |              \
  36                                  (1 << STM_ADC_CR2_ADON))
  37
  38 /*
  39  * Callback from DMA ISR
  40  *
  41  * Shut down DMA engine, signal anyone waiting
  42  */
  43 static void ao_adc_done(int index)
  44 {
  45         (void) index;
  46         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  47         ao_adc_ready = 1;
  48         ao_wakeup((void *) &ao_adc_ready);
  49 }
  50
  51 /*
  52  * Start the ADC sequence using the DMA engine
  53  */
  54 static void
  55 ao_adc_poll(struct ao_adc *packet)
  56 {
  57         ao_adc_ready = 0;
  58         stm_adc.sr = 0;
  59         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
  60                             &stm_adc.dr,
  61                             (void *) packet,
  62                             AO_NUM_ADC,
  63                             (0 << STM_DMA_CCR_MEM2MEM) |
  64                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  65                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  66                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  67                             (1 << STM_DMA_CCR_MINC) |
  68                             (0 << STM_DMA_CCR_PINC) |
  69                             (0 << STM_DMA_CCR_CIRC) |
  70                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
  71         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
  72         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
  73
  74         stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
  75 }
  76
  77 /*
  78  * Fetch a copy of the most recent ADC data
  79  */
  80 void
  81 ao_adc_single_get(struct ao_adc *packet)
  82 {
  83         ao_adc_poll(packet);
  84         ao_arch_block_interrupts();
  85         while (!ao_adc_ready)
  86                 ao_sleep(&ao_adc_ready);
  87         ao_arch_release_interrupts();
  88 }
  89
  90 static void
  91 ao_adc_dump(void)
  92 {
  93         struct ao_adc   packet;
  94         ao_adc_single_get(&packet);
  95         AO_ADC_DUMP(&packet);
  96 }
  97
  98 __code struct ao_cmds ao_adc_cmds[] = {
  99         { ao_adc_dump,  "a\0Display current ADC values" },
 100         { 0, NULL },
 101 };
 102
 103 void
 104 ao_adc_single_init(void)
 105 {
 106 #ifdef AO_ADC_PIN0_PORT
 107         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 108 #endif
 109
 110 #ifdef AO_ADC_PIN0_PORT
 111         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 112 #endif
 113 #ifdef AO_ADC_PIN1_PORT
 114         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 115 #endif
 116 #ifdef AO_ADC_PIN2_PORT
 117         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 118 #endif
 119 #ifdef AO_ADC_PIN3_PORT
 120         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 121 #endif
 122 #ifdef AO_ADC_PIN4_PORT
 123         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 124 #endif
 125 #ifdef AO_ADC_PIN5_PORT
 126         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 127 #endif
 128 #ifdef AO_ADC_PIN6_PORT
 129         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 130 #endif
 131 #ifdef AO_ADC_PIN7_PORT
 132         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 133 #endif
 134 #ifdef AO_ADC_PIN8_PORT
 135         stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
 136 #endif
 137 #ifdef AO_ADC_PIN9_PORT
 138         stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
 139 #endif
 140 #ifdef AO_ADC_PIN10_PORT
 141         stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
 142 #endif
 143 #ifdef AO_ADC_PIN11_PORT
 144         stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
 145 #endif
 146 #ifdef AO_ADC_PIN12_PORT
 147         stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
 148 #endif
 149 #ifdef AO_ADC_PIN13_PORT
 150         stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
 151 #endif
 152 #ifdef AO_ADC_PIN14_PORT
 153         stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
 154 #endif
 155 #ifdef AO_ADC_PIN15_PORT
 156         stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
 157 #endif
 158 #ifdef AO_ADC_PIN16_PORT
 159         stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
 160 #endif
 161 #ifdef AO_ADC_PIN17_PORT
 162         stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
 163 #endif
 164 #ifdef AO_ADC_PIN18_PORT
 165         stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
 166 #endif
 167 #ifdef AO_ADC_PIN19_PORT
 168         stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
 169 #endif
 170 #ifdef AO_ADC_PIN20_PORT
 171         stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
 172 #endif
 173 #ifdef AO_ADC_PIN21_PORT
 174         stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
 175 #endif
 176 #ifdef AO_ADC_PIN22_PORT
 177         stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
 178 #endif
 179 #ifdef AO_ADC_PIN23_PORT
 180         stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
 181 #endif
 182 #ifdef AO_ADC_PIN24_PORT
 183         #error "Too many ADC ports"
 184 #endif
 185
 186         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
 187
 188         /* Turn off ADC during configuration */
 189         stm_adc.cr2 = 0;
 190
 191         stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
 192                        (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
 193                        (0 << STM_ADC_CR1_AWDEN ) |
 194                        (0 << STM_ADC_CR1_JAWDEN ) |
 195                        (0 << STM_ADC_CR1_PDI ) |
 196                        (0 << STM_ADC_CR1_PDD ) |
 197                        (0 << STM_ADC_CR1_DISCNUM ) |
 198                        (0 << STM_ADC_CR1_JDISCEN ) |
 199                        (0 << STM_ADC_CR1_DISCEN ) |
 200                        (0 << STM_ADC_CR1_JAUTO ) |
 201                        (0 << STM_ADC_CR1_AWDSGL ) |
 202                        (1 << STM_ADC_CR1_SCAN ) |
 203                        (0 << STM_ADC_CR1_JEOCIE ) |
 204                        (0 << STM_ADC_CR1_AWDIE ) |
 205                        (0 << STM_ADC_CR1_EOCIE ) |
 206                        (0 << STM_ADC_CR1_AWDCH ));
 207
 208         /* 384 cycle sample time for everyone */
 209         stm_adc.smpr1 = 0x3ffff;
 210         stm_adc.smpr2 = 0x3fffffff;
 211         stm_adc.smpr3 = 0x3fffffff;
 212
 213         stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
 214         stm_adc.sqr2 = 0;
 215         stm_adc.sqr3 = 0;
 216         stm_adc.sqr4 = 0;
 217         stm_adc.sqr5 = 0;
 218 #if AO_NUM_ADC > 0
 219         stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
 220 #endif
 221 #if AO_NUM_ADC > 1
 222         stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
 223 #endif
 224 #if AO_NUM_ADC > 2
 225         stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
 226 #endif
 227 #if AO_NUM_ADC > 3
 228         stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
 229 #endif
 230 #if AO_NUM_ADC > 4
 231         stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
 232 #endif
 233 #if AO_NUM_ADC > 5
 234         stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
 235 #endif
 236 #if AO_NUM_ADC > 6
 237         stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
 238 #endif
 239 #if AO_NUM_ADC > 7
 240         stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
 241 #endif
 242 #if AO_NUM_ADC > 8
 243         stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
 244 #endif
 245 #if AO_NUM_ADC > 9
 246         stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
 247 #endif
 248 #if AO_NUM_ADC > 10
 249         stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
 250 #endif
 251 #if AO_NUM_ADC > 11
 252         stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
 253 #endif
 254 #if AO_NUM_ADC > 12
 255         stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
 256 #endif
 257 #if AO_NUM_ADC > 13
 258         stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
 259 #endif
 260 #if AO_NUM_ADC > 14
 261         stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
 262 #endif
 263 #if AO_NUM_ADC > 15
 264         stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
 265 #endif
 266 #if AO_NUM_ADC > 16
 267         stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
 268 #endif
 269 #if AO_NUM_ADC > 17
 270         stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
 271 #endif
 272 #if AO_NUM_ADC > 18
 273 #error "need to finish stm_adc.sqr settings"
 274 #endif
 275
 276         /* Turn ADC on */
 277         stm_adc.cr2 = AO_ADC_CR2_VAL;
 278
 279         /* Wait for ADC to be ready */
 280         while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
 281                 ;
 282
 283 #ifndef HAS_ADC_TEMP
 284 #error Please define HAS_ADC_TEMP
 285 #endif
 286 #if HAS_ADC_TEMP
 287         stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
 288 #else
 289         stm_adc.ccr = 0;
 290 #endif
 291         /* Clear any stale status bits */
 292         stm_adc.sr = 0;
 293
 294         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
 295
 296         ao_cmd_register(&ao_adc_cmds[0]);
 297 }